[Bug target/95046] New: Vectorize V2SFmode operations

[Bug target/95046] New: Vectorize V2SFmode operations

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

            Bug ID: 95046
           Summary: Vectorize V2SFmode operations
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ubizjak at gmail dot com
  Target Milestone: ---

The compiler should vectorize V2SF operations using XMM registers.

The same principles as applied to integer MMX operations (mmx-with-sse) should
also apply to V2SF mode operations, but to avoid unwanted secondary effects
(e.g. exceptions) extra care should be taken to load values to registers with
parts outside V2SFmode cleared.

Following testcase:

--cut here--
float r[2], a[2], b[2];

void foo (void)
{
  for (int i = 0; i < 2; i++)
    r[i] = a[i] + b[i];
}
--cut here--

should vectorize to:

        movq    a(%rip), %xmm0
        movq    b(%rip), %xmm1
        addps   %xmm1, %xmm0
        movlps  %xmm0, r(%rip)

Please note movq insn that assures clearing of top 64bits of 128bit xmm
register.

[Bug target/95046] Vectorize V2SFmode operations

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2020-05-11
             Target|                            |x86_64
             Status|UNCONFIRMED                 |NEW
           Severity|normal                      |enhancement

[Bug target/95046] Vectorize V2SFmode operations

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
   Target Milestone|---                         |11.0
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail dot com

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:7c355156aa20eaec7401d7c66f6a6cfbe597abc2

commit r11-263-g7c355156aa20eaec7401d7c66f6a6cfbe597abc2
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Mon May 11 11:16:31 2020 +0200

    i386: Vectorize basic V2SFmode operations [PR94913]

    Enable V2SFmode vectorization and vectorize V2SFmode PLUS,
    MINUS, MULT, MIN and MAX operations using XMM registers.

    To avoid unwanted secondary effects (e.g. exceptions), load values
    to XMM registers using MOVQ that clears high bits of the XMM
    register outside V2SFmode.

    The compiler now vectorizes e.g.:

    float r[2], a[2], b[2];

    void
    test_plus (void)
    {
      for (int i = 0; i < 2; i++)
        r[i] = a[i] + b[i];
    }

    to:
            movq    a(%rip), %xmm0
            movq    b(%rip), %xmm1
            addps   %xmm1, %xmm0
            movlps  %xmm0, r(%rip)
            ret

    gcc/ChangeLog:

            PR target/95046
            * config/i386/i386.c (ix86_vector_mode_supported_p):
            Vectorize 3dNOW! vector modes for TARGET_MMX_WITH_SSE.
            * config/i386/mmx.md (*mov<mode>_internal): Do not set
            mode of alternative 13 to V2SF for TARGET_MMX_WITH_SSE.

            (mmx_addv2sf3): Change operand predicates from
            nonimmediate_operand to register_mmxmem_operand.
            (addv2sf3): New expander.
            (*mmx_addv2sf3): Add SSE/AVX alternatives.  Change operand
            predicates from nonimmediate_operand to register_mmxmem_operand.
            Enable instruction pattern for TARGET_MMX_WITH_SSE.

            (mmx_subv2sf3): Change operand predicate from
            nonimmediate_operand to register_mmxmem_operand.
            (mmx_subrv2sf3): Ditto.
            (subv2sf3): New expander.
            (*mmx_subv2sf3): Add SSE/AVX alternatives.  Change operand
            predicates from nonimmediate_operand to register_mmxmem_operand.
            Enable instruction pattern for TARGET_MMX_WITH_SSE.

            (mmx_mulv2sf3): Change operand predicates from
            nonimmediate_operand to register_mmxmem_operand.
            (mulv2sf3): New expander.
            (*mmx_mulv2sf3): Add SSE/AVX alternatives.  Change operand
            predicates from nonimmediate_operand to register_mmxmem_operand.
            Enable instruction pattern for TARGET_MMX_WITH_SSE.

            (mmx_<code>v2sf3): Change operand predicates from
            nonimmediate_operand to register_mmxmem_operand.
            (<code>v2sf3): New expander.
            (*mmx_<code>v2sf3): Add SSE/AVX alternatives.  Change operand
            predicates from nonimmediate_operand to register_mmxmem_operand.
            Enable instruction pattern for TARGET_MMX_WITH_SSE.
            (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-1.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:aa4317866bf3e9f42f3b8e3b1b1ec113ed1f818d

commit r11-270-gaa4317866bf3e9f42f3b8e3b1b1ec113ed1f818d
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Mon May 11 16:37:19 2020 +0200

    i386: Improve basic vectorized V2SFmode operations [PR95046]

    Use plain "v" constraint for AVX alternatives and add "prefix" attribute.

    gcc/ChangeLog:

            PR target/95046
            * config/i386/mmx.md (mmx_addv2sf3): Use "v" constraint
            instead of "Yv" for AVX alternatives.  Add "prefix" attribute.
            (*mmx_addv2sf3): Ditto.
            (*mmx_subv2sf3): Ditto.
            (*mmx_mulv2sf3): Ditto.
            (*mmx_<code>v2sf3): Ditto.
            (mmx_ieee_<ieee_maxmin>v2sf3): Ditto.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:2b2d298ff845ab7a07ffbd51da79473736da3324

commit r11-281-g2b2d298ff845ab7a07ffbd51da79473736da3324
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Mon May 11 20:12:14 2020 +0200

    i386: Add V2SFmode sqrt insn pattern [PR95046]

    gcc/ChangeLog:

    2020-05-11  Uroš Bizjak  <ubizjak@gmail.com>

            PR target/95046
            * config/i386/mmx.md (sqrtv2sf2): New insn pattern.

    testsuite/ChangeLog:

    2020-05-11  Uroš Bizjak  <ubizjak@gmail.com>

            PR target/95046
            * gcc.target/i386/pr95046-1.c (test_sqrt): Add.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:6416f67273aaeafd6ad89c2c82076dabb50f8dbe

commit r11-322-g6416f67273aaeafd6ad89c2c82076dabb50f8dbe
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue May 12 17:06:13 2020 +0200

    i386: Add V2SFmode NEG, ABS and logic insn patterns [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/mmx.md (<code>v2sf2): New insn pattern.
            (*mmx_<code>v2sf2): New insn_and_split pattern.
            (*mmx_nabsv2sf2): Ditto.
            (*mmx_andnotv2sf3): New insn pattern.
            (*mmx_<code>v2sf3): Ditto.
            * config/i386/i386.md (absneg_op): New code attribute.
            * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
            (ix86_build_signbit_mask): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-2.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:2a2dea6b63ae600eb1d084c06d8a3ba42c66dd6b

commit r11-323-g2a2dea6b63ae600eb1d084c06d8a3ba42c66dd6b
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue May 12 17:08:03 2020 +0200

    i386: Add V2SFmode NEG, ABS and logic insn patterns [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/mmx.md (<code>v2sf2): New insn pattern.
            (*mmx_<code>v2sf2): New insn_and_split pattern.
            (*mmx_nabsv2sf2): Ditto.
            (*mmx_andnotv2sf3): New insn pattern.
            (*mmx_<code>v2sf3): Ditto.
            * config/i386/i386.md (absneg_op): New code attribute.
            * config/i386/i386.c (ix86_build_const_vector): Handle V2SFmode.
            (ix86_build_signbit_mask): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-2.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:955b1f929906cabc5b17c40cbc7d767eebd64cc7

commit r11-331-g955b1f929906cabc5b17c40cbc7d767eebd64cc7
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue May 12 18:36:27 2020 +0200

    i386: Add V2SFmode FMA insn patterns [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/mmx.md (fmav2sf4): New insn pattern.
            (fmsv2sf4): Ditto.
            (fnmav2sf4): Ditto.
            (fnmsv2sf4): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-3.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:8a6790fb4e5090624fbd71e2b895e6bdd5319fd7

commit r11-332-g8a6790fb4e5090624fbd71e2b895e6bdd5319fd7
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue May 12 19:24:53 2020 +0200

    i386: Add V2SFmode copysign, xorsign and signbit expanders [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/mmx.md (copysignv2sf3): New expander.
            (xorsignv2sf3): Ditto.
            (signbitv2sf3): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-4.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:42ef8a5e662a765dc794a7a5c0227bcd83556e44

commit r11-379-g42ef8a5e662a765dc794a7a5c0227bcd83556e44
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu May 14 09:15:23 2020 +0200

    i386: Add V2SFmode conversion functions [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): rename from
mmx_pf2id.
            Add SSE/AVX alternative.  Change operand predicates from
            nonimmediate_operand to register_mmxmem_operand.
            Enable instruction pattern for TARGET_MMX_WITH_SSE.
            (fix_truncv2sfv2si2): New expander.
            (fixuns_truncv2sfv2si2): Ditto.

            (mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
            Add SSE/AVX alternative.  Change operand predicates from
            nonimmediate_operand to register_mmxmem_operand.
            Enable instruction pattern for TARGET_MMX_WITH_SSE.
            (floatv2siv2sf2): New expander.
            (floatunsv2siv2sf2): Ditto.

            * config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
            Update for rename.
            (IX86_BUILTIN_PI2FD): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-5.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:365e3cde4978c6a7dbfa50865720226254c016be

commit r11-386-g365e3cde4978c6a7dbfa50865720226254c016be
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu May 14 13:47:33 2020 +0200

    i386: Add V2DFmode conversion functions [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.

            (floatv2siv2df2): New expander.
            (floatunsv2siv2df2): New insn pattern.

            (fix_truncv2dfv2si2): New expander.
            (fixuns_truncv2dfv2si2): New insn pattern.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-6.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #10 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:9056cd80351c65c3b9a3257644236f2007c46a3f

commit r11-400-g9056cd80351c65c3b9a3257644236f2007c46a3f
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu May 14 19:51:40 2020 +0200

    i386: Add V2DFmode float trunc/extend functions [PR95046]

    gcc/ChangeLog:

            PR target/95046
            * config/i386/sse.md (truncv2dfv2df2): New insn pattern.
            (extendv2sfv2df2): Ditto.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-7.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:f4356120ba88c083dd5987376aab7590dd1e0e13

commit r11-409-gf4356120ba88c083dd5987376aab7590dd1e0e13
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 15 09:24:38 2020 +0200

    i386: Add V2SFmode hadd/hsub instructions [PR95046]

    PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative
    in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which
    implies SSE2.  These instructions are only generated via builtins, and
    since several 3dNow! insns have no corresponding SSE alternative,
    we can't avoid MMX registers with 3dNow! builtins anyway.

    Add SSE3/AVX alternatives to the insn pattern, so compiler will be able
    to use XMM registers when available, but don't prevent MMX registers,
    since they are needed when SSE3 is not active.

    Add additional generic insn patterns, used by the combiner to
    synthesize horizontal V2SFmode add/sub instructions.  These patterns
    are active for TARGET_MMX_WITH_SSE only, and use only XMM registers.

    gcc/ChangeLog:

            PR target/95046
            * config/i386/i386.md (isa): Add sse3_noavx.
            (enabled): Handle sse3_noavx.

            * config/i386/mmx.md (mmx_haddv2sf3): New expander.
            (*mmx_haddv2sf3): Rename from mmx_haddv2sf3.  Add SSE/AVX
            alternatives.  Match commutative vec_select selector operands.
            (*mmx_haddv2sf3_low): New insn pattern.

            (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
            (*mmx_hsubv2sf3_low): New insn pattern.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-8.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #12 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:f8b0665445bee8673b62c0a40ae257fe8c75a9b6

commit r11-410-gf8b0665445bee8673b62c0a40ae257fe8c75a9b6
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri May 15 10:02:00 2020 +0200

    i386: Add V2SFmode hadd/hsub instructions [PR95046]

    PFACC/PFNACC 3dNow! instructions got their corresponding SSE alternative
    in SSE3, so these can't be implemented with TARGET_MMX_WITH_SSE, which
    implies SSE2.  These instructions are only generated via builtins, and
    since several 3dNow! insns have no corresponding SSE alternative,
    we can't avoid MMX registers with 3dNow! builtins anyway.

    Add SSE3/AVX alternatives to the insn pattern, so compiler will be able
    to use XMM registers when available, but don't prevent MMX registers,
    since they are needed when SSE3 is not active.

    Add additional generic insn patterns, used by the combiner to
    synthesize horizontal V2SFmode add/sub instructions.  These patterns
    are active for TARGET_MMX_WITH_SSE only, and use only XMM registers.

    gcc/ChangeLog:

            PR target/95046
            * config/i386/i386.md (isa): Add sse3_noavx.
            (enabled): Handle sse3_noavx.

            * config/i386/mmx.md (mmx_haddv2sf3): New expander.
            (*mmx_haddv2sf3): Rename from mmx_haddv2sf3.  Add SSE/AVX
            alternatives.  Match commutative vec_select selector operands.
            (*mmx_haddv2sf3_low): New insn pattern.

            (*mmx_hsubv2sf3): Add SSE/AVX alternatives.
            (*mmx_hsubv2sf3_low): New insn pattern.

    testsuite/ChangeLog:

            PR target/95046
            * gcc.target/i386/pr95046-8.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #13 from Uroš Bizjak <ubizjak at gmail dot com> ---
Implemented for gcc-11.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #14 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:c60d9160b4d966dbea5b1bbea4f817c64d0bee2d

commit r12-1912-gc60d9160b4d966dbea5b1bbea4f817c64d0bee2d
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Jun 29 19:14:35 2021 +0200

    i386: Add V2SFmode vec_addsub pattern [PR95046]

    gcc/

    2021-06-21  Uroš Bizjak  <ubizjak@gmail.com>

            PR target/95046
            * config/i386/mmx.md (vec_addsubv2sf3): New insn pattern.

    gcc/testsuite/

    2021-06-21  Uroš Bizjak  <ubizjak@gmail.com>

            PR target/95046
            * gcc.target/i386/pr95046-9.c: New test.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #15 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:8f921393e339090566c1589d81009caa954de90d

commit r12-6113-g8f921393e339090566c1589d81009caa954de90d
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri Dec 24 17:09:36 2021 +0100

    i386: Add V2SFmode DIV insn pattern [PR95046, PR103797]

    Use V4SFmode "DIVPS X,Y" with [y0, y1, 1.0f, 1.0f] as a divisor
    to avoid division by zero.

    2021-12-24  Uroš Bizjak  <ubizjak@gmail.com>

    gcc/ChangeLog:

            PR target/95046
            PR target/103797
            * config/i386/mmx.md (divv2sf3): New instruction pattern.

    gcc/testsuite/ChangeLog:

            PR target/95046
            PR target/103797
            * gcc.target/i386/pr95046-1.c (test_div): Add.
            (dg-options): Add -mno-recip.

[Bug target/95046] Vectorize V2SFmode operations

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95046

--- Comment #16 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:e078de24eae8253fd4f24342f65166b525dd99c6

commit r12-6121-ge078de24eae8253fd4f24342f65166b525dd99c6
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Mon Dec 27 10:00:28 2021 +0100

    testsuite: Avoid unwanted vecorization [PR95046]

    2021-12-27  Uroš Bizjak  <ubizjak@gmail.com>

    gcc/testsuite/ChangeLog:

            PR target/95046
            * gfortran.dg/extract_recip_1.f: Adjust testcase.