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* [gcc(refs/users/meissner/heads/work053)] Revert patches.
@ 2021-05-25 5:14 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2021-05-25 5:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bf90a563930d303451ae3a4392656cf381d0f576
commit bf90a563930d303451ae3a4392656cf381d0f576
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 25 01:13:58 2021 -0400
Revert patches.
gcc/
2021-05-25 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraint.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with LXVKQ, it is easy.
(lxvkq_operand): New predicate.
* config/rs6000/rs6000-protos.h (lxvkq_constant_p): New
declaration.
* config/rs6000/rs6000-cpus.h (ISA_3_1_MASKS_SERVER): Add -mlxvkq.
(POWERPC_MASKS): Add -mlxvkq.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mlxvkq.
(lxvkq_constant_p): New function.
(rs6000_output_move_128bit): Add support for generating lxvkq.
(rs6000_opt_masks): Add -mlxvkq.
* config/rs6000/rs6000.opt (-mlxvkq): New option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support to
generate lxvkq.
(vsx_mov<mode>_32bit): Add support to generate lxvkq.
gcc/testsuite/
2021-05-20 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/float128-lxvkq.c: New test.
gcc/
2021-05-20 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mxxsplti32dx.
(xxsplti32dx_constant_float_p): New helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_opt_masks): Add -mxxsplti32dx.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
2021-05-20 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
count.
Diff:
---
gcc/config/rs6000/constraints.md | 11 --
gcc/config/rs6000/predicates.md | 32 ---
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000-protos.h | 3 -
gcc/config/rs6000/rs6000.c | 218 +--------------------
gcc/config/rs6000/rs6000.md | 67 ++-----
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 100 ++--------
gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c | 144 --------------
.../gcc.target/powerpc/vec-splat-constant-df.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-sf.c | 5 +-
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 10 +-
12 files changed, 42 insertions(+), 567 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d14ce98e9ac..e1fadd63580 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,12 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
(define_constraint "eF"
"A vector constant that can be loaded with the XXSPLTIDP instruction."
@@ -224,11 +218,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; KF/TF scalar than can be loaded with XVKQ
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "lxvkq_operand"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 0c17db42962..8c461ba2b76 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -606,16 +606,6 @@
if (xxspltidp_operand (op, mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded
- with that instruction. */
- if (lxvkq_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -694,25 +684,6 @@
return xxspltidp_constant_p (op, mode, &value);
})
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if
-;; the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
-;; Return 1 if the operand is an IEEE 128-bit special constant that can be
-;; loaded with the LXVKQ instruction.
-(define_predicate "lxvkq_operand"
- (match_code "const_double")
-{
- int immediate = 0;
- return lxvkq_constant_p (op, mode, &immediate);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -732,9 +703,6 @@
if (xxspltidp_operand (op, mode))
return true;
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index a9553129838..3b657e490b1 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -83,7 +83,6 @@
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS \
- | OPTION_MASK_LXVKQ \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
@@ -140,7 +139,6 @@
| OPTION_MASK_P10_FUSION_2LOGICAL \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
- | OPTION_MASK_LXVKQ \
| OPTION_MASK_MFCRF \
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index d71aef11bed..ea8ca6f8d95 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -33,9 +33,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
-extern bool lxvkq_constant_p (rtx, machine_mode, int *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a0586804625..bac28806a89 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4489,23 +4489,14 @@ rs6000_option_override_internal (bool global_init_p)
if (TARGET_POWER10 && TARGET_VSX)
{
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTI32DX) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTI32DX;
-
if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0)
rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_LXVKQ) == 0)
- rs6000_isa_flags |= OPTION_MASK_LXVKQ;
}
else
- rs6000_isa_flags &= ~(OPTION_MASK_LXVKQ
- | OPTION_MASK_XXSPLTIW
- | OPTION_MASK_XXSPLTIDP
- | OPTION_MASK_XXSPLTI32DX);
+ rs6000_isa_flags &= ~(OPTION_MASK_XXSPLTIW | OPTION_MASK_XXSPLTIDP);
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -6595,199 +6586,6 @@ xxspltidp_constant_p (rtx op,
return true;
}
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = value >> 32;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
-/* Return true if OP is of the given MODE is one of the 18 special values that
- can be generated with the LXVKQ instruction.
-
- Return the constant that will go in the LXVKQ instruction.
-
- The LXVKQ immediates are:
- 1 - 7: 1.0 .. 7.0.
- 8: Positive infinity.
- 9: Default quiet NaN.
- 16: -0.0.
- 17 - 23: -1.0 .. 7.0.
- 24: Negative infinity. */
-
-bool
-lxvkq_constant_p (rtx op,
- machine_mode mode,
- int *imm_p)
-{
- *imm_p = -1;
-
- if (!TARGET_LXVKQ)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return false;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- /* All of the values generated can be expressed as SFmode values, so if it
- doesn't fit in SFmode, exit. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- /* +/- Inifinity is 8/24. */
- if (REAL_VALUE_ISINF (*rv))
- {
- *imm_p = real_isneg (rv) ? 24 : 8;
- return true;
- }
-
- /* NaN is 9. */
- if (REAL_VALUE_ISNAN (*rv) && !REAL_VALUE_NEGATIVE (*rv))
- {
- *imm_p = 9;
- return true;
- }
-
- /* -0.0 is 16. */
- if (REAL_VALUE_MINUS_ZERO (*rv))
- {
- *imm_p = 16;
- return true;
- }
-
- /* The other values are all integers 1..7, and -1..-7. */
- if (!real_isinteger (rv, mode))
- return false;
-
- HOST_WIDE_INT value = real_to_integer (rv);
- if (value >= 1 && value <= 7)
- {
- *imm_p = value;
- return true;
- }
- else if (value >= -7 && value <= -1)
- {
- /* Subtraction is used because value is negative. */
- *imm_p = 16 - value;
- return true;
- }
-
- /* We can't load the value with LXVKQ. */
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6836,9 +6634,6 @@ output_vec_const_move (rtx *operands)
|| xxspltidp_operand (vec, mode))
return "#";
- if (xxsplti32dx_operand (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -13560,7 +13355,6 @@ rs6000_output_move_128bit (rtx operands[])
int src_regno;
bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
- int lxvkq_immediate = 0;
if (REG_P (dest))
{
@@ -13705,14 +13499,6 @@ rs6000_output_move_128bit (rtx operands[])
}
/* Constants. */
- else if (dest_vmx_p
- && CONST_DOUBLE_P (src)
- && lxvkq_constant_p (src, mode, &lxvkq_immediate))
- {
- operands[2] = GEN_INT (lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -24412,7 +24198,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "hard-dfp", OPTION_MASK_DFP, false, true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
- { "lxvkq", OPTION_MASK_LXVKQ, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
{ "mma", OPTION_MASK_MMA, false, true },
@@ -24440,7 +24225,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "xxsplti32dx", OPTION_MASK_XXSPLTI32DX, false, true },
{ "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
{ "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true },
#ifdef OPTION_MASK_64BIT
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1200c4db6a9..57bbe281cee 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7614,17 +7614,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0, eF"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7647,28 +7647,19 @@
mt%0 %1
mf%1 %0
nop
- #
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
+ *, *, *, *, p10")
(set_attr "prefixed"
"*, *, *, *, *, *,
*, *, *, *, *, *,
- *, *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *, yes")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -7928,18 +7919,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR XXSPLTIDP
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r, eF"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7957,33 +7948,24 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two, vecperm")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8, *")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
+ *, *, *, p10")
(set_attr "prefixed"
"*, *, *, *, *,
*, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *, yes")])
;; STW LWZ MR G-const H-const F-const
@@ -8010,19 +7992,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r, eF"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8045,34 +8027,23 @@
nop
mfvsrd %0,%x1
mtvsrd %x0,%1
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
+ *, p8v, p8v, p10")
(set_attr "prefixed"
"*, *, *, *, *,
*, *, *, *, *,
*, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, *, *, yes")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 5bf96209b83..03e7ed28634 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -635,11 +635,3 @@ Generate (do not generate) XXSPLTIW instructions.
mxxspltidp
Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags)
Generate (do not generate) XXSPLTIDP instructions.
-
-mxxsplti32dx
-Target Undocumented Mask(XXSPLTI32DX) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTI32DX instructions.
-
-mlxvkq
-Target Undocumented Mask(LXVKQ) Var(rs6000_isa_flags)
-Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index bc708113865..168e4c21af8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -388,7 +388,6 @@
UNSPEC_XXEVAL
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1189,17 +1188,17 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) LXVKQ
+;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?wa, v, <??r>, wZ, v, wa")
+ ?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ, eQ"))]
+ ?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1210,37 +1209,37 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecsimple, *, *, vecstore, vecload, vecsimple")
+ vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, 5, 2, *, *, *")
+ *, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *, *, *, *")
+ *, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, 20, 8, *, *, *")
+ *, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- <VSisa>, *, *, *, *, p10")])
+ <VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
-;; LVX (VMX) STVX (VMX) LXVKQ
+;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa, v, <??r>,
- wZ, v, wa")
+ wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM, W, <nW>,
- v, wZ, eQ"))]
+ v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1251,15 +1250,15 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple, *, *,
- vecstore, vecload, vecsimple")
+ vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *, 20, 16,
- *, *, *")
+ *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>, *, *,
- *, *, p10")])
+ *, *")])
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
@@ -6531,74 +6530,3 @@
"xxspltidp %x0,%1"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxspltib %x0,0
- xxspltib %x0,255
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c b/gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c
deleted file mode 100644
index a5cbe0b477f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-lxvkq.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
index 1435ef4ef4f..8f6e176f9af 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
@@ -48,16 +48,13 @@ scalar_double_m_inf (void) /* XXSPLTIDP. */
double
scalar_double_pi (void)
{
- return M_PI; /* 2x XXSPLTI32DX. */
+ return M_PI; /* PLFD. */
}
double
scalar_double_denorm (void)
{
- return 0x1p-149f; /* XXSPLTIB, XXSPLTI32DX. */
+ return 0x1p-149f; /* PLFD. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
index e9a45d5159d..72504bdfbbd 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
@@ -57,7 +57,4 @@ scalar_float_denorm (void)
return 0x1p-149f; /* PLFS. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
index d81198b163d..d509459292c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
@@ -51,16 +51,14 @@ v2df_double_m_inf (void)
vector double
v2df_double_pi (void)
{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
+ return (vector double) { M_PI, M_PI }; /* PLFD. */
}
vector double
v2df_double_denorm (void)
{
- return (vector double) { (double)0x1p-149f, /* XXSPLTIB, */
- (double)0x1p-149f }; /* XXSPLTI32DX. */
+ return (vector double) { (double)0x1p-149f,
+ (double)0x1p-149f }; /* PLFD. */
}
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work053)] Revert patches.
@ 2021-05-20 12:31 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2021-05-20 12:31 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ea543e401fafab119e97e82d0d02dadfca3a8dc0
commit ea543e401fafab119e97e82d0d02dadfca3a8dc0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu May 20 08:30:09 2021 -0400
Revert patches.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mxxsplti32dx.
(xxsplti32dx_constant_float_p): New helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_opt_masks): Add -mxxsplti32dx.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
count.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraints.md (eF): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the floating point constant is
easy.
(xxspltidp_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltidp support.
(POWERPC_MASKS): Add -mxxspltidp support.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltidp support.
(const_vector_element_all_same): New function.
(xxspltidp_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(rs6000_opt_masks): Add -mxxspltidp support.
(rs6000_emit_xxspltidp_v2df): Change function to implement the
XXSPLTIDP instruction.
* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
to UNSPEC_XXSPLTIDP to match the instruction.
(xxspltidp_v2df): Use 'use' for the expand arguments, instead of
writing out an insn.
(xxspltidp_v2df_inst): Delete.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal1): New define_insn_and_split.
(xxspltidp_<mode>_internal2): New define_insn.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Add
-mxxspltiw support.
(POWERPC_MASKS): Add -mxxspltiw support.
* config/rs6000/rs6000-protos.h (sign_extend_mode_constant): New
declaration.
(zero_extend_mode_constant); New declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltiw support.
(xxspltib_constant_p): If we can generate XXSPLTIW, don't generate
a XXSPLTIB and an extend instruction.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(rs6000_opt_masks): Add -mxxspltiw.
(sign_extend_mode_constant): New function.
(zero_extend_mode_constant): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
(xxspltiw_v8hi): New insn.
(xxspltiw_v4si): Rewrite to generate a vector constant.
(xxspltiw_v4sf): Rewrite to generate a vector constant.
(xxspltiw_v4si_inst): Delete.
(xxspltiw_v4sf_inst): Delete.
(xxspltiw_v8hi_dup): New insn.
(xxspltiw_v4si_dup): New insn.
(xxspltiw_v4sf_dup): New insn.
(XXSPLTIW): New mode iterator.
(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/pr86731-fwrapv.c: Turn off power10 code
generation.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 11 -
gcc/config/rs6000/predicates.md | 68 -----
gcc/config/rs6000/rs6000-cpus.def | 9 +-
gcc/config/rs6000/rs6000-protos.h | 6 -
gcc/config/rs6000/rs6000.c | 298 +--------------------
gcc/config/rs6000/rs6000.md | 81 ++----
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 275 +++----------------
gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c | 7 -
.../gcc.target/powerpc/vec-splat-constant-df.c | 63 -----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 63 -----
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 66 -----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 66 -----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 53 ----
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
16 files changed, 72 insertions(+), 1061 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d665e2a94db..561ce9797af 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,17 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
-;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
-(define_constraint "eF"
- "A vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "xxspltidp_operand"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index fc30b69018d..e21bc745f72 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,16 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (xxspltidp_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -650,55 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the
-;; XXSPLTIW instruction. Do not return 1 if the constant can be generated with
-;; XXSPLTIB or VSPLTIS{H,W}
-(define_predicate "xxspltiw_operand"
- (match_code "const_vector")
-{
- if (!TARGET_XXSPLTIW)
- return false;
-
- if (mode != V8HImode && mode != V4SImode && mode != V4SFmode)
- return false;
-
- rtx element = CONST_VECTOR_ELT (op, 0);
- for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i)))
- return false;
-
- if (element == CONST0_RTX (GET_MODE_INNER (mode)))
- return false;
-
- if (CONST_INT_P (element) && EASY_VECTOR_15 (INTVAL (element)))
- return false;
-
- return true;
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the
-;; value is 0.0, since that is easy to generate without using XXSPLTIDP.
-(define_predicate "xxspltidp_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- if (op == CONST0_RTX (mode))
- return false;
-
- HOST_WIDE_INT value = 0;
- return xxspltidp_constant_p (op, mode, &value);
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if
-;; the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -712,15 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (xxspltiw_operand (op, mode))
- return true;
-
- if (xxspltidp_operand (op, mode))
- return true;
-
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 3b657e490b1..cbbb42c1b3a 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -85,9 +85,7 @@
| OTHER_POWER10_MASKS \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
- | OPTION_MASK_P10_FUSION_2LOGICAL \
- | OPTION_MASK_XXSPLTIDP \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_P10_FUSION_2LOGICAL)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@@ -162,9 +160,8 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
- | OPTION_MASK_VSX \
- | OPTION_MASK_XXSPLTIDP \
- | OPTION_MASK_XXSPLTIW)
+ | OPTION_MASK_VSX)
+
#endif
/* This table occasionally claims that a processor does not support a
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 286f79143ef..c407034d58c 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,9 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
@@ -286,9 +283,6 @@ extern void rs6000_asm_output_dwarf_pcrel (FILE *file, int size,
extern void rs6000_asm_output_dwarf_datarel (FILE *file, int size,
const char *label);
extern long rs6000_const_f32_to_i32 (rtx operand);
-extern HOST_WIDE_INT sign_extend_mode_constant (machine_mode, HOST_WIDE_INT);
-extern unsigned HOST_WIDE_INT zero_extend_mode_constant (machine_mode,
- HOST_WIDE_INT);
/* Declare functions in rs6000-c.c */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 59660bda5f1..ef1ebaaee05 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4487,22 +4487,6 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
- if (TARGET_POWER10 && TARGET_VSX)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTI32DX) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTI32DX;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP;
- }
- else
- rs6000_isa_flags &= ~(OPTION_MASK_XXSPLTIW
- | OPTION_MASK_XXSPLTIDP
- | OPTION_MASK_XXSPLTI32DX);
-
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -6480,11 +6464,9 @@ xxspltib_constant_p (rtx op,
/* See if we could generate vspltisw/vspltish directly instead of xxspltib +
sign extend. Special case 0/-1 to allow getting any VSX register instead
- of an Altivec register. Also if we can generate a XXSPLTIW instruction,
- don't emit a XXSPLTIB and an extend instruction. */
- if ((mode == V4SImode || mode == V8HImode)
- && !IN_RANGE (value, -1, 0)
- && (EASY_VECTOR_15 (value) || TARGET_XXSPLTIW))
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
@@ -6501,209 +6483,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the element of a constant vector whose elements are all the same. In
- addition if VEC_DUPLICATE is used, return the element being duplicated. If
- neither is true, return NULL_RTX. */
-
-static rtx
-const_vector_element_all_same (rtx op)
-{
- if (GET_CODE (op) == VEC_DUPLICATE)
- {
- rtx element = XEXP (op, 0);
- return (CONST_INT_P (element) || CONST_DOUBLE_P (element)
- ? element
- : NULL_RTX);
- }
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- machine_mode mode = GET_MODE (op);
- size_t n_elts = GET_MODE_NUNITS (mode);
- rtx element = CONST_VECTOR_ELT (op, 0);
-
- for (size_t i = 1; i < n_elts; i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1)))
- return NULL_RTX;
-
- return element;
- }
-
- return NULL_RTX;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIDP instruction.
-
- Return the constant that is being split via CONSTANT_PTR to use in the
- XXSPLTIDP instruction. */
-
-bool
-xxspltidp_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- if (!TARGET_XXSPLTIDP)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- rtx element = op;
- if (mode == V2DFmode)
- {
- element = const_vector_element_all_same (op);
- if (!element)
- return false;
-
- mode = DFmode;
- }
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (GET_MODE (element) != mode)
- return false;
-
- if (!CONST_DOUBLE_P (element))
- return false;
-
- /* Don't return true for 0.0 since that is easy to create without
- XXSPLTIDP. */
- if (element == CONST0_RTX (mode))
- return false;
-
- /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- long value;
- REAL_VALUE_TO_TARGET_SINGLE (*rv, value);
-
- /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */
- if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0))
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = value >> 32;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6748,13 +6527,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_operand (vec, mode)
- || xxspltidp_operand (vec, mode))
- return "#";
-
- if (xxsplti32dx_operand (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -24346,9 +24118,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "xxsplti32dx", OPTION_MASK_XXSPLTI32DX, false, true },
- { "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
- { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
@@ -28188,7 +27957,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value)
inform (input_location,
"the result for the xxspltidp instruction "
"is undefined for subnormal input values");
- emit_insn (gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value)));
+ emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value)));
}
/* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */
@@ -28211,65 +27980,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-/* Sign extend integer values to a given mode. */
-HOST_WIDE_INT
-sign_extend_mode_constant (machine_mode mode, HOST_WIDE_INT value)
-{
- HOST_WIDE_INT mask1;
- HOST_WIDE_INT mask2;
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- case E_QImode:
- mask1 = HOST_WIDE_INT_C (0xff);
- mask2 = HOST_WIDE_INT_C (0x80);
- break;
-
- case E_HImode:
- mask1 = HOST_WIDE_INT_C (0xffff);
- mask2 = HOST_WIDE_INT_C (0x8000);
- break;
-
- case E_SImode:
- mask1 = HOST_WIDE_INT_C (0xffffffff);
- mask2 = HOST_WIDE_INT_C (0x80000000);
- break;
- }
-
- return (((value & mask1) ^ mask2) - mask2);
-}
-
-/* Zero extend integer values to a given mode. */
-unsigned HOST_WIDE_INT
-zero_extend_mode_constant (machine_mode mode, HOST_WIDE_INT value)
-{
- unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT) value;
- unsigned HOST_WIDE_INT mask;
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- case E_QImode:
- mask = HOST_WIDE_INT_UC (0xff);
- break;
-
- case E_HImode:
- mask = HOST_WIDE_INT_UC (0xffff);
- break;
-
- case E_SImode:
- mask = HOST_WIDE_INT_UC (0xffffffff);
- break;
- }
-
- return uvalue & mask;
-}
-
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1200c4db6a9..0c76338c734 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7614,17 +7614,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7646,29 +7646,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -7928,18 +7914,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7956,34 +7942,20 @@
#
#
#
- #
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8010,19 +7982,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8044,35 +8016,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 352d4a72ae4..2685fa71517 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -627,15 +627,3 @@ Enable instructions that guard against return-oriented programming attacks.
mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-
-mxxspltiw
-Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTIW instructions.
-
-mxxspltidp
-Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxsplti32dx
-Target Undocumented Mask(XXSPLTI32DX) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTI32DX instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 6b7972ca0f6..15a8c0e22d8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -386,9 +386,9 @@
UNSPEC_VDIVES
UNSPEC_VDIVEU
UNSPEC_XXEVAL
- UNSPEC_XXSPLTIDP
+ UNSPEC_XXSPLTIW
+ UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -6239,10 +6239,41 @@
"vmulld %0,%1,%2"
[(set_attr "type" "veccomplex")])
+;; XXSPLTIW built-in function support
+(define_insn "xxspltiw_v4si"
+ [(set (match_operand:V4SI 0 "register_operand" "=wa")
+ (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
+(define_expand "xxspltiw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+{
+ long long value = rs6000_const_f32_to_i32 (operands[1]);
+ emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
+ DONE;
+})
+
+(define_insn "xxspltiw_v4sf_inst"
+ [(set (match_operand:V4SF 0 "register_operand" "=wa")
+ (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIW))]
+ "TARGET_POWER10"
+ "xxspltiw %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTIDP built-in function support
(define_expand "xxspltidp_v2df"
- [(use (match_operand:V2DF 0 "register_operand" ))
- (use (match_operand:SF 1 "const_double_operand"))]
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
"TARGET_POWER10"
{
long value = rs6000_const_f32_to_i32 (operands[1]);
@@ -6250,6 +6281,15 @@
DONE;
})
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
@@ -6380,230 +6420,3 @@
[(set_attr "type" "vecsimple")
(set_attr "prefixed" "yes")])
-;; XXSPLTIW built-in function support. Convert to a vector constant, which
-;; will then be optimized to the XXSPLTIW instruction.
-(define_expand "xxspltiw_v4si"
- [(use (match_operand:V4SI 0 "register_operand"))
- (use (match_operand:SI 1 "s32bit_cint_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SImode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-(define_expand "xxspltiw_v4sf"
- [(use (match_operand:V4SF 0 "register_operand"))
- (use (match_operand:SF 1 "const_double_operand"))]
- "TARGET_POWER10"
-{
- rtx op1 = operands[1];
- rtvec rv = gen_rtvec (4, op1, op1, op1, op1);
- rtx vec_constant = gen_rtx_CONST_VECTOR (V4SFmode, rv);
- emit_move_insn (operands[0], vec_constant);
-})
-
-;; XXSPLTIW support. Add support for the XXSPLTIW built-in functions, and to
-;; use XXSPLTIW to load up vector V8HImode, V4SImode, and V4SFmode vector
-;; constants where all elements are the the same. We special case loading up
-;; integer -16..15 and floating point 0.0f, since we can use the shorter
-;; XXSPLTIB, VSPLTISH, and VSPLTISW instructions.
-
-(define_insn "*xxspltiw_v8hi_dup"
- [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V8HI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT value = INTVAL (operands[1]);
- unsigned HOST_WIDE_INT uns_value = zero_extend_mode_constant (HImode, value);
- HOST_WIDE_INT sign_value = sign_extend_mode_constant (HImode, uns_value);
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltish %0,%1";
- }
-
- /* The assembler doesn't like negative values. */
- HOST_WIDE_INT new_value = (uns_value << 16) | uns_value;
- operands[2] = GEN_INT (zero_extend_mode_constant (SImode, new_value));
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "*xxspltiw_v4si_dup"
- [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa")
- (vec_duplicate:V4SI
- (match_operand 1 "const_int_operand" "O,wM,wB,n")))]
- "TARGET_XXSPLTIW"
-{
- HOST_WIDE_INT value = INTVAL (operands[1]);
- unsigned HOST_WIDE_INT uns_value = zero_extend_mode_constant (SImode, value);
- HOST_WIDE_INT sign_value = sign_extend_mode_constant (SImode, uns_value);
-
- if (sign_value == 0)
- return "xxspltib %x0,0";
-
- if (sign_value == -1)
- return "xxspltib %x0,255";
-
- int r = reg_or_subregno (operands[0]);
- if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value))
- {
- operands[2] = GEN_INT (sign_value);
- return "vspltisw %0,%2";
- }
-
- /* The assembler doesn't like negative values. */
- operands[2] = GEN_INT (uns_value);
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,*,yes")])
-
-(define_insn "xxspltiw_v4sf_dup"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa")
- (vec_duplicate:V4SF
- (match_operand:SF 1 "const_double_operand" "O,F")))]
- "TARGET_XXSPLTIW"
-{
- if (operands[1] == CONST0_RTX (SFmode))
- return "xxspltib %x0,0";
-
- /* The assembler doesn't like negative values. */
- long value = rs6000_const_f32_to_i32 (operands[1]);
- operands[2] = GEN_INT (zero_extend_mode_constant (SImode, value));
- return "xxspltiw %x0,%2";
-}
- [(set_attr "type" "vecsimple")
- (set_attr "prefixed" "*,yes")])
-
-;; Convert vector constant to vec_duplicate.
-(define_mode_iterator XXSPLTIW [V8HI V4SI V4SF])
-
-(define_split
- [(set (match_operand:XXSPLTIW 0 "vsx_register_operand")
- (match_operand:XXSPLTIW 1 "xxspltiw_operand"))]
- "TARGET_XXSPLTIW && GET_CODE (operands[1]) == CONST_VECTOR"
- [(set (match_dup 0)
- (vec_duplicate:<MODE> (match_dup 2)))]
-{
- operands[2] = CONST_VECTOR_ELT (operands[1], 0);
-})
-
-;; Generate the XXSPLTIDP instruction to support SFmode and DFmode scalar
-;; constants and V2DF vector constants where both elements are the same. The
-;; constant has be expressible as a SFmode constant that is not a SFmode
-;; denormal value.
-(define_mode_iterator XXSPLTIDP [SF DF V2DF])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))]
- "TARGET_XXSPLTIDP"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; Just in case the user issued -mno-xxspltidp, allow the built-in function
-;; even if the compiler does not automatically generate XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal2"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxspltib %x0,0
- xxspltib %x0,255
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
index 8a00aaca70d..f312550f04d 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c
@@ -8,13 +8,6 @@
/* { dg-require-effective-target lp64 } */
/* { dg-options "-maltivec -O3 -fwrapv " } */
-/* If the compiler is generating power10 instructions, turn it off. Otherwise,
- it will generate a XXSPLTIW instruction instead of LXV/LXVD2X. */
-
-#ifdef _ARCH_PWR10
-#pragma GCC target ("cpu=power9")
-#endif
-
#include <altivec.h>
/* original test as reported. */
vector unsigned int splat(void)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 1435ef4ef4f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* XXSPLTIB, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index e9a45d5159d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index d81198b163d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f, /* XXSPLTIB, */
- (double)0x1p-149f }; /* XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 06830b02076..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 8 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 02d0c6d66a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index e6d0fab6d67..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index f49ef91422e..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,6 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
+
+
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work053)] Revert patches.
@ 2021-05-19 14:19 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2021-05-19 14:19 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ad044552c2c851234de386a2b1142fd5d99acd6b
commit ad044552c2c851234de386a2b1142fd5d99acd6b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed May 19 10:17:54 2021 -0400
Revert patches.
gcc/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(xxsplti32dx_operand): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
support for -mxxsplti32dx.
(xxsplti32dx_constant_float_p): New helper function.
(xxsplti32dx_constant_p): New function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_opt_masks): Add -mxxsplti32dx.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add support for
constants loaded with XXSPLTI32DX.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(XXSPLTI32DX): New mode iterator.
(xxsplti32dx_<mode>): New insn and splitter for XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insn.
(xxsplti32dx_<mode>_second): New insn.
gcc/testsuite/
2021-05-19 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-df.c: Update insn count.
* gcc.target/powerpc/vec-splat-constant-v2df.c: Update insn
count.
gcc/
2021-05-18 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* config/rs6000/constraints.md (eF): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the floating point constant is
easy.
(xxspltidp_operand): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mxxspltidp support.
(POWERPC_MASKS): Add -mxxspltidp support.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
declaration.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
-mxxspltidp support.
(const_vector_element_all_same): New function.
(xxspltidp_constant_p): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(rs6000_opt_masks): Add -mxxspltidp support.
(rs6000_emit_xxspltidp_v2df): Change function to implement the
XXSPLTIDP instruction.
* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
to UNSPEC_XXSPLTIDP to match the instruction.
(xxspltidp_v2df): Use 'use' for the expand arguments, instead of
writing out an insn.
(xxspltidp_v2df_inst): Delete.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal1): New define_insn_and_split.
(xxspltidp_<mode>_internal2): New define_insn.
gcc/testsuite/
2021-05-03 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 11 -
gcc/config/rs6000/predicates.md | 39 ----
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000-protos.h | 3 -
gcc/config/rs6000/rs6000.c | 233 +--------------------
gcc/config/rs6000/rs6000.md | 81 ++-----
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 124 ++---------
.../gcc.target/powerpc/vec-splat-constant-df.c | 63 ------
.../gcc.target/powerpc/vec-splat-constant-sf.c | 63 ------
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 66 ------
11 files changed, 38 insertions(+), 655 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d665e2a94db..561ce9797af 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,17 +208,6 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; SF/DF/V2DF/DI/V2DI scalar or vector constant that can be loaded with a pair
-;; of XXSPLTI32DX instructions.
-(define_constraint "eD"
- "A vector constant that can be loaded with XXSPLTI32DX instructions."
- (match_operand 0 "xxsplti32dx_operand"))
-
-;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP
-(define_constraint "eF"
- "A vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "xxspltidp_operand"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index fc30b69018d..bf678f429af 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,16 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (xxspltidp_operand (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can
- be loaded with a pair of those instructions. */
- if (xxsplti32dx_operand (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -676,29 +666,6 @@
return true;
})
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the
-;; value is 0.0, since that is easy to generate without using XXSPLTIDP.
-(define_predicate "xxspltidp_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- if (op == CONST0_RTX (mode))
- return false;
-
- HOST_WIDE_INT value = 0;
- return xxspltidp_constant_p (op, mode, &value);
-})
-
-;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be
-;; loaded via a pair f ISA 3.1 XXSPLTI32DX instructions. Do not return true if
-;; the value can be loaded with the XXSPLTIDP instruction or XXSPLTIB to load 0.
-(define_predicate "xxsplti32dx_operand"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- HOST_WIDE_INT high = 0, low = 0;
- return xxsplti32dx_constant_p (op, mode, &high, &low);
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -715,12 +682,6 @@
if (xxspltiw_operand (op, mode))
return true;
- if (xxspltidp_operand (op, mode))
- return true;
-
- if (xxsplti32dx_operand (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index 3b657e490b1..a21a95bc7aa 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -86,7 +86,6 @@
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
- | OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
/* Flags that need to be turned off if -mno-power9-vector. */
@@ -163,7 +162,6 @@
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_VSX \
- | OPTION_MASK_XXSPLTIDP \
| OPTION_MASK_XXSPLTIW)
#endif
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index ce1a2fd1473..c407034d58c 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,9 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern bool easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *);
-extern bool xxsplti32dx_constant_p (rtx, machine_mode, HOST_WIDE_INT *,
- HOST_WIDE_INT *);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7aca290918e..f0984e9fec5 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4487,21 +4487,11 @@ rs6000_option_override_internal (bool global_init_p)
if (!TARGET_PCREL && TARGET_PCREL_OPT)
rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
- if (TARGET_POWER10 && TARGET_VSX)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTI32DX) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTI32DX;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
-
- if ((rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIDP) == 0)
- rs6000_isa_flags |= OPTION_MASK_XXSPLTIDP;
- }
- else
- rs6000_isa_flags &= ~(OPTION_MASK_XXSPLTIW
- | OPTION_MASK_XXSPLTIDP
- | OPTION_MASK_XXSPLTI32DX);
+ if (TARGET_POWER10 && TARGET_VSX
+ && (rs6000_isa_flags_explicit & OPTION_MASK_XXSPLTIW) == 0)
+ rs6000_isa_flags |= OPTION_MASK_XXSPLTIW;
+ else if (!TARGET_POWER10 || !TARGET_VSX)
+ rs6000_isa_flags &= ~OPTION_MASK_XXSPLTIW;
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -6501,209 +6491,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the element of a constant vector whose elements are all the same. In
- addition if VEC_DUPLICATE is used, return the element being duplicated. If
- neither is true, return NULL_RTX. */
-
-static rtx
-const_vector_element_all_same (rtx op)
-{
- if (GET_CODE (op) == VEC_DUPLICATE)
- {
- rtx element = XEXP (op, 0);
- return (CONST_INT_P (element) || CONST_DOUBLE_P (element)
- ? element
- : NULL_RTX);
- }
-
- else if (GET_CODE (op) == CONST_VECTOR)
- {
- machine_mode mode = GET_MODE (op);
- size_t n_elts = GET_MODE_NUNITS (mode);
- rtx element = CONST_VECTOR_ELT (op, 0);
-
- for (size_t i = 1; i < n_elts; i++)
- if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1)))
- return NULL_RTX;
-
- return element;
- }
-
- return NULL_RTX;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTIDP instruction.
-
- Return the constant that is being split via CONSTANT_PTR to use in the
- XXSPLTIDP instruction. */
-
-bool
-xxspltidp_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *constant_ptr)
-{
- *constant_ptr = 0;
-
- if (!TARGET_XXSPLTIDP)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- rtx element = op;
- if (mode == V2DFmode)
- {
- element = const_vector_element_all_same (op);
- if (!element)
- return false;
-
- mode = DFmode;
- }
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (GET_MODE (element) != mode)
- return false;
-
- if (!CONST_DOUBLE_P (element))
- return false;
-
- /* Don't return true for 0.0 since that is easy to create without
- XXSPLTIDP. */
- if (element == CONST0_RTX (mode))
- return false;
-
- /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element);
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- long value;
- REAL_VALUE_TO_TARGET_SINGLE (*rv, value);
-
- /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */
- if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0))
- return false;
-
- *constant_ptr = value;
- return true;
-}
-
-/* Return true if OP is a floating point constant that can be loaded with the
- XXSPLTI32DX instruction. If the constant can be loaded with the simpler
- XXSPLTIDP (constants that can fit as SFmode constants) or XXSPLTIB (0.0)
- instructions, return false.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-static bool
-xxsplti32dx_constant_float_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- HOST_WIDE_INT xxspltidp_value = 0;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- if (mode != SFmode && mode != DFmode)
- return false;
-
- if (op == CONST0_RTX (mode))
- return false;
-
- if (xxspltidp_constant_p (op, mode, &xxspltidp_value))
- return false;
-
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to undo
- this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0];
- *low_ptr = high_low[1];
- return true;
-}
-
-/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1
- XXSPLTI32DX instruction. If the instruction can be synthesized with
- XXSPLTIDP or is 0/-1, return false.
-
- We handle the following types of constants:
-
- 1) vector double constants where each element is the same and you can't
- load the constant with XXSPLTIDP;
-
- 2) vector long long constants where each element is the same;
-
- 3) Scalar floating point constants that can't be loaded with XXSPLTIDP.
-
- Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-bool
-xxsplti32dx_constant_p (rtx op,
- machine_mode mode,
- HOST_WIDE_INT *high_ptr,
- HOST_WIDE_INT *low_ptr)
-{
- *high_ptr = *low_ptr = 0;
-
- if (!TARGET_XXSPLTI32DX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (op == CONST0_RTX (mode))
- return false;
-
- switch (mode)
- {
- default:
- break;
-
- case E_V2DFmode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- return xxsplti32dx_constant_float_p (ele, DFmode, high_ptr, low_ptr);
- }
-
- case E_SFmode:
- case E_DFmode:
- return xxsplti32dx_constant_float_p (op, mode, high_ptr, low_ptr);
-
- case E_V2DImode:
- {
- rtx ele = const_vector_element_all_same (op);
- if (!ele)
- return false;
-
- /* If we can generate XXSPLTIB and VEXTSB2D, don't return true. */
- HOST_WIDE_INT value = INTVAL (ele);
- if (IN_RANGE (value, -128, 127))
- return false;
-
- *high_ptr = value >> 32;
- *low_ptr = value & 0xffffffff;
- return true;
- }
- }
-
- return false;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -6748,11 +6535,7 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (xxspltiw_operand (vec, mode)
- || xxspltidp_operand (vec, mode))
- return "#";
-
- if (xxsplti32dx_operand (vec, mode))
+ if (xxspltiw_operand (vec, mode))
return "#";
if (TARGET_P9_VECTOR
@@ -24346,9 +24129,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "string", 0, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "xxsplti32dx", OPTION_MASK_XXSPLTI32DX, false, true },
{ "xxspltiw", OPTION_MASK_XXSPLTIW, false, true },
- { "xxspltidp", OPTION_MASK_XXSPLTIDP, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
{ "aix64", OPTION_MASK_64BIT, false, false },
@@ -28188,7 +27969,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value)
inform (input_location,
"the result for the xxspltidp instruction "
"is undefined for subnormal input values");
- emit_insn (gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value)));
+ emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value)));
}
/* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1200c4db6a9..0c76338c734 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7614,17 +7614,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7646,29 +7646,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -7928,18 +7914,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7956,34 +7942,20 @@
#
#
#
- #
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8010,19 +7982,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8044,35 +8016,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "prefixed"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, yes, yes")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 352d4a72ae4..5e282d3741c 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -631,11 +631,3 @@ Generate code that will run in privileged state.
mxxspltiw
Target Undocumented Mask(XXSPLTIW) Var(rs6000_isa_flags)
Generate (do not generate) XXSPLTIW instructions.
-
-mxxspltidp
-Target Undocumented Mask(XXSPLTIDP) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxsplti32dx
-Target Undocumented Mask(XXSPLTI32DX) Var(rs6000_isa_flags)
-Generate (do not generate) XXSPLTI32DX instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 5ef2203c4b8..c850864c7ad 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -386,9 +386,8 @@
UNSPEC_VDIVES
UNSPEC_VDIVEU
UNSPEC_XXEVAL
- UNSPEC_XXSPLTIDP
+ UNSPEC_XXSPLTID
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -6241,8 +6240,9 @@
;; XXSPLTIDP built-in function support
(define_expand "xxspltidp_v2df"
- [(use (match_operand:V2DF 0 "register_operand" ))
- (use (match_operand:SF 1 "const_double_operand"))]
+ [(set (match_operand:V2DF 0 "register_operand" )
+ (unspec:V2DF [(match_operand:SF 1 "const_double_operand")]
+ UNSPEC_XXSPLTID))]
"TARGET_POWER10"
{
long value = rs6000_const_f32_to_i32 (operands[1]);
@@ -6250,6 +6250,15 @@
DONE;
})
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTID))]
+ "TARGET_POWER10"
+ "xxspltidp %x0,%1"
+ [(set_attr "type" "vecsimple")
+ (set_attr "prefixed" "yes")])
+
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
@@ -6475,110 +6484,3 @@
{
operands[2] = CONST_VECTOR_ELT (operands[1], 0);
})
-
-;; Generate the XXSPLTIDP instruction to support SFmode and DFmode scalar
-;; constants and V2DF vector constants where both elements are the same. The
-;; constant has be expressible as a SFmode constant that is not a SFmode
-;; denormal value.
-(define_mode_iterator XXSPLTIDP [SF DF V2DF])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))]
- "TARGET_XXSPLTIDP"
- "#"
- "&& 1"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- HOST_WIDE_INT value = 0;
-
- if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (value);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; Just in case the user issued -mno-xxspltidp, allow the built-in function
-;; even if the compiler does not automatically generate XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal2"
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [SF DF V2DF V2DI])
-
-(define_insn_and_split "*xxsplti32dx_<mode>"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTI32DX 1 "xxsplti32dx_operand"))]
- "TARGET_XXSPLTI32DX"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high = 0, low = 0;
-
- if (!xxsplti32dx_constant_p (operands[1], <MODE>mode, &high, &low))
- gcc_unreachable ();
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB instruction instead the first XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")
- (set_attr "num_insns" "2")
- (set_attr "max_prefixed_insns" "2")])
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxspltib %x0,0
- xxspltib %x0,255
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 1435ef4ef4f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* XXSPLTIB, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplfd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index e9a45d5159d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mplfs\M} } } */
-/* { dg-final { scan-assembler-not {\mplxssp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index d81198b163d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* 2x XXSPLTI32DX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f, /* XXSPLTIB, */
- (double)0x1p-149f }; /* XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work053)] Revert patches.
@ 2021-05-18 16:07 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2021-05-18 16:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a4b585ccb8716c376d2707659264d38b284b71f3
commit a4b585ccb8716c376d2707659264d38b284b71f3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 18 12:06:15 2021 -0400
Revert patches.
gcc/testsuite/
2021-05-18 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR testsuite/100166
* gcc.dg/pr56727-2.c:
* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c:
* gcc.target/powerpc/fold-vec-div-longlong.c:
* gcc.target/powerpc/fold-vec-mult-longlong.c:
* gcc.target/powerpc/ppc-eq0-1.c:
* gcc.target/powerpc/ppc-ne0-1.c:
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn counts
to allow the test to run when generating code for power10.
gcc/testsuite/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch.
PR testsuite/100166
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c:
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c:
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c:
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c:
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c:
* gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c:
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c:
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c:
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c:
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c:
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c:
* gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c:
* gcc.target/powerpc/fold-vec-load-vec_xl-char.c:
* gcc.target/powerpc/fold-vec-load-vec_xl-double.c:
* gcc.target/powerpc/fold-vec-load-vec_xl-float.c:
* gcc.target/powerpc/fold-vec-load-vec_xl-int.c:
* gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c:
* gcc.target/powerpc/fold-vec-load-vec_xl-short.c:
* gcc.target/powerpc/fold-vec-splat-floatdouble.c:
* gcc.target/powerpc/fold-vec-splat-longlong.c:
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c:
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c:
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c:
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c:
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c:
* gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c:
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c:
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c:
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c:
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c:
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c:
* gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c:
* gcc.target/powerpc/fold-vec-store-vec_xst-char.c:
* gcc.target/powerpc/fold-vec-store-vec_xst-double.c:
* gcc.target/powerpc/fold-vec-store-vec_xst-float.c:
* gcc.target/powerpc/fold-vec-store-vec_xst-int.c:
* gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c:
* gcc.target/powerpc/fold-vec-store-vec_xst-short.c:
* gcc.target/powerpc/lvsl-lvsr.c: Update insn counts to account
for power10 code generation.
---
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c | 2 +-
.../powerpc/fold-vec-load-builtin_vec_xl-double.c | 2 +-
.../powerpc/fold-vec-load-builtin_vec_xl-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c | 2 +-
.../powerpc/fold-vec-load-builtin_vec_xl-longlong.c | 2 +-
.../powerpc/fold-vec-load-builtin_vec_xl-short.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_xl-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_xl-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_xl-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_xl-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_xl-short.c | 2 +-
.../gcc.target/powerpc/fold-vec-splat-floatdouble.c | 7 ++++---
gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c | 2 +-
.../powerpc/fold-vec-store-builtin_vec_xst-char.c | 2 +-
.../powerpc/fold-vec-store-builtin_vec_xst-double.c | 2 +-
.../powerpc/fold-vec-store-builtin_vec_xst-float.c | 2 +-
.../powerpc/fold-vec-store-builtin_vec_xst-int.c | 2 +-
.../powerpc/fold-vec-store-builtin_vec_xst-longlong.c | 2 +-
.../powerpc/fold-vec-store-builtin_vec_xst-short.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c | 2 +-
.../powerpc/fold-vec-store-vec_vsx_st-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c | 2 +-
39 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 9b199c219bf..104710700c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char);
BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
index c49dfe8d95b..bfb3cfbc081 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector double, signed long long, vector double);
BUILD_VAR_TEST( test5, vector double, signed int, vector double);
BUILD_CST_TEST( test6, vector double, 12, vector double);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c
index cdded361b12..373bead2e60 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector float, signed long long, vector float);
BUILD_VAR_TEST( test5, vector float, signed int, vector float);
BUILD_CST_TEST( test6, vector float, 12, vector float);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c
index bc18bebb1d6..744b96780f1 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int);
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c
index 66e953a2fbc..249b3eb8cff 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long);
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c
index 0ef1c590d94..997f6f89a9d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigne
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short);
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c
index 0b76341b1de..6aae43583f6 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c
@@ -35,5 +35,5 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char);
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c
index beb6d037a6b..b3f3b7fcd07 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test4, vector double, int, vector double);
BUILD_VAR_TEST( test5, vector double, long long, vector double);
BUILD_CST_TEST( test6, vector double, 12, vector double);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c
index 5f9b6d35830..56cbe9ad102 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test5, vector float, signed long long, vector float);
BUILD_VAR_TEST( test7, vector float, signed int, vector float);
BUILD_CST_TEST( test8, vector float, 12, vector float);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c
index a59f52fbb1e..2cde9f5b6dd 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int);
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c
index 5c121fa26bd..cf2b7f9b5bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long);
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c
index 07154d811a1..cfc0e307d80 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigne
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short);
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c
index 04c4f31deef..7281b3cca7a 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, unsigned char);
BUILD_VAR_TEST( test11, vector unsigned char, signed int, unsigned char);
BUILD_CST_TEST( test12, vector unsigned char, 12, unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c
index 1958d65be89..3f3d985c45b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector double, signed long long, double);
BUILD_VAR_TEST( test5, vector double, signed int, double);
BUILD_CST_TEST( test6, vector double, 12, double);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c
index 5578138d2f1..eafe3053771 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test4, vector float, signed long long, vector float);
BUILD_VAR_TEST( test5, vector float, signed int, vector float);
BUILD_CST_TEST( test6, vector float, 12, vector float);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c
index 8ba880ea61f..a2267218af9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int);
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c
index 6df3c79fd1b..f2e5469ab74 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long);
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c
index c5088ab177e..2d64b4f11d2 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigne
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short);
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
index ab396967c3d..76619177388 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
@@ -20,11 +20,12 @@ vector double testd_01 (vector double x) { return vec_splat (x, 0b00001); }
vector double test_dc ()
{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00010); }
-/* If the source vector is a known constant, we will generate a load. */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 2 } } */
+/* If the source vector is a known constant, we will generate a load or possibly
+ XXSPLTIW. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M|\mxxspltiw\M} 2 } } */
/* For float types, we generate a splat. */
-/* { dg-final { scan-assembler-times "vspltw|xxspltw" 3 } } */
+/* { dg-final { scan-assembler-times {\mvspltw\M|\mxxspltw\M} 3 } } */
/* For double types, we will generate xxpermdi instructions. */
/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
index 4fa06c85ecc..b95b987abce 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
@@ -25,7 +25,7 @@ vector signed long long test_sll () { const vector signed long long y = {34, 45}
vector unsigned long long test_ull () { const vector unsigned long long y = {56, 67}; return vec_splat (y, 0b00010); }
/* Assorted load instructions for the initialization with known constants. */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M} 3 } } */
/* xxpermdi for vec_splat of long long vectors.
At the time of this writing, the number of xxpermdi instructions
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
index d1100d01a83..162563caed4 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char );
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c
index 74e34c307fd..c42a720d361 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector double, signed long long, double );
BUILD_VAR_TEST( test5, vector double, signed int, double );
BUILD_CST_TEST( test6, vector double, 12, double );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c
index db6bd331829..b200c47fd2f 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector float, signed long long, vector float );
BUILD_VAR_TEST( test5, vector float, signed int, vector float );
BUILD_CST_TEST( test6, vector float, 12, vector float );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c
index 2a328897cbb..d9848820b3a 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int );
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c
index a62ca516f95..bb72d9b2a99 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long );
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c
index 2b1e1c0b90e..f4dbb702583 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short );
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c
index 82bb891a9c9..ae5cf8ef0b4 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char );
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c
index 34772cfe135..1360f4d4ce9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test7, vector double, signed long long, vector double );
BUILD_VAR_TEST( test8, vector double, signed int, vector double );
BUILD_CST_TEST( test9, vector double, 12, vector double );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c
index cf13f2a7ec1..1b70f2a80f7 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test7, vector float, signed long long, vector float );
BUILD_VAR_TEST( test8, vector float, signed int, vector float );
BUILD_CST_TEST( test9, vector float, 12, vector float );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c
index a9e189ddadd..4e4a499eaad 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int );
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c
index f50e2b93da1..b57c126b9ab 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector unsi
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long );
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c
index 0f8a93ad371..7593f425258 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short );
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c
index 4f5930aa909..fdd2ed5648d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char );
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c
index 511d5fe7299..62f8552fdde 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test7, vector double, signed long long, vector double );
BUILD_VAR_TEST( test8, vector double, signed int, vector double );
BUILD_CST_TEST( test9, vector double, 12, vector double );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c
index 13e6cb6e7af..ad15a5a2b51 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test7, vector float, signed long long, vector float );
BUILD_VAR_TEST( test8, vector float, signed int, vector float );
BUILD_CST_TEST( test9, vector float, 12, vector float );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c
index fd6ff78509b..abe93dfb235 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int );
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c
index a669481b0d8..6859593bf0a 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector unsi
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long );
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c
index 78eae57fb23..6c54873db20 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short );
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
index 93843c09f35..26aadbcbc63 100644
--- a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
+++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
@@ -6,7 +6,7 @@
/* { dg-options "-O0 -Wno-deprecated" } */
/* { dg-final { scan-assembler-times "lvsl" 2 } } */
/* { dg-final { scan-assembler-times "lvsr" 2 } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mp?lxv\M} 2 } } */
/* { dg-final { scan-assembler-times {\m(?:v|xx)permr?\M} 2 } } */
--
2.31.1
---
gcc/testsuite/gcc.dg/pr56727-2.c | 2 +-
.../vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 +++++++
gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 7 +++++++
gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c | 8 ++++++++
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 2 +-
7 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index c54369ed25e..77fdf4bc350 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } } */
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* && ilp32 } } } } */
-/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-final { scan-assembler "(bl f\n\\s*nop)|(bl f@notoc)" { target { powerpc*-*-linux* && lp64 } } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index 246f38fa6d1..d9f173b521e 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv|plxv|pstxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* } } } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index 312e984d3cc..1d20b7ff100 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -6,6 +6,13 @@
/* { dg-require-effective-target lp64 } */
/* { dg-options "-mvsx -O2" } */
+/* If the compiler was configured to automatically generate power10 support with
+ --with-cpu=power10, turn it off. Otherwise, it will generate VDIVSD and
+ VDIVUD instructions. */
+#ifdef _ARCH_PWR10
+#pragma GCC target ("cpu=power9")
+#endif
+
#include <altivec.h>
vector signed long long
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
index 38dba9f5023..7510dc5c7a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
@@ -6,6 +6,13 @@
/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
+/* If the compiler was configured to automatically generate power10 support with
+ --with-cpu=power10, turn it off. Otherwise, it will generate VMULLD
+ instructions. */
+#ifdef _ARCH_PWR10
+#pragma GCC target ("cpu=power9")
+#endif
+
#include <altivec.h>
vector signed long long
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
index 496a6e340c0..2ddf03117ab 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
@@ -7,4 +7,4 @@ int foo(int x)
return x == 0;
}
-/* { dg-final { scan-assembler "cntlzw|isel" } } */
+/* { dg-final { scan-assembler "cntlzw|isel|setbc" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
index 63c4b6087df..bf777979833 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
@@ -2,6 +2,14 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mno-isel" } */
+/* If the compiler was configured to automatically generate power10 support with
+ --with-cpu=power10, turn it off. Otherwise, it will generate a SETBCR
+ instruction instead of ADDIC/SUBFE. */
+
+#ifdef _ARCH_PWR10
+#pragma GCC target ("cpu=power9")
+#endif
+
/* { dg-final { scan-assembler-times "addic" 4 } } */
/* { dg-final { scan-assembler-times "subfe" 1 } } */
/* { dg-final { scan-assembler-times "addze" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index 1269fe635c6..d5ed700b9bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -30,5 +30,5 @@ vector signed long long splats4(void)
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M|\mplvx\M} 2 } } */
--
2.31.1
Diff:
---
gcc/testsuite/gcc.dg/pr56727-2.c | 2 +-
.../gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 -------
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 7 -------
gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c | 7 +++----
gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c | 2 +-
.../gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c | 2 +-
gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c | 2 +-
gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c | 2 +-
gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c | 8 --------
gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c | 2 +-
46 files changed, 45 insertions(+), 68 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/pr56727-2.c b/gcc/testsuite/gcc.dg/pr56727-2.c
index 77fdf4bc350..c54369ed25e 100644
--- a/gcc/testsuite/gcc.dg/pr56727-2.c
+++ b/gcc/testsuite/gcc.dg/pr56727-2.c
@@ -18,4 +18,4 @@ void h ()
/* { dg-final { scan-assembler "@(PLT|plt)" { target i?86-*-* x86_64-*-* } } } */
/* { dg-final { scan-assembler "@(PLT|plt)" { target { powerpc*-*-linux* && ilp32 } } } } */
-/* { dg-final { scan-assembler "(bl f\n\\s*nop)|(bl f@notoc)" { target { powerpc*-*-linux* && lp64 } } } } */
+/* { dg-final { scan-assembler "bl f\n\\s*nop" { target { powerpc*-*-linux* && lp64 } } } } */
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
index d9f173b521e..246f38fa6d1 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a-pr63175.c
@@ -25,6 +25,6 @@ main1 (void)
with no word loads (lw, lwu, lwz, lwzu, or their indexed forms)
or word stores (stw, stwu, stwx, stwux, or their indexed forms). */
-/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv|plxv|pstxv)" } } */
+/* { dg-final { scan-assembler "\t(lvx|lxv|lvsr|stxv)" } } */
/* { dg-final { scan-assembler-not "\tlwz?u?x? " { xfail { powerpc-ibm-aix* } } } } */
/* { dg-final { scan-assembler-not "\tstwu?x? " } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
index 1d20b7ff100..312e984d3cc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
@@ -6,13 +6,6 @@
/* { dg-require-effective-target lp64 } */
/* { dg-options "-mvsx -O2" } */
-/* If the compiler was configured to automatically generate power10 support with
- --with-cpu=power10, turn it off. Otherwise, it will generate VDIVSD and
- VDIVUD instructions. */
-#ifdef _ARCH_PWR10
-#pragma GCC target ("cpu=power9")
-#endif
-
#include <altivec.h>
vector signed long long
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
index 104710700c8..9b199c219bf 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char);
BUILD_CST_TEST( test12, vector unsigned char, 8, vector unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
index bfb3cfbc081..c49dfe8d95b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector double, signed long long, vector double);
BUILD_VAR_TEST( test5, vector double, signed int, vector double);
BUILD_CST_TEST( test6, vector double, 12, vector double);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c
index 373bead2e60..cdded361b12 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-float.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector float, signed long long, vector float);
BUILD_VAR_TEST( test5, vector float, signed int, vector float);
BUILD_CST_TEST( test6, vector float, 12, vector float);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c
index 744b96780f1..bc18bebb1d6 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-int.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int);
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c
index 249b3eb8cff..66e953a2fbc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-longlong.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long);
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c
index 997f6f89a9d..0ef1c590d94 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-builtin_vec_xl-short.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigne
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short);
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c
index 6aae43583f6..0b76341b1de 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-char.c
@@ -35,5 +35,5 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char);
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c
index b3f3b7fcd07..beb6d037a6b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-double.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test4, vector double, int, vector double);
BUILD_VAR_TEST( test5, vector double, long long, vector double);
BUILD_CST_TEST( test6, vector double, 12, vector double);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c
index 56cbe9ad102..5f9b6d35830 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-float.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test5, vector float, signed long long, vector float);
BUILD_VAR_TEST( test7, vector float, signed int, vector float);
BUILD_CST_TEST( test8, vector float, 12, vector float);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c
index 2cde9f5b6dd..a59f52fbb1e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-int.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int);
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c
index cf2b7f9b5bc..5c121fa26bd 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-longlong.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long);
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c
index cfc0e307d80..07154d811a1 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_vsx_ld-short.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigne
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short);
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c
index 7281b3cca7a..04c4f31deef 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-char.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, unsigned char);
BUILD_VAR_TEST( test11, vector unsigned char, signed int, unsigned char);
BUILD_CST_TEST( test12, vector unsigned char, 12, unsigned char);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c
index 3f3d985c45b..1958d65be89 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector double, signed long long, double);
BUILD_VAR_TEST( test5, vector double, signed int, double);
BUILD_CST_TEST( test6, vector double, 12, double);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c
index eafe3053771..5578138d2f1 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-float.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test4, vector float, signed long long, vector float);
BUILD_VAR_TEST( test5, vector float, signed int, vector float);
BUILD_CST_TEST( test6, vector float, 12, vector float);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c
index a2267218af9..8ba880ea61f 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-int.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int);
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c
index f2e5469ab74..6df3c79fd1b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-longlong.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long);
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long);
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c
index 2d64b4f11d2..c5088ab177e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-load-vec_xl-short.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigne
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short);
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short);
-/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M|\mplxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mlxvw4x\M|\mlxvd2x\M|\mlxvx\M|\mlvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
index 7510dc5c7a7..38dba9f5023 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c
@@ -6,13 +6,6 @@
/* { dg-options "-maltivec -mvsx -mpower8-vector" } */
/* { dg-additional-options "-maix64" { target powerpc-ibm-aix* } } */
-/* If the compiler was configured to automatically generate power10 support with
- --with-cpu=power10, turn it off. Otherwise, it will generate VMULLD
- instructions. */
-#ifdef _ARCH_PWR10
-#pragma GCC target ("cpu=power9")
-#endif
-
#include <altivec.h>
vector signed long long
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
index 76619177388..ab396967c3d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-floatdouble.c
@@ -20,12 +20,11 @@ vector double testd_01 (vector double x) { return vec_splat (x, 0b00001); }
vector double test_dc ()
{ const vector double y = { 3.0, 5.0 }; return vec_splat (y, 0b00010); }
-/* If the source vector is a known constant, we will generate a load or possibly
- XXSPLTIW. */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M|\mxxspltiw\M} 2 } } */
+/* If the source vector is a known constant, we will generate a load. */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 2 } } */
/* For float types, we generate a splat. */
-/* { dg-final { scan-assembler-times {\mvspltw\M|\mxxspltw\M} 3 } } */
+/* { dg-final { scan-assembler-times "vspltw|xxspltw" 3 } } */
/* For double types, we will generate xxpermdi instructions. */
/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
index b95b987abce..4fa06c85ecc 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-splat-longlong.c
@@ -25,7 +25,7 @@ vector signed long long test_sll () { const vector signed long long y = {34, 45}
vector unsigned long long test_ull () { const vector unsigned long long y = {56, 67}; return vec_splat (y, 0b00010); }
/* Assorted load instructions for the initialization with known constants. */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M|\mplxv\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M|\mlxv\M} 3 } } */
/* xxpermdi for vec_splat of long long vectors.
At the time of this writing, the number of xxpermdi instructions
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
index 162563caed4..d1100d01a83 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char );
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c
index c42a720d361..74e34c307fd 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector double, signed long long, double );
BUILD_VAR_TEST( test5, vector double, signed int, double );
BUILD_CST_TEST( test6, vector double, 12, double );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c
index b200c47fd2f..db6bd331829 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-float.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test4, vector float, signed long long, vector float );
BUILD_VAR_TEST( test5, vector float, signed int, vector float );
BUILD_CST_TEST( test6, vector float, 12, vector float );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c
index d9848820b3a..2a328897cbb 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-int.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int );
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c
index bb72d9b2a99..a62ca516f95 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-longlong.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector uns
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long );
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c
index f4dbb702583..2b1e1c0b90e 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-builtin_vec_xst-short.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short );
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c
index ae5cf8ef0b4..82bb891a9c9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-char.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char );
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c
index 1360f4d4ce9..34772cfe135 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-double.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test7, vector double, signed long long, vector double );
BUILD_VAR_TEST( test8, vector double, signed int, vector double );
BUILD_CST_TEST( test9, vector double, 12, vector double );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c
index 1b70f2a80f7..cf13f2a7ec1 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-float.c
@@ -28,4 +28,4 @@ BUILD_VAR_TEST( test7, vector float, signed long long, vector float );
BUILD_VAR_TEST( test8, vector float, signed int, vector float );
BUILD_CST_TEST( test9, vector float, 12, vector float );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c
index 4e4a499eaad..a9e189ddadd 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-int.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int );
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c
index b57c126b9ab..f50e2b93da1 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-longlong.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector unsi
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long );
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c
index 7593f425258..0f8a93ad371 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_vsx_st-short.c
@@ -36,4 +36,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short );
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c
index fdd2ed5648d..4f5930aa909 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-char.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned char, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned char, signed int, vector unsigned char );
BUILD_CST_TEST( test12, vector unsigned char, 12, vector unsigned char );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c
index 62f8552fdde..511d5fe7299 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-double.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test7, vector double, signed long long, vector double );
BUILD_VAR_TEST( test8, vector double, signed int, vector double );
BUILD_CST_TEST( test9, vector double, 12, vector double );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c
index ad15a5a2b51..13e6cb6e7af 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-float.c
@@ -27,4 +27,4 @@ BUILD_VAR_TEST( test7, vector float, signed long long, vector float );
BUILD_VAR_TEST( test8, vector float, signed int, vector float );
BUILD_CST_TEST( test9, vector float, 12, vector float );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c
index abe93dfb235..fd6ff78509b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-int.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned int, signed long long, vector unsigned i
BUILD_VAR_TEST( test11, vector unsigned int, signed int, vector unsigned int );
BUILD_CST_TEST( test12, vector unsigned int, 12, vector unsigned int );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c
index 6859593bf0a..a669481b0d8 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-longlong.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned long long, signed long long, vector unsi
BUILD_VAR_TEST( test11, vector unsigned long long, signed int, vector unsigned long long );
BUILD_CST_TEST( test12, vector unsigned long long, 12, vector unsigned long long );
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c
index 6c54873db20..78eae57fb23 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-store-vec_xst-short.c
@@ -35,4 +35,4 @@ BUILD_VAR_TEST( test10, vector unsigned short, signed long long, vector unsigned
BUILD_VAR_TEST( test11, vector unsigned short, signed int, vector unsigned short );
BUILD_CST_TEST( test12, vector unsigned short, 12, vector unsigned short );
-/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M|\mpstxv\M} 12 } } */
+/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstxvd2x\M|\mstxvx\M|\mstvx\M} 12 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
index 26aadbcbc63..93843c09f35 100644
--- a/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
+++ b/gcc/testsuite/gcc.target/powerpc/lvsl-lvsr.c
@@ -6,7 +6,7 @@
/* { dg-options "-O0 -Wno-deprecated" } */
/* { dg-final { scan-assembler-times "lvsl" 2 } } */
/* { dg-final { scan-assembler-times "lvsr" 2 } } */
-/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mp?lxv\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 2 } } */
/* { dg-final { scan-assembler-times {\m(?:v|xx)permr?\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
index 2ddf03117ab..496a6e340c0 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c
@@ -7,4 +7,4 @@ int foo(int x)
return x == 0;
}
-/* { dg-final { scan-assembler "cntlzw|isel|setbc" } } */
+/* { dg-final { scan-assembler "cntlzw|isel" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
index bf777979833..63c4b6087df 100644
--- a/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/ppc-ne0-1.c
@@ -2,14 +2,6 @@
/* { dg-do compile } */
/* { dg-options "-O2 -mno-isel" } */
-/* If the compiler was configured to automatically generate power10 support with
- --with-cpu=power10, turn it off. Otherwise, it will generate a SETBCR
- instruction instead of ADDIC/SUBFE. */
-
-#ifdef _ARCH_PWR10
-#pragma GCC target ("cpu=power9")
-#endif
-
/* { dg-final { scan-assembler-times "addic" 4 } } */
/* { dg-final { scan-assembler-times "subfe" 1 } } */
/* { dg-final { scan-assembler-times "addze" 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index d5ed700b9bc..1269fe635c6 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -30,5 +30,5 @@ vector signed long long splats4(void)
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M|\mplvx\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M} 2 } } */
^ permalink raw reply [flat|nested] 5+ messages in thread
* [gcc(refs/users/meissner/heads/work053)] Revert patches
@ 2021-05-18 1:28 Michael Meissner
0 siblings, 0 replies; 5+ messages in thread
From: Michael Meissner @ 2021-05-18 1:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e226978b94be055843b07130a389992984784856
commit e226978b94be055843b07130a389992984784856
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 17 21:26:59 2021 -0400
Revert patches
gcc/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* config/rs6000/rs6000.c (rs6000_maybe_emit_fp_cmove): Add IEEE
128-bit floating point conditional move support.
(have_compare_and_set_mask): Add IEEE 128-bit floating point
types.
* config/rs6000/rs6000.md (mov<mode>cc, IEEE128 iterator): New insn.
(mov<mode>cc_p10, IEEE128 iterator): New insn.
(mov<mode>cc_invert_p10, IEEE128 iterator): New insn.
(fpmask<mode>, IEEE128 iterator): New insn.
(xxsel<mode>, IEEE128 iterator): New insn.
gcc/testsuite/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* gcc.target/powerpc/float128-cmove.c: New test.
* gcc.target/powerpc/float128-minmax-3.c: New test.
gcc/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA
3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp
instructions.
* config/rs6000/rs6000.md (s<minmax><mode>3, IEEE128 iterator):
New insns.
gcc/testsuite/
2021-05-17 Michael Meissner <meissner@linux.ibm.com>
Revert patch
* gcc.target/powerpc/float128-minmax-2.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.c | 41 +-------
gcc/config/rs6000/rs6000.md | 117 ---------------------
gcc/testsuite/gcc.target/powerpc/float128-cmove.c | 58 ----------
.../gcc.target/powerpc/float128-minmax-2.c | 15 ---
.../gcc.target/powerpc/float128-minmax-3.c | 15 ---
5 files changed, 3 insertions(+), 243 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ef1ebaaee05..0d0595dddd6 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15706,8 +15706,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
return 1;
}
-/* Possibly emit the xsmaxc{dp,qp} and xsminc{dp,qp} instructions to emit a
- maximum or minimum with "C" semantics.
+/* Possibly emit the xsmaxcdp and xsmincdp instructions to emit a maximum or
+ minimum with "C" semantics.
Unless you use -ffast-math, you can't use these instructions to replace
conditions that implicitly reverse the condition because the comparison
@@ -15783,7 +15783,6 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
enum rtx_code code = GET_CODE (op);
rtx op0 = XEXP (op, 0);
rtx op1 = XEXP (op, 1);
- machine_mode compare_mode = GET_MODE (op0);
machine_mode result_mode = GET_MODE (dest);
rtx compare_rtx;
rtx cmove_rtx;
@@ -15792,35 +15791,6 @@ rs6000_maybe_emit_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
if (!can_create_pseudo_p ())
return 0;
- /* We allow the comparison to be either SFmode/DFmode and the true/false
- condition to be either SFmode/DFmode. I.e. we allow:
-
- float a, b;
- double c, d, r;
-
- r = (a == b) ? c : d;
-
- and:
-
- double a, b;
- float c, d, r;
-
- r = (a == b) ? c : d;
-
- but we don't allow intermixing the IEEE 128-bit floating point types with
- the 32/64-bit scalar types.
-
- It gets too messy where SFmode/DFmode can use any register and TFmode/KFmode
- can only use Altivec registers. In addtion, we would need to do a XXPERMDI
- if we compare SFmode/DFmode and move TFmode/KFmode. */
-
- if (compare_mode == result_mode
- || (compare_mode == SFmode && result_mode == DFmode)
- || (compare_mode == DFmode && result_mode == SFmode))
- ;
- else
- return false;
-
switch (code)
{
case EQ:
@@ -15873,10 +15843,6 @@ have_compare_and_set_mask (machine_mode mode)
case E_DFmode:
return TARGET_P9_MINMAX;
- case E_KFmode:
- case E_TFmode:
- return TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode);
-
default:
break;
}
@@ -16145,8 +16111,7 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
/* VSX/altivec have direct min/max insns. */
if ((code == SMAX || code == SMIN)
&& (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
- || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
- || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode))))
+ || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
{
emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
return;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 0c76338c734..0bfeb24d9e8 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -5196,17 +5196,6 @@
}
[(set_attr "type" "fp")])
-;; Min/max for ISA 3.1 IEEE 128-bit floating point
-(define_insn "s<minmax><mode>3"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (fp_minmax:IEEE128
- (match_operand:IEEE128 1 "altivec_register_operand" "v")
- (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
- "TARGET_POWER10"
- "xs<minmax>cqp %0,%1,%2"
- [(set_attr "type" "vecfloat")
- (set_attr "size" "128")])
-
;; The conditional move instructions allow us to perform max and min operations
;; even when we don't have the appropriate max/min instruction using the FSEL
;; instruction.
@@ -5431,112 +5420,6 @@
"xxsel %x0,%x4,%x3,%x1"
[(set_attr "type" "vecmove")])
-;; Support for ISA 3.1 IEEE 128-bit conditional move. The mode used in the
-;; comparison must be the same as used in the conditional move.
-(define_expand "mov<mode>cc"
- [(set (match_operand:IEEE128 0 "gpc_reg_operand")
- (if_then_else:IEEE128 (match_operand 1 "comparison_operator")
- (match_operand:IEEE128 2 "gpc_reg_operand")
- (match_operand:IEEE128 3 "gpc_reg_operand")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
-{
- if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
- DONE;
- else
- FAIL;
-})
-
-(define_insn_and_split "*mov<mode>cc_p10"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=&v,v")
- (if_then_else:IEEE128
- (match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:IEEE128 2 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 3 "altivec_register_operand" "v,v")])
- (match_operand:IEEE128 4 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
- (clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "#"
- "&& 1"
- [(set (match_dup 6)
- (if_then_else:V2DI (match_dup 1)
- (match_dup 7)
- (match_dup 8)))
- (set (match_dup 0)
- (if_then_else:IEEE128 (ne (match_dup 6)
- (match_dup 8))
- (match_dup 4)
- (match_dup 5)))]
-{
- if (GET_CODE (operands[6]) == SCRATCH)
- operands[6] = gen_reg_rtx (V2DImode);
-
- operands[7] = CONSTM1_RTX (V2DImode);
- operands[8] = CONST0_RTX (V2DImode);
-}
- [(set_attr "length" "8")
- (set_attr "type" "vecperm")])
-
-;; Handle inverting the fpmask comparisons.
-(define_insn_and_split "*mov<mode>cc_invert_p10"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=&v,v")
- (if_then_else:IEEE128
- (match_operator:CCFP 1 "invert_fpmask_comparison_operator"
- [(match_operand:IEEE128 2 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 3 "altivec_register_operand" "v,v")])
- (match_operand:IEEE128 4 "altivec_register_operand" "v,v")
- (match_operand:IEEE128 5 "altivec_register_operand" "v,v")))
- (clobber (match_scratch:V2DI 6 "=0,&v"))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "#"
- "&& 1"
- [(set (match_dup 6)
- (if_then_else:V2DI (match_dup 9)
- (match_dup 7)
- (match_dup 8)))
- (set (match_dup 0)
- (if_then_else:IEEE128 (ne (match_dup 6)
- (match_dup 8))
- (match_dup 5)
- (match_dup 4)))]
-{
- rtx op1 = operands[1];
- enum rtx_code cond = reverse_condition_maybe_unordered (GET_CODE (op1));
-
- if (GET_CODE (operands[6]) == SCRATCH)
- operands[6] = gen_reg_rtx (V2DImode);
-
- operands[7] = CONSTM1_RTX (V2DImode);
- operands[8] = CONST0_RTX (V2DImode);
-
- operands[9] = gen_rtx_fmt_ee (cond, CCFPmode, operands[2], operands[3]);
-}
- [(set_attr "length" "8")
- (set_attr "type" "vecperm")])
-
-(define_insn "*fpmask<mode>"
- [(set (match_operand:V2DI 0 "altivec_register_operand" "=v")
- (if_then_else:V2DI
- (match_operator:CCFP 1 "fpmask_comparison_operator"
- [(match_operand:IEEE128 2 "altivec_register_operand" "v")
- (match_operand:IEEE128 3 "altivec_register_operand" "v")])
- (match_operand:V2DI 4 "all_ones_constant" "")
- (match_operand:V2DI 5 "zero_constant" "")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xscmp%V1qp %0,%2,%3"
- [(set_attr "type" "fpcompare")])
-
-(define_insn "*xxsel<mode>"
- [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
- (if_then_else:IEEE128
- (ne (match_operand:V2DI 1 "altivec_register_operand" "v")
- (match_operand:V2DI 2 "zero_constant" ""))
- (match_operand:IEEE128 3 "altivec_register_operand" "v")
- (match_operand:IEEE128 4 "altivec_register_operand" "v")))]
- "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
- "xxsel %x0,%x4,%x3,%x1"
- [(set_attr "type" "vecmove")])
-
\f
;; Conversions to and from floating-point.
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c b/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
deleted file mode 100644
index 2fae8dc23bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-cmove.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#ifndef TYPE
-#ifdef __LONG_DOUBLE_IEEE128__
-#define TYPE long double
-
-#else
-#define TYPE _Float128
-#endif
-#endif
-
-/* Verify that the ISA 3.1 (power10) IEEE 128-bit conditional move instructions
- are generated. */
-
-TYPE
-eq (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a == b) ? c : d;
-}
-
-TYPE
-ne (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a != b) ? c : d;
-}
-
-TYPE
-lt (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a < b) ? c : d;
-}
-
-TYPE
-le (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a <= b) ? c : d;
-}
-
-TYPE
-gt (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a > b) ? c : d;
-}
-
-TYPE
-ge (TYPE a, TYPE b, TYPE c, TYPE d)
-{
- return (a >= b) ? c : d;
-}
-
-/* { dg-final { scan-assembler-times {\mxscmpeqqp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxscmpgeqp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxscmpgtqp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxxsel\M} 6 } } */
-/* { dg-final { scan-assembler-not {\mxscmpuqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
deleted file mode 100644
index c71ba08c9f8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
-TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
deleted file mode 100644
index 6f7627c0f2a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-minmax-3.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#ifndef TYPE
-#define TYPE _Float128
-#endif
-
-/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
- call. */
-TYPE f128_min (TYPE a, TYPE b) { return (a < b) ? a : b; }
-TYPE f128_max (TYPE a, TYPE b) { return (b > a) ? b : a; }
-
-/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
-/* { dg-final { scan-assembler {\mxsmincqp\M} } } */
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