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* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-15 5:23 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-15 5:23 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ab9c804795b684729ad965488baec17dc39e3d29
commit ab9c804795b684729ad965488baec17dc39e3d29
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 15 01:23:14 2021 -0400
Revert patches.
2021-10-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_prefixed): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add field for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/predicates.md | 11 +-
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 123 +--------------------
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 4 +-
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 -----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 -----------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -----------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
10 files changed, 10 insertions(+), 343 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 252abbbaf9a..517ce08f03d 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,9 +611,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -647,7 +644,7 @@
})
;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with one prefixed instruction, such as XXSPLTIDP or XXSPLTIW.
+;; register with one prefixed instruction, such as XXSPLTIDP.
;;
;; We have to have separate predicates and constraints for scalars and vectors,
;; otherwise things get messed up with TImode when you try to load very large
@@ -669,9 +666,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
return false;
})
@@ -750,9 +744,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
return easy_altivec_constant (op, mode);
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 52f094dd410..6e8b81cb134 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -240,13 +240,11 @@ typedef struct {
unsigned char bytes[VECTOR_CONST_BYTES];
machine_mode orig_mode; /* Original mode. */
unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
unsigned int lxvkq_immediate; /* Immediate to use with LXVKQ. */
} rs6000_vec_const;
extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 9c24c9bc3f7..d238dd84fe7 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6925,17 +6925,12 @@ xxspltib_constant_p (rtx op,
else
return false;
- /* See if we could generate vspltisw/vspltish/xxspltiw directly instead of
- xxspltib + sign extend. Special case 0/-1 to allow getting any VSX
- register instead of an Altivec register. */
- if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0))
- {
- if (EASY_VECTOR_15 (value))
- return false;
-
- if (TARGET_XXSPLTIW && TARGET_PREFIXED && TARGET_VSX)
- return false;
- }
+ /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
+ sign extend. Special case 0/-1 to allow getting any VSX register instead
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
+ return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
if (mode == V16QImode)
@@ -7009,52 +7004,6 @@ output_vec_const_move (rtx *operands)
operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
return "xxspltidp %x0,%2";
}
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- HOST_WIDE_INT imm = vec_const.xxspltiw_immediate;
-
- /* See if we can generate the shorter VSPLTISB, VSPLTISH, or
- VSPLTISW instead of XXSPLTIW. */
- if (dest_vmx_p)
- {
- HOST_WIDE_INT sign_imm
- = ((imm & 0xffffffff) ^ 0x80000000) - 0x80000000;
-
- if (EASY_VECTOR_15 (sign_imm))
- {
- operands[2] = GEN_INT (sign_imm);
- return "vspltisw %0,%2";
- }
-
- if (vec_const.bytes[0] == vec_const.bytes[1]
- && vec_const.bytes[0] == vec_const.bytes[2]
- && vec_const.bytes[0] == vec_const.bytes[3])
- {
- HOST_WIDE_INT sign_imm8 = ((imm & 0xff) ^ 0x80) - 0x80;
- if (EASY_VECTOR_15 (sign_imm8))
- {
- operands[2] = GEN_INT (sign_imm8);
- return "vspltisb %0,%2";
- }
- }
-
- if (vec_const.h_words[0] == vec_const.h_words[1])
- {
- HOST_WIDE_INT sign_imm16
- = ((imm & 0xffff) ^ 0x8000) - 0x8000;
-
- if (EASY_VECTOR_15 (sign_imm16))
- {
- operands[2] = GEN_INT (sign_imm16);
- return "vspltish %0,%2";
- }
- }
- }
-
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
}
if (TARGET_P9_VECTOR
@@ -26821,9 +26770,6 @@ prefixed_xxsplti_p (rtx_insn *insn)
{
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
return false;
@@ -28838,63 +28784,6 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
return true;
}
-/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with VSPLTIW.. */
- if (value == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = SImode;
-
- if (!FLOAT_MODE_P (mode))
- {
- /* Can we use VSPLTISW to load the constant? */
- int sign_value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_value))
- return false;
-
- /* Can we use VSPLTISB to load the constant? */
- if (vec_const->bytes[0] == vec_const->bytes[1]
- && vec_const->bytes[0] == vec_const->bytes[2]
- && vec_const->bytes[0] == vec_const->bytes[3])
- {
- int sign_value8 = ((value & 0xff) ^ 0x80) - 0x80;
- if (EASY_VECTOR_15 (sign_value8))
- return false;
- }
-
- /* Can we use VSPLTISH to load the constant? */
- if (vec_const->h_words[0] == vec_const->h_words[1])
- {
- int sign_value16 = ((value & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_value16))
- return false;
- }
- }
-
- /* Record the immediate in the vec_const structure for XXSPLTIW. */
- vec_const->xxspltiw_immediate = value;
-
- return true;
-}
-
/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
the fields used to generate the instruction. */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 015bf91b6d5..c9eb78952d6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,10 +644,6 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 07b0b671920..15a22525000 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,7 +1192,7 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ
+;; XXLSPLTIDP LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
@@ -1241,7 +1241,7 @@
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ
+;; XXSPLTIDP LXVKQ
;; VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..5f84930e1a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,7 +149,7 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-29 22:31 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-29 22:31 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0522babffe2fa86a5cb6057137141988493a277e
commit 0522babffe2fa86a5cb6057137141988493a277e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 29 18:30:27 2021 -0400
Revert patches.
gcc/
2021-10-29 Michael Meissner <meissner@the-meissners.org>
Revert patches.
* config/rs6000/rs6000.c (TARGET_FORTRAN_REAL_KIND_FLOAT128_P):
Set target hook.
(rs6000_fortran_real_kind_float128_p): New target hook.
* target.def (fortran_real_kind_float128_p): New target hook.
* targhooks.c (default_fortran_real_kind_float128_p): New default
target hooks for Fortran kind support.
* targhooks.h (default_fortran_real_kind_float128_p): New
declaration.
* doc/tm.texi.in (TARGET_FORTRAN_REAL_KIND_FLOAT128_P): Document
new target hook.
* doc/tm.texi: Regenerate.
gcc/fortran/
2021-10-29 Michael Meissner <meissner@the-meissners.org>
Revert patches.
* trans-types.c (gfc_build_real_type): Rework support to better
detect float128 on PowerPC.
gcc/
2021-10-29 Michael Meissner <meissner@the-meissners.org>
Revert patches.
* config/rs6000/rs6000.c (TARGET_FORTRAN_REAL_KIND_NUMBER): Set
target hook.
(TARGET_FORTRAN_REAL_KIND_TYPE): Likewise.
(rs6000_fortran_real_kind_number): New target hook.
(rs6000_fortran_real_kind_type): Likewise.
* target.def (fortran_real_kind_number): New target hook.
(fortran_real_kind_type): Likewise.
* targhooks.c (default_fortran_real_kind_number): New default
target hooks for Fortran kind support.
(default_fortran_real_kind_type): Likewise.
* targhooks.c (default_fortran_real_kind_number): New
declaration.
(default_fortran_real_kind_type): Likewise.
* doc/tm.texi.in (TARGET_FORTRAN_REAL_KIND_NUMBER): Document new
target hooks.
(TARGET_FORTRAN_REAL_KIND_TYPE): Likewise.
* doc/tm.texi: Regenerate.
gcc/fortran/
2021-10-29 Michael Meissner <meissner@the-meissners.org>
Revert patches.
* f95-lang.c (gfc_init_builtin_functions): Flesh out more Float128
support.
* trans-types.c (gfc_init_kinds): Add support for using target
hooks to allow the backend to control KIND numbers.
(gfc_build_real_type): Likewise.
(gfc_build_complex_type): Add support for complex Float128.
Diff:
---
gcc/config/rs6000/rs6000.c | 101 ---------------------------------------------
gcc/doc/tm.texi | 17 --------
gcc/doc/tm.texi.in | 6 ---
gcc/fortran/f95-lang.c | 28 -------------
gcc/fortran/trans-types.c | 32 +++++---------
gcc/target.def | 22 +---------
gcc/targhooks.c | 37 -----------------
gcc/targhooks.h | 3 --
gcc/tree.h | 2 -
9 files changed, 12 insertions(+), 236 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 70595e58ac2..22f5d701908 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1787,15 +1787,6 @@ static const struct attribute_spec rs6000_attribute_table[] =
#undef TARGET_INVALID_CONVERSION
#define TARGET_INVALID_CONVERSION rs6000_invalid_conversion
-
-#undef TARGET_FORTRAN_REAL_KIND_NUMBER
-#define TARGET_FORTRAN_REAL_KIND_NUMBER rs6000_fortran_real_kind_number
-
-#undef TARGET_FORTRAN_REAL_KIND_TYPE
-#define TARGET_FORTRAN_REAL_KIND_TYPE rs6000_fortran_real_kind_type
-
-#undef TARGET_FORTRAN_REAL_KIND_FLOAT128_P
-#define TARGET_FORTRAN_REAL_KIND_FLOAT128_P rs6000_fortran_real_kind_float128_p
\f
/* Processor table. */
@@ -28385,98 +28376,6 @@ rs6000_globalize_decl_name (FILE * stream, tree decl)
}
#endif
-\f
-
-/* PowerPC support for Fortran KIND support. Given a MODE, return a kind
- number to be used for real modes. If we support IEEE 128-bit, make KIND=16
- always be IEEE 128-bit, and make KIND=15 be the IBM 128-bit double-double
- format. */
-
-static int
-rs6000_fortran_real_kind_number (machine_mode mode)
-{
- if (TARGET_FLOAT128_TYPE)
- {
- /* If long double is IEEE 128-bit, return 16 for long double and 15 for
- __ibm128, and ignore the explicit __float128 type. Otherwise return
- 15 for long double, 16 for __float128, and ignore __ibm128. */
- if (FLOAT128_IEEE_P (TFmode))
- {
- if (mode == TFmode)
- return 16;
- else if (mode == IFmode)
- return 15;
- }
- else
- {
- if (mode == KFmode)
- return 16;
- else if (mode == TFmode)
- return 15;
- }
- }
-
- return 0;
-}
-
-/* PowerPC support for Fortran KIND support. Return a type given a precision
- that Fortran will handle for kind support. We don't have to support the
- standard types. */
-static tree
-rs6000_fortran_real_kind_type (int precision)
-{
- if (TARGET_FLOAT128_TYPE)
- {
- switch (precision)
- {
- case FLOAT_PRECISION_TFmode:
- return long_double_type_node;
-
- case FLOAT_PRECISION_IFmode:
- return (FLOAT128_IBM_P (TFmode)
- ? long_double_type_node
- : ibm128_float_type_node);
-
- case FLOAT_PRECISION_KFmode:
- return (FLOAT128_IEEE_P (TFmode)
- ? long_double_type_node
- : float128_type_node);
-
- default:
- break;
- }
- }
-
- return NULL_TREE;
-}
-
-/* PowerPC support for Fortran KIND support. Return true given a precision for
- a floating point scalar type that Fortran will handle for kind support. We
- don't have to handle the standard types here. */
-static bool
-rs6000_fortran_real_kind_float128_p (int precision)
-{
- if (TARGET_FLOAT128_TYPE)
- {
- switch (precision)
- {
- case FLOAT_PRECISION_TFmode:
- return FLOAT128_IEEE_P (TFmode);
-
- case FLOAT_PRECISION_IFmode:
- return false;
-
- case FLOAT_PRECISION_KFmode:
- return true;
-
- default:
- break;
- }
- }
-
- return NULL_TREE;
-}
-
\f
/* On 64-bit Linux and Freebsd systems, possibly switch the long double library
function names from <foo>l to <foo>f128 if the default long double type is
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index e9743d791d2..902402d7503 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -12612,20 +12612,3 @@ counters are incremented using atomic operations. Targets not supporting
64-bit atomic operations may override the default value and request a 32-bit
type.
@end deftypefn
-
-@deftypefn {Target Hook} int TARGET_FORTRAN_REAL_KIND_NUMBER (machine_mode @var{mode})
-Returns an integer from a @code{MODE} that would be the Fortran kind
-number for target specific modes. @code{MODE} is a scalar floating point
-mode. If the mode cannot be represented, a 0 is returned.
-@end deftypefn
-
-@deftypefn {Target Hook} tree TARGET_FORTRAN_REAL_KIND_TYPE (int @var{precision})
-Returns a floating point scalar type with precision @code{PRECISION} that
-can be used for a Fortran kind type. If the precision cannot be represented,
-a @code{NULL_TREE} is returned.
-@end deftypefn
-
-@deftypefn {Target Hook} bool TARGET_FORTRAN_REAL_KIND_FLOAT128_P (int @var{precision})
-Returns true if the floating point scalar type with precision
-@code{PRECISION} is an IEEE 128-bit floating point value.
-@end deftypefn
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 28ae369e588..86352dc9bd2 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -8187,9 +8187,3 @@ maintainer is familiar with.
@hook TARGET_MEMTAG_UNTAGGED_POINTER
@hook TARGET_GCOV_TYPE_SIZE
-
-@hook TARGET_FORTRAN_REAL_KIND_NUMBER
-
-@hook TARGET_FORTRAN_REAL_KIND_TYPE
-
-@hook TARGET_FORTRAN_REAL_KIND_FLOAT128_P
diff --git a/gcc/fortran/f95-lang.c b/gcc/fortran/f95-lang.c
index b8117dc72b4..58dcaf01d75 100644
--- a/gcc/fortran/f95-lang.c
+++ b/gcc/fortran/f95-lang.c
@@ -674,11 +674,9 @@ gfc_init_builtin_functions (void)
tree mfunc_float[6];
tree mfunc_double[6];
tree mfunc_longdouble[6];
- tree mfunc_float128[6];
tree mfunc_cfloat[6];
tree mfunc_cdouble[6];
tree mfunc_clongdouble[6];
- tree mfunc_cfloat128[6];
tree func_cfloat_float, func_float_cfloat;
tree func_cdouble_double, func_double_cdouble;
tree func_clongdouble_longdouble, func_longdouble_clongdouble;
@@ -693,11 +691,9 @@ gfc_init_builtin_functions (void)
build_builtin_fntypes (mfunc_float, float_type_node);
build_builtin_fntypes (mfunc_double, double_type_node);
build_builtin_fntypes (mfunc_longdouble, long_double_type_node);
- build_builtin_fntypes (mfunc_float128, float128_type_node);
build_builtin_fntypes (mfunc_cfloat, complex_float_type_node);
build_builtin_fntypes (mfunc_cdouble, complex_double_type_node);
build_builtin_fntypes (mfunc_clongdouble, complex_long_double_type_node);
- build_builtin_fntypes (mfunc_cfloat128, complex_float128_type_node);
func_cfloat_float = build_function_type_list (float_type_node,
complex_float_type_node,
@@ -740,8 +736,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_roundl", mfunc_longdouble[0],
BUILT_IN_ROUNDL, "roundl", ATTR_CONST_NOTHROW_LEAF_LIST);
- gfc_define_builtin ("__builtin_roundf128", mfunc_float128[0],
- BUILT_IN_ROUNDF128, "roundf128", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_round", mfunc_double[0],
BUILT_IN_ROUND, "round", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_roundf", mfunc_float[0],
@@ -749,8 +743,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_truncl", mfunc_longdouble[0],
BUILT_IN_TRUNCL, "truncl", ATTR_CONST_NOTHROW_LEAF_LIST);
- gfc_define_builtin ("__builtin_truncf128", mfunc_float128[0],
- BUILT_IN_TRUNCF128, "truncl", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_trunc", mfunc_double[0],
BUILT_IN_TRUNC, "trunc", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_truncf", mfunc_float[0],
@@ -758,7 +750,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_cabsl", func_clongdouble_longdouble,
BUILT_IN_CABSL, "cabsl", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_cabsf128. */
gfc_define_builtin ("__builtin_cabs", func_cdouble_double,
BUILT_IN_CABS, "cabs", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_cabsf", func_cfloat_float,
@@ -767,9 +758,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_copysignl", mfunc_longdouble[1],
BUILT_IN_COPYSIGNL, "copysignl",
ATTR_CONST_NOTHROW_LEAF_LIST);
- gfc_define_builtin ("__builtin_copysignf128", mfunc_longdouble[1],
- BUILT_IN_COPYSIGNF128, "copysignf128",
- ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_copysign", mfunc_double[1],
BUILT_IN_COPYSIGN, "copysign",
ATTR_CONST_NOTHROW_LEAF_LIST);
@@ -780,7 +768,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_nextafterl", mfunc_longdouble[1],
BUILT_IN_NEXTAFTERL, "nextafterl",
ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_nextafterf128. */
gfc_define_builtin ("__builtin_nextafter", mfunc_double[1],
BUILT_IN_NEXTAFTER, "nextafter",
ATTR_CONST_NOTHROW_LEAF_LIST);
@@ -794,8 +781,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_rintl", mfunc_longdouble[0],
BUILT_IN_RINTL, "rintl", attr);
- gfc_define_builtin ("__builtin_rintf128", mfunc_float128[0],
- BUILT_IN_RINTF128, "rintf128", attr);
gfc_define_builtin ("__builtin_rint", mfunc_double[0],
BUILT_IN_RINT, "rint", attr);
gfc_define_builtin ("__builtin_rintf", mfunc_float[0],
@@ -803,7 +788,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_remainderl", mfunc_longdouble[1],
BUILT_IN_REMAINDERL, "remainderl", attr);
- /* no __builtin_remainderf128. */
gfc_define_builtin ("__builtin_remainder", mfunc_double[1],
BUILT_IN_REMAINDER, "remainder", attr);
gfc_define_builtin ("__builtin_remainderf", mfunc_float[1],
@@ -811,7 +795,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_logbl", mfunc_longdouble[0],
BUILT_IN_LOGBL, "logbl", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_logbf128. */
gfc_define_builtin ("__builtin_logb", mfunc_double[0],
BUILT_IN_LOGB, "logb", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_logbf", mfunc_float[0],
@@ -820,7 +803,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_frexpl", mfunc_longdouble[4],
BUILT_IN_FREXPL, "frexpl", ATTR_NOTHROW_LEAF_LIST);
- /* no __builtin_frexpf128. */
gfc_define_builtin ("__builtin_frexp", mfunc_double[4],
BUILT_IN_FREXP, "frexp", ATTR_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_frexpf", mfunc_float[4],
@@ -828,8 +810,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_fabsl", mfunc_longdouble[0],
BUILT_IN_FABSL, "fabsl", ATTR_CONST_NOTHROW_LEAF_LIST);
- gfc_define_builtin ("__builtin_fabsf128", mfunc_float128[0],
- BUILT_IN_FABSF128, "fabsf128", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_fabs", mfunc_double[0],
BUILT_IN_FABS, "fabs", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_fabsf", mfunc_float[0],
@@ -837,7 +817,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_scalbnl", mfunc_longdouble[2],
BUILT_IN_SCALBNL, "scalbnl", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_scalbnf128. */
gfc_define_builtin ("__builtin_scalbn", mfunc_double[2],
BUILT_IN_SCALBN, "scalbn", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_scalbnf", mfunc_float[2],
@@ -845,7 +824,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_fmodl", mfunc_longdouble[1],
BUILT_IN_FMODL, "fmodl", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_fmodf128. */
gfc_define_builtin ("__builtin_fmod", mfunc_double[1],
BUILT_IN_FMOD, "fmod", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_fmodf", mfunc_float[1],
@@ -894,21 +872,18 @@ gfc_init_builtin_functions (void)
/* These are used to implement the ** operator. */
gfc_define_builtin ("__builtin_powl", mfunc_longdouble[1],
BUILT_IN_POWL, "powl", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_powf128. */
gfc_define_builtin ("__builtin_pow", mfunc_double[1],
BUILT_IN_POW, "pow", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_powf", mfunc_float[1],
BUILT_IN_POWF, "powf", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_cpowl", mfunc_clongdouble[1],
BUILT_IN_CPOWL, "cpowl", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_cpowf128. */
gfc_define_builtin ("__builtin_cpow", mfunc_cdouble[1],
BUILT_IN_CPOW, "cpow", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_cpowf", mfunc_cfloat[1],
BUILT_IN_CPOWF, "cpowf", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_powil", mfunc_longdouble[2],
BUILT_IN_POWIL, "powil", ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_powif128. */
gfc_define_builtin ("__builtin_powi", mfunc_double[2],
BUILT_IN_POWI, "powi", ATTR_CONST_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_powif", mfunc_float[2],
@@ -920,7 +895,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_cbrtl", mfunc_longdouble[0],
BUILT_IN_CBRTL, "cbrtl",
ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_cbrtf128. */
gfc_define_builtin ("__builtin_cbrt", mfunc_double[0],
BUILT_IN_CBRT, "cbrt",
ATTR_CONST_NOTHROW_LEAF_LIST);
@@ -930,7 +904,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_cexpil", func_longdouble_clongdouble,
BUILT_IN_CEXPIL, "cexpil",
ATTR_CONST_NOTHROW_LEAF_LIST);
- /* no __builtin_cexpif128. */
gfc_define_builtin ("__builtin_cexpi", func_double_cdouble,
BUILT_IN_CEXPI, "cexpi",
ATTR_CONST_NOTHROW_LEAF_LIST);
@@ -944,7 +917,6 @@ gfc_init_builtin_functions (void)
gfc_define_builtin ("__builtin_sincosl",
func_longdouble_longdoublep_longdoublep,
BUILT_IN_SINCOSL, "sincosl", ATTR_NOTHROW_LEAF_LIST);
- /* no __builtin_sincosf128. */
gfc_define_builtin ("__builtin_sincos", func_double_doublep_doublep,
BUILT_IN_SINCOS, "sincos", ATTR_NOTHROW_LEAF_LIST);
gfc_define_builtin ("__builtin_sincosf", func_float_floatp_floatp,
diff --git a/gcc/fortran/trans-types.c b/gcc/fortran/trans-types.c
index 4b2885de3f1..1c78a906397 100644
--- a/gcc/fortran/trans-types.c
+++ b/gcc/fortran/trans-types.c
@@ -451,6 +451,14 @@ gfc_init_kinds (void)
useless. */
if (!targetm.libgcc_floating_mode_supported_p (mode))
continue;
+ if (mode != TYPE_MODE (float_type_node)
+ && (mode != TYPE_MODE (double_type_node))
+ && (mode != TYPE_MODE (long_double_type_node))
+#if defined(HAVE_TFmode) && defined(ENABLE_LIBQUADMATH_SUPPORT)
+ && (mode != TFmode)
+#endif
+ )
+ continue;
/* Let the kind equal the precision divided by 8, rounding up. Again,
this insulates the programmer from the underlying byte size.
@@ -472,9 +480,7 @@ gfc_init_kinds (void)
reach this code.
*/
- kind = targetm.fortran_real_kind_number (mode);
- if (kind == 0)
- kind = (GET_MODE_PRECISION (mode) + 7) / 8;
+ kind = (GET_MODE_PRECISION (mode) + 7) / 8;
if (kind == 4)
saw_r4 = true;
@@ -850,26 +856,12 @@ gfc_build_real_type (gfc_real_info *info)
info->c_double = 1;
if (mode_precision == LONG_DOUBLE_TYPE_SIZE)
info->c_long_double = 1;
-
-#if defined(HAVE_TFmode) && defined(ENABLE_LIBQUADMATH_SUPPORT)
- if (TYPE_PRECISION (float128_type_node) == mode_precision)
- {
+ if (mode_precision != LONG_DOUBLE_TYPE_SIZE && mode_precision == 128)
+ {
/* TODO: see PR101835. */
info->c_float128 = 1;
gfc_real16_is_float128 = true;
}
-#endif
-
- tree type = targetm.fortran_real_kind_type (mode_precision);
- if (type)
- {
- if (type == float128_type_node)
- {
- info->c_float128 = 1;
- gfc_real16_is_float128 = true;
- }
- return type;
- }
if (TYPE_PRECISION (float_type_node) == mode_precision)
return float_type_node;
@@ -897,8 +889,6 @@ gfc_build_complex_type (tree scalar_type)
return complex_double_type_node;
if (scalar_type == long_double_type_node)
return complex_long_double_type_node;
- if (scalar_type == float128_type_node)
- return complex_float128_type_node;
new_type = make_node (COMPLEX_TYPE);
TREE_TYPE (new_type) = scalar_type;
diff --git a/gcc/target.def b/gcc/target.def
index 308649779fa..c5d90cace80 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -7129,26 +7129,6 @@ counters are incremented using atomic operations. Targets not supporting\n\
type.",
HOST_WIDE_INT, (void), default_gcov_type_size)
-DEFHOOK
-(fortran_real_kind_number,
- "Returns an integer from a @code{MODE} that would be the Fortran kind\n\
-number for target specific modes. @code{MODE} is a scalar floating point\n\
-mode. If the mode cannot be represented, a 0 is returned.",
- int, (machine_mode mode), default_fortran_real_kind_number)
-
-DEFHOOK
-(fortran_real_kind_type,
- "Returns a floating point scalar type with precision @code{PRECISION} that\n\
-can be used for a Fortran kind type. If the precision cannot be represented,\n\
-a @code{NULL_TREE} is returned.",
- tree, (int precision), default_fortran_real_kind_type)
-
-DEFHOOK
-(fortran_real_kind_float128_p,
- "Returns true if the floating point scalar type with precision\n\
-@code{PRECISION} is an IEEE 128-bit floating point value.",
- bool, (int precision), default_fortran_real_kind_float128_p)
-
- /* Close the 'struct gcc_target' definition. */
+/* Close the 'struct gcc_target' definition. */
HOOK_VECTOR_END (C90_EMPTY_HACK)
diff --git a/gcc/targhooks.c b/gcc/targhooks.c
index cc15539ffdb..cbbcedf790f 100644
--- a/gcc/targhooks.c
+++ b/gcc/targhooks.c
@@ -2661,41 +2661,4 @@ default_gcov_type_size (void)
return TYPE_PRECISION (long_long_integer_type_node) > 32 ? 64 : 32;
}
-/* The default implementation of TARGET_FORTRAN_REAL_KIND_NUMBER. */
-
-int
-default_fortran_real_kind_number (machine_mode mode ATTRIBUTE_UNUSED)
-{
-#if defined(HAVE_TFmode) && defined(ENABLE_LIBQUADMATH_SUPPORT)
- if (mode == TFmode)
- return GET_MODE_SIZE (TFmode);
-#endif
-
- return 0;
-}
-
-/* The default implementation of TARGET_FORTRAN_REAL_KIND_TYPE. */
-tree
-default_fortran_real_kind_type (int precision ATTRIBUTE_UNUSED)
-{
-#if defined(HAVE_TFmode) && defined(ENABLE_LIBQUADMATH_SUPPORT)
- if (precision == TYPE_PRECISION (float128_type_node))
- return float128_type_node;
-#endif
-
- return NULL_TREE;
-}
-
-/* The default implementation of TARGET_FORTRAN_REAL_KIND_FLOAT128_p. */
-bool
-default_fortran_real_kind_float128_p (int precision ATTRIBUTE_UNUSED)
-{
-#if defined(HAVE_TFmode) && defined(ENABLE_LIBQUADMATH_SUPPORT)
- if (precision == TYPE_PRECISION (float128_type_node))
- return true;
-#endif
-
- return false;
-}
-
#include "gt-targhooks.h"
diff --git a/gcc/targhooks.h b/gcc/targhooks.h
index c5f9cd08450..92d51992e62 100644
--- a/gcc/targhooks.h
+++ b/gcc/targhooks.h
@@ -304,7 +304,4 @@ extern rtx default_memtag_untagged_pointer (rtx, rtx);
extern HOST_WIDE_INT default_gcov_type_size (void);
-extern int default_fortran_real_kind_number (machine_mode);
-extern tree default_fortran_real_kind_type (int);
-extern bool default_fortran_real_kind_float128_p (int);
#endif /* GCC_TARGHOOKS_H */
diff --git a/gcc/tree.h b/gcc/tree.h
index f3b47f81a09..7542d97ce12 100644
--- a/gcc/tree.h
+++ b/gcc/tree.h
@@ -4225,8 +4225,6 @@ tree_strip_any_location_wrapper (tree exp)
#define complex_double_type_node global_trees[TI_COMPLEX_DOUBLE_TYPE]
#define complex_long_double_type_node global_trees[TI_COMPLEX_LONG_DOUBLE_TYPE]
-#define complex_float128_type_node global_trees[TI_COMPLEX_FLOAT128_TYPE]
-
#define COMPLEX_FLOATN_NX_TYPE_NODE(IDX) global_trees[TI_COMPLEX_FLOATN_NX_TYPE_FIRST + (IDX)]
#define void_type_node global_trees[TI_VOID_TYPE]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-21 2:51 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-21 2:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:e4dc538c3ebe51f08b98e5620964795faacc799f
commit e4dc538c3ebe51f08b98e5620964795faacc799f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 20 22:50:25 2021 -0400
Revert patches.
2021-10-20 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New
declaration.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(constant_generates_lxvkq): New function.
* config/rs6000/rs6000.opt (-mieee128-constant): New debug
option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
gcc/
Revert patches.
* config/rs6000/constraints.md (eP): Update comment.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIW.
(vsx_prefixed_constant): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (constant_generates_xxspltiw): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(constant_generates_xxspltiw): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec.
(xxspltiw_<mode>_internal): New insns.
(VSX prefixed constant splitter): Add XXSPLTIW support.
* config/rs6000/rs6000.opt (-msplat-word-constant): New debug
switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/constraints.md | 8 +-
gcc/config/rs6000/predicates.md | 34 +----
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 118 +--------------
gcc/config/rs6000/rs6000.md | 17 ---
gcc/config/rs6000/rs6000.opt | 8 --
gcc/config/rs6000/vsx.md | 28 ++--
gcc/doc/md.texi | 4 -
.../gcc.target/powerpc/float128-constant.c | 160 ---------------------
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 -------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 --------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
14 files changed, 18 insertions(+), 570 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index a4b05837fa6..7d594872a78 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -214,17 +214,11 @@
(match_operand 0 "cint34_operand"))
;; A SF/DF scalar constant or a vector constant that can be loaded into vector
-;; registers with one prefixed instruction such as XXSPLTIDP or XXSPLTIW.
+;; registers with one prefixed instruction such as XXSPLTIDP.
(define_constraint "eP"
"A constant that can be loaded into a VSX register with one prefixed insn."
(match_operand 0 "vsx_prefixed_constant"))
-;; A TF/KF scalar constant or a vector constant that can load certain IEEE
-;; 128-bit constants into vector registers using LXVKQ.
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded into VSX registers."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 46ea61d64ac..fefa420ed67 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -606,14 +606,8 @@
if (TARGET_POWER10
&& constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
{
- if (constant_generates_lxvkq (&vsx_const))
- return true;
-
if (constant_generates_xxspltidp (&vsx_const))
return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -626,7 +620,7 @@
;; Return 1 if the operand is a 64-bit floating point scalar constant or a
;; vector constant that can be loaded to a VSX register with one prefixed
-;; instruction, such as XXSPLTIDP or XXSPLTIW.
+;; instruction, such as XXSPLTIDP.
;;
;; In addition regular constants, we also recognize constants formed with the
;; VEC_DUPLICATE insn from scalar constants.
@@ -657,29 +651,9 @@
if (constant_generates_xxspltidp (&vsx_const))
return true;
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
-
return false;
})
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,const_double")
-{
- rs6000_const vsx_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10
- || !TARGET_VSX)
- return false;
-
- return (constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT)
- && constant_generates_lxvkq (&vsx_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -730,14 +704,8 @@
if (TARGET_POWER10
&& constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT))
{
- if (constant_generates_lxvkq (&vsx_const))
- return true;
-
if (constant_generates_xxspltidp (&vsx_const))
return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
}
if (TARGET_P9_VECTOR
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 20cb092e159..ec4f78d9241 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -259,8 +259,6 @@ typedef struct {
extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *,
rs6000_const_splat);
extern unsigned constant_generates_xxspltidp (rs6000_const *);
-extern unsigned constant_generates_xxspltiw (rs6000_const *);
-extern unsigned constant_generates_lxvkq (rs6000_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 22f5d701908..b041db3c728 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate XXSPLTIW or XXSPLTIDP, don't generate XXSPLTIB and a
- sign extend operation. */
- else if (vsx_prefixed_constant (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -7001,26 +6996,12 @@ output_vec_const_move (rtx *operands)
if (constant_to_bytes (vec, mode, &vsx_const,
RS6000_CONST_SPLAT_16_BYTES))
{
- unsigned imm = constant_generates_lxvkq (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "lxvkq %x0,%2";
- }
-
- imm = constant_generates_xxspltidp (&vsx_const);
+ unsigned imm = constant_generates_xxspltidp (&vsx_const);
if (imm)
{
operands[2] = GEN_INT (imm);
return "xxspltidp %x0,%2";
}
-
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
}
}
@@ -26788,9 +26769,6 @@ prefixed_xxsplti_p (rtx_insn *insn)
{
if (constant_generates_xxspltidp (&vsx_const))
return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
}
return false;
@@ -29027,100 +29005,6 @@ constant_generates_xxspltidp (rs6000_const *vsx_const)
return sf_value;
}
-/* Determine if a vector constant can be loaded with XXSPLTIW. Return zero if
- the XXSPLTIW instruction cannot be used. Otherwise return the immediate
- value to be used with the XXSPLTIW instruction. */
-
-unsigned
-constant_generates_xxspltiw (rs6000_const *vsx_const)
-{
- if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX)
- return 0;
-
- /* Only recognize XXSPLTIW for 16-byte vector constants (or 8-byte scalar
- constants that have been splatted to 128-bits). */
- if (vsx_const->total_size != 16)
- return 0;
-
- if (!vsx_const->all_words_same)
- return 0;
-
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (vsx_const->all_bytes_same)
- return 0;
-
- /* See if we can use VSPLTISH or VSPLTISW. */
- if (vsx_const->all_half_words_same)
- {
- unsigned short h_word = vsx_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_h_word))
- return 0;
- }
-
- unsigned int word = vsx_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_word))
- return 0;
-
- return vsx_const->words[0];
-}
-
-/* Determine if an IEEE 128-bit constant can be loaded with LXVKQ. Return zero
- if the LXVKQ instruction cannot be used. Otherwise return the immediate
- value to be used with the LXVKQ instruction. */
-
-unsigned
-constant_generates_lxvkq (rs6000_const *vsx_const)
-{
- /* Is the instruction supported with power10 code generation, IEEE 128-bit
- floating point hardware and VSX registers are available. */
- if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10
- || !TARGET_VSX)
- return 0;
-
- /* Only recognize LXVKQ for 16-byte (4 word) vector constants. */
- unsigned total_size = vsx_const->total_size;
- if (total_size != 16)
- return 0;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- if (vsx_const->words[1] != 0
- || vsx_const->words[2] != 0
- || vsx_const->words[3] != 0)
- return 0;
-
- /* See if we have a match. */
- switch (vsx_const->words[0])
- {
- case 0x3FFF0000U: return 1; /* IEEE 128-bit +1.0. */
- case 0x40000000U: return 2; /* IEEE 128-bit +2.0. */
- case 0x40008000U: return 3; /* IEEE 128-bit +3.0. */
- case 0x40010000U: return 4; /* IEEE 128-bit +4.0. */
- case 0x40014000U: return 5; /* IEEE 128-bit +5.0. */
- case 0x40018000U: return 6; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: return 7; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: return 8; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: return 9; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: return 16; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: return 17; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: return 18; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: return 19; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: return 20; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: return 21; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: return 22; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: return 23; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: return 24; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- break;
- }
-
- return 0;
-}
-
\f
struct gcc_target targetm = TARGET_INITIALIZER;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3c94e547939..2633ad9f815 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -157,7 +157,6 @@
UNSPEC_HASHST
UNSPEC_HASHCHK
UNSPEC_XXSPLTIDP_CONST
- UNSPEC_XXSPLTIW_CONST
])
;;
@@ -8233,15 +8232,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-(define_insn "xxspltiw_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW_CONST))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
(define_split
[(set (match_operand:SFDF 0 "vsx_register_operand")
(match_operand:SFDF 1 "vsx_prefixed_constant"))]
@@ -8262,13 +8252,6 @@
DONE;
}
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- emit_insn (gen_xxspltiw_<mode>_internal (dest, GEN_INT (imm)));
- DONE;
- }
-
else
gcc_unreachable ();
})
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 3ddac80289c..429da57d19d 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,14 +644,6 @@ msplat-float-constant
Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the XXSPLTIDP instruction.
-msplat-word-constant
-Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the XXSPLTIW instruction.
-
-mieee128-constant
-Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the LXVKQ instruction.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ce8402101ef..0ceecc1975c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,19 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ
+;; XXLSPLTI*
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
+ wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eP, eQ,
+ eP,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,46 +1216,46 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
+ vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
+ *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
+ *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
+ *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
+ p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ
+;; XXSPLTI*
;; VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa,
- wa, wa,
+ wa,
v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM,
- eP, eQ,
+ eP,
W, <nW>,
v, wZ"))]
@@ -1268,19 +1268,19 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
+ vecperm,
*, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *,
- *, *,
+ *,
20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>,
- p10, p10,
+ p10,
*, *,
*, *")])
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 41a568b7d4e..13b56279565 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3340,10 +3340,6 @@ A signed 34-bit integer constant if prefixed instructions are supported.
A scalar floating point constant or a vector constant that can be
loaded with one prefixed instruction to a VSX register.
-@item eQ
-An IEEE 128-bit constant that can be loaded into a VSX register with a
-single instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index e3286a786a5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..5f84930e1a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,7 +149,7 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-21 2:27 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-21 2:27 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c0e1470ccd169cdc4781f46f621a7c8535f4fbb2
commit c0e1470ccd169cdc4781f46f621a7c8535f4fbb2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 20 22:25:12 2021 -0400
Revert patches.
2021-10-20 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New
declaration.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(constant_generates_lxvkq): New function.
* config/rs6000/rs6000.opt (-mieee128-constant): New debug
option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIW.
(vsx_prefixed_constant): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (constant_generates_xxspltiw): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(constant_generates_xxspltiw): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec.
(xxspltiw_<mode>_internal): New insns.
(VSX prefixed constant splitter): Add XXSPLTIW support.
* config/rs6000/rs6000.opt (-msplat-word-constant): New debug
switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
2021-10-20 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eP): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(vsx_prefixed_constant): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(constant_generates_xxspltidp): New declaration.
* config/rs6000/rs6000.c (prefixed_xxsplti_p): New function.
(constant_generates_xxspltidp): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec.
(prefixed attribute): Add support for prefixed instructions to load
constants into VSX registers.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(xxspltidp_<mode>_internal): New insns.
(splitter for VSX prefix constants): New splitters.
* config/rs6000/rs6000.opt (-msplat-float-constant): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eP constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
2021-10-20 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/rs6000-protos.h (RS6000_CONST_*): New macros.
(rs6000_const_splat): New enum type.
(rs6000_const): New structure type.
(constant_to_bytes): New declaration.
* config/rs6000/rs6000.c (constant_integer_to_bytes): New helper
function.
(constant_floating_point_to_bytes): New helper function.
(constant_to_bytes): New function.
Diff:
---
gcc/config/rs6000/constraints.md | 12 -
gcc/config/rs6000/predicates.md | 87 ----
gcc/config/rs6000/rs6000-protos.h | 39 --
gcc/config/rs6000/rs6000.c | 530 ---------------------
gcc/config/rs6000/rs6000.md | 102 +---
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 32 +-
gcc/doc/md.texi | 8 -
.../gcc.target/powerpc/float128-constant.c | 160 -------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ---
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 --
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 --
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
19 files changed, 30 insertions(+), 1406 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 906fa44bec3..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,18 +213,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; A SF/DF scalar constant or a vector constant that can be loaded into vector
-;; registers with one prefixed instruction such as XXSPLTIDP.
-(define_constraint "eP"
- "A constant that can be loaded into a VSX register with one prefixed insn."
- (match_operand 0 "vsx_prefixed_constant"))
-
-;; A TF/KF scalar constant or a vector constant that can load certain IEEE
-;; 128-bit constants into vector registers using LXVKQ.
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded into VSX registers."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 46ea61d64ac..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,21 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_const vsx_const;
- if (TARGET_POWER10
- && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- {
- if (constant_generates_lxvkq (&vsx_const))
- return true;
-
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -624,62 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit floating point scalar constant or a
-;; vector constant that can be loaded to a VSX register with one prefixed
-;; instruction, such as XXSPLTIDP or XXSPLTIW.
-;;
-;; In addition regular constants, we also recognize constants formed with the
-;; VEC_DUPLICATE insn from scalar constants.
-;;
-;; We don't handle scalar integer constants here because the assumption is the
-;; normal integer constants will be loaded into GPR registers. For the
-;; constants that need to be loaded into vector registers, the instructions
-;; don't work well with TImode variables assigned a constant. This is because
-;; the 64-bit scalar constants are splatted into both halves of the register.
-
-(define_predicate "vsx_prefixed_constant"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- /* If we can generate the constant with 1-2 Altivec instructions, don't
- generate a prefixed instruction. */
- if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode))
- return false;
-
- /* Do we have prefixed instructions and are VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- rs6000_const vsx_const;
- if (!constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- return false;
-
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
-
- return false;
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,const_double")
-{
- rs6000_const vsx_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10
- || !TARGET_VSX)
- return false;
-
- return (constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT)
- && constant_generates_lxvkq (&vsx_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -724,22 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- /* Constants that can be generated with ISA 3.1 instructions are
- easy. */
- rs6000_const vsx_const;
- if (TARGET_POWER10
- && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT))
- {
- if (constant_generates_lxvkq (&vsx_const))
- return true;
-
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 20cb092e159..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,44 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to constants that are converted to
- byte, half-word, word, and double-word values. All fields are kept in big
- endian order. */
-#define RS6000_CONST_MAX_BITS 128 /* Largest constant size. */
-#define RS6000_CONST_MAX_BYTES (RS6000_CONST_MAX_BITS / 8)
-#define RS6000_CONST_MAX_HALF_WORDS (RS6000_CONST_MAX_BITS / 16)
-#define RS6000_CONST_MAX_WORDS (RS6000_CONST_MAX_BITS / 32)
-#define RS6000_CONST_MAX_DOUBLE_WORDS (RS6000_CONST_MAX_BITS / 64)
-
-/* If the constant is small, whether we will splat the constant to fill a
- vector. */
-typedef enum {
- RS6000_CONST_NO_SPLAT, /* Do not splat the constant. */
- RS6000_CONST_SPLAT_16_BYTES /* Splat to fill 16-bytes. */
-} rs6000_const_splat;
-
-typedef struct {
- /* Constant as various sized items. */
- unsigned HOST_WIDE_INT double_words[RS6000_CONST_MAX_DOUBLE_WORDS];
- unsigned int words[RS6000_CONST_MAX_WORDS];
- unsigned short half_words[RS6000_CONST_MAX_HALF_WORDS];
- unsigned char bytes[RS6000_CONST_MAX_BYTES];
-
- unsigned total_size; /* Size in bytes of the constant. */
- unsigned original_size; /* Size before a possible splat. */
- bool fp_constant_p; /* Is the constant floating point? */
- bool all_double_words_same; /* Are the double words all equal? */
- bool all_words_same; /* Are the words all equal? */
- bool all_half_words_same; /* Are the halft words all equal? */
- bool all_bytes_same; /* Are the bytes all equal? */
-} rs6000_const;
-
-extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *,
- rs6000_const_splat);
-extern unsigned constant_generates_xxspltidp (rs6000_const *);
-extern unsigned constant_generates_xxspltiw (rs6000_const *);
-extern unsigned constant_generates_lxvkq (rs6000_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 282505471ff..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate XXSPLTIW or XXSPLTIDP, don't generate XXSPLTIB and a
- sign extend operation. */
- else if (vsx_prefixed_constant (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6995,35 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (TARGET_PREFIXED)
- {
- rs6000_const vsx_const;
- if (constant_to_bytes (vec, mode, &vsx_const,
- RS6000_CONST_SPLAT_16_BYTES))
- {
- unsigned imm = constant_generates_lxvkq (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "lxvkq %x0,%2";
- }
-
- imm = constant_generates_xxspltidp (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "xxspltidp %x0,%2";
- }
-
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26758,44 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether an instruction is a prefixed XXSPLTI* instruction. This is called
- from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_const vsx_const;
- if (constant_to_bytes (src, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- {
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28659,464 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the constant structure. */
-
-static void
-constant_integer_to_bytes (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_const *info)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- info->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the rs6000 constant structure. */
-
-static void
-constant_floating_point_to_bytes (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_const *info)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[RS6000_CONST_MAX_WORDS];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= RS6000_CONST_MAX_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- info->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-
- /* Mark that this constant involes floating point. */
- info->fp_constant_p = true;
-}
-
-/* Convert an RTL constant OP with mode MODE to an internal structure INFO.
- Possibly splat the constant to a larger size (SPLAT).
-
- Break out the constant out to bytes, half words, words, and double words.
- Return true if we have successfully broken out a constant.
-
- We handle CONST_INT, CONST_DOUBLE, CONST_VECTOR, and VEC_DUPLICATE of
- constants. */
-
-bool
-constant_to_bytes (rtx op,
- machine_mode mode,
- rs6000_const *info,
- rs6000_const_splat splat)
-{
- /* Initialize the constant structure. */
- memset ((void *)info, 0, sizeof (rs6000_const));
-
- /* Assume plain integer constants are DImode. */
- if (mode == VOIDmode)
- mode = CONST_INT_P (op) ? DImode : GET_MODE (op);
-
- if (mode == VOIDmode)
- return false;
-
- unsigned size = GET_MODE_SIZE (mode);
-
- if (size > RS6000_CONST_MAX_BYTES)
- return false;
-
- /* Set up the bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- constant_integer_to_bytes (op, mode, 0, info);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- {
- mode = DFmode;
- size = GET_MODE_SIZE (DFmode);
- }
-
- constant_floating_point_to_bytes (op, mode, 0, info);
- break;
- }
-
- /* Vector constants, iterate over each element. On little endian
- systems, we have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t ele_size = GET_MODE_SIZE (ele_mode);
- size_t nunits = GET_MODE_NUNITS (mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = CONST_VECTOR_ELT (op, num);
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * ele_size;
-
- if (CONST_INT_P (ele))
- constant_integer_to_bytes (ele, ele_mode, byte_num, info);
- else if (CONST_DOUBLE_P (ele))
- constant_floating_point_to_bytes (ele, ele_mode, byte_num, info);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant.
- Since we are duplicating the element, we don't have to worry about
- endian issues. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t ele_size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
- size_t nunits = GET_MODE_NUNITS (mode);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * ele_size;
-
- if (CONST_INT_P (ele))
- constant_integer_to_bytes (ele, ele_mode, byte_num, info);
- else
- constant_floating_point_to_bytes (ele, ele_mode, byte_num, info);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- unsigned total_size = size;
-
- /* Possibly splat the constant to fill a vector size. */
- if (splat == RS6000_CONST_SPLAT_16_BYTES)
- {
- if (size < 16)
- {
- total_size = 16;
- if ((total_size % size) != 0)
- return false;
-
- for (size_t offset = size; offset < total_size; offset += size)
- memcpy ((void *) &info->bytes[offset],
- (void *) &info->bytes[0],
- size);
- }
- }
-
- else if (splat != RS6000_CONST_NO_SPLAT)
- return false;
-
- /* Remember total/original sizes. */
- info->total_size = total_size;
- info->original_size = size;
-
- /* Determine if the bytes are all the same. */
- unsigned char first_byte = info->bytes[0];
- info->all_bytes_same = true;
- for (size_t i = 1; i < total_size; i++)
- if (first_byte != info->bytes[i])
- {
- info->all_bytes_same = false;
- break;
- }
-
- /* Pack half words together & determine if all of the half words are the
- same. */
- for (size_t i = 0; i < total_size; i += 2)
- info->half_words[i / 2] = ((info->bytes[i] << 8)
- | info->bytes[i + 1]);
-
- unsigned short first_hword = info->half_words[0];
- info->all_half_words_same = true;
- for (size_t i = 1; i < total_size / 2; i++)
- if (first_hword != info->half_words[i])
- {
- info->all_half_words_same = false;
- break;
- }
-
- /* Pack words together & determine if all of the words are the same. */
- for (size_t i = 0; i < total_size; i += 4)
- info->words[i / 4] = ((info->bytes[i] << 24)
- | (info->bytes[i + 1] << 16)
- | (info->bytes[i + 2] << 8)
- | info->bytes[i + 3]);
-
- unsigned int first_word = info->words[0];
- info->all_words_same = true;
- for (size_t i = 1; i < total_size / 4; i++)
- if (first_word != info->words[i])
- {
- info->all_words_same = false;
- break;
- }
-
- /* Pack double words together & determine if all of the double words are the
- same. */
- for (size_t i = 0; i < total_size; i += 8)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | info->bytes[i + j];
-
- info->double_words[i / 8] = d_word;
- }
-
- unsigned HOST_WIDE_INT first_dword = info->double_words[0];
- info->all_double_words_same = true;
- for (size_t i = 1; i < total_size / 8; i++)
- if (first_dword != info->double_words[i])
- {
- info->all_double_words_same = false;
- break;
- }
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. Return zero if
- the XXSPLTIDP instruction cannot be used. Otherwise return the immediate
- value to be used with the XXSPLTIDP instruction. */
-
-unsigned
-constant_generates_xxspltidp (rs6000_const *vsx_const)
-{
- if (!TARGET_SPLAT_FLOAT_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX)
- return 0;
-
- /* Only recognize XXSPLTIDP for 16-byte vector constants (or 8-byte scalar
- constants that have been splatted to 128-bits). */
- if (vsx_const->total_size != 16)
- return 0;
-
- /* Make sure that the two 64-bit segments are the same. */
- if (!vsx_const->all_double_words_same)
- return 0;
-
- /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP.
- Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */
- if (vsx_const->all_bytes_same
- || vsx_const->all_half_words_same
- || vsx_const->all_words_same)
- return 0;
-
- unsigned HOST_WIDE_INT value = vsx_const->double_words[0];
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and the signalling NaN bit pattern. Recognize infinity and
- negative infinity. */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define RS6000_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define RS6000_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define RS6000_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define RS6000_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (value != RS6000_CONST_DF_NAN
- && value != RS6000_CONST_DF_NANS
- && value != RS6000_CONST_DF_INF
- && value != RS6000_CONST_DF_NEG_INF)
- {
- /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for
- the exponent, and 52 bits for the mantissa (not counting the hidden
- bit used for normal numbers). NaN values have the exponent set to all
- 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */
-
- int df_exponent = (value >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return 0;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return 0;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vsx_const->words[0], vsx_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return 0;
-
- /* Return the immediate to be used. */
- return sf_value;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. Return zero if
- the XXSPLTIW instruction cannot be used. Otherwise return the immediate
- value to be used with the XXSPLTIW instruction. */
-
-unsigned
-constant_generates_xxspltiw (rs6000_const *vsx_const)
-{
- if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX)
- return 0;
-
- if (!vsx_const->all_words_same)
- return 0;
-
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (vsx_const->all_bytes_same)
- return 0;
-
- /* See if we can use VSPLTISH or VSPLTISW. */
- if (vsx_const->all_half_words_same)
- {
- unsigned short h_word = vsx_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_h_word))
- return 0;
- }
-
- unsigned int word = vsx_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_word))
- return 0;
-
- return vsx_const->words[0];
-}
-
-/* Determine if an IEEE 128-bit constant can be loaded with LXVKQ. Return zero
- if the LXVKQ instruction cannot be used. Otherwise return the immediate
- value to be used with the LXVKQ instruction. */
-
-unsigned
-constant_generates_lxvkq (rs6000_const *vsx_const)
-{
- /* Is the instruction supported with power10 code generation, IEEE 128-bit
- floating point hardware and VSX registers are available. */
- if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10
- || !TARGET_VSX)
- return 0;
-
- /* Only recognize LXVKQ for 16-byte (4 word) vector constants. */
- unsigned total_size = vsx_const->total_size;
- if (total_size != 16)
- return 0;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- if (vsx_const->words[1] != 0
- || vsx_const->words[2] != 0
- || vsx_const->words[3] != 0)
- return 0;
-
- /* See if we have a match. */
- switch (vsx_const->words[0])
- {
- case 0x3FFF0000U: return 1; /* IEEE 128-bit +1.0. */
- case 0x40000000U: return 2; /* IEEE 128-bit +2.0. */
- case 0x40008000U: return 3; /* IEEE 128-bit +3.0. */
- case 0x40010000U: return 4; /* IEEE 128-bit +4.0. */
- case 0x40014000U: return 5; /* IEEE 128-bit +5.0. */
- case 0x40018000U: return 6; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: return 7; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: return 8; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: return 9; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: return 16; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: return 17; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: return 18; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: return 19; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: return 20; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: return 21; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: return 22; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: return 23; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: return 24; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- break;
- }
-
- return 0;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3c94e547939..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -156,8 +156,6 @@
UNSPEC_PEXTD
UNSPEC_HASHST
UNSPEC_HASHCHK
- UNSPEC_XXSPLTIDP_CONST
- UNSPEC_XXSPLTIW_CONST
])
;;
@@ -316,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7766,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eP"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7798,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8067,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eP"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8095,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8136,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eP"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8170,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -8216,62 +8206,6 @@
(set_attr "length"
"*, *, *, *, *, 8,
12, 16, *")])
-
-;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
-;; constants that look like DFmode floating point values where both elements
-;; are the same. The constant has to be expressible as a SFmode constant that
-;; is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP_CONST))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxspltiw_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW_CONST))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:SFDF 0 "vsx_register_operand")
- (match_operand:SFDF 1 "vsx_prefixed_constant"))]
- "TARGET_POWER10"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
- rs6000_const vsx_const;
-
- if (!constant_to_bytes (src, <MODE>mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- gcc_unreachable ();
-
- unsigned imm = constant_generates_xxspltidp (&vsx_const);
- if (imm)
- {
- emit_insn (gen_xxspltidp_<mode>_internal (dest, GEN_INT (imm)));
- DONE;
- }
-
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- emit_insn (gen_xxspltiw_<mode>_internal (dest, GEN_INT (imm)));
- DONE;
- }
-
- else
- gcc_unreachable ();
-})
\f
(define_expand "mov<mode>"
[(set (match_operand:FMOVE128 0 "general_operand")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 3ddac80289c..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,18 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-msplat-float-constant
-Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the XXSPLTIDP instruction.
-
-msplat-word-constant
-Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the XXSPLTIW instruction.
-
-mieee128-constant
-Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the LXVKQ instruction.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ce8402101ef..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eP, eQ,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa, wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eP, eQ,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *, *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10, p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 41a568b7d4e..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3336,14 +3336,6 @@ A constant whose negation is a signed 16-bit constant.
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eP
-A scalar floating point constant or a vector constant that can be
-loaded with one prefixed instruction to a VSX register.
-
-@item eQ
-An IEEE 128-bit constant that can be loaded into a VSX register with a
-single instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index e3286a786a5..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 27764ddbc83..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 1f0475cf47a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 02d0c6d66a2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 59418d3bb0a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,8 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-21 0:37 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-21 0:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:72eb78e13a4ff90aa3b1b7d2384fae076e639d32
commit 72eb78e13a4ff90aa3b1b7d2384fae076e639d32
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 20 20:37:15 2021 -0400
Revert patches.
2021-10-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIW.
(vsx_prefixed_constant): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (constant_generates_xxspltiw): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(constant_generates_xxspltiw): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec.
(xxspltiw_<mode>_internal): New insns.
(VSX prefixed constant splitter): Add XXSPLTIW support.
* config/rs6000/rs6000.opt (-msplat-word-constant): New debug
switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/predicates.md | 11 +---
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 49 ----------------
gcc/config/rs6000/rs6000.md | 17 ------
gcc/config/rs6000/rs6000.opt | 4 --
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ---------
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ----------------------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----------------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 --------------------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
10 files changed, 2 insertions(+), 289 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4b07850eb64..fefa420ed67 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -608,9 +608,6 @@
{
if (constant_generates_xxspltidp (&vsx_const))
return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -623,7 +620,7 @@
;; Return 1 if the operand is a 64-bit floating point scalar constant or a
;; vector constant that can be loaded to a VSX register with one prefixed
-;; instruction, such as XXSPLTIDP or XXSPLTIW.
+;; instruction, such as XXSPLTIDP.
;;
;; In addition regular constants, we also recognize constants formed with the
;; VEC_DUPLICATE insn from scalar constants.
@@ -654,9 +651,6 @@
if (constant_generates_xxspltidp (&vsx_const))
return true;
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
-
return false;
})
@@ -712,9 +706,6 @@
{
if (constant_generates_xxspltidp (&vsx_const))
return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
}
if (TARGET_P9_VECTOR
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 0b93bc3cc0e..ec4f78d9241 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -259,7 +259,6 @@ typedef struct {
extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *,
rs6000_const_splat);
extern unsigned constant_generates_xxspltidp (rs6000_const *);
-extern unsigned constant_generates_xxspltiw (rs6000_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4f24d9491da..b041db3c728 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate XXSPLTIW or XXSPLTIDP, don't generate XXSPLTIB and a
- sign extend operation. */
- else if (vsx_prefixed_constant (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -7007,13 +7002,6 @@ output_vec_const_move (rtx *operands)
operands[2] = GEN_INT (imm);
return "xxspltidp %x0,%2";
}
-
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
}
}
@@ -26781,9 +26769,6 @@ prefixed_xxsplti_p (rtx_insn *insn)
{
if (constant_generates_xxspltidp (&vsx_const))
return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
}
return false;
@@ -29020,40 +29005,6 @@ constant_generates_xxspltidp (rs6000_const *vsx_const)
return sf_value;
}
-/* Determine if a vector constant can be loaded with XXSPLTIW. Return zero if
- the XXSPLTIW instruction cannot be used. Otherwise return the immediate
- value to be used with the XXSPLTIW instruction. */
-
-unsigned
-constant_generates_xxspltiw (rs6000_const *vsx_const)
-{
- if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX)
- return 0;
-
- if (!vsx_const->all_words_same)
- return 0;
-
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (vsx_const->all_bytes_same)
- return 0;
-
- /* See if we can use VSPLTISH or VSPLTISW. */
- if (vsx_const->all_half_words_same)
- {
- unsigned short h_word = vsx_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_h_word))
- return 0;
- }
-
- unsigned int word = vsx_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_word))
- return 0;
-
- return vsx_const->words[0];
-}
-
\f
struct gcc_target targetm = TARGET_INITIALIZER;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3c94e547939..2633ad9f815 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -157,7 +157,6 @@
UNSPEC_HASHST
UNSPEC_HASHCHK
UNSPEC_XXSPLTIDP_CONST
- UNSPEC_XXSPLTIW_CONST
])
;;
@@ -8233,15 +8232,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-(define_insn "xxspltiw_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW_CONST))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
(define_split
[(set (match_operand:SFDF 0 "vsx_register_operand")
(match_operand:SFDF 1 "vsx_prefixed_constant"))]
@@ -8262,13 +8252,6 @@
DONE;
}
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- emit_insn (gen_xxspltiw_<mode>_internal (dest, GEN_INT (imm)));
- DONE;
- }
-
else
gcc_unreachable ();
})
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index ec607a7aee7..429da57d19d 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,10 +644,6 @@ msplat-float-constant
Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the XXSPLTIDP instruction.
-msplat-word-constant
-Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the XXSPLTIW instruction.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..5f84930e1a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,7 +149,7 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-20 22:26 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-20 22:26 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cb5b3200e1d9226f6efa4afdae4d5f5d963d215d
commit cb5b3200e1d9226f6efa4afdae4d5f5d963d215d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 20 18:25:50 2021 -0400
Revert patches.
2021-10-20 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIW.
(vsx_prefixed_constant): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (constant_generates_xxspltiw): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(constant_generates_xxspltiw): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec.
(xxspltiw_<mode>_internal): New insns.
(VSX prefixed constant splitter): Add XXSPLTIW support.
* config/rs6000/rs6000.opt (-msplat-word-constant): New debug
switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
2021-10-20 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eP): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(vsx_prefixed_constant): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(constant_generates_xxspltidp): New declaration.
* config/rs6000/rs6000.c (prefixed_xxsplti_p): New function.
(constant_generates_xxspltidp): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec.
(prefixed attribute): Add support for prefixed instructions to load
constants into VSX registers.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(xxspltidp_<mode>_internal): New insns.
(splitter for VSX prefix constants): New splitters.
* config/rs6000/rs6000.opt (-msplat-float-constant): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eP constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
Diff:
---
gcc/config/rs6000/constraints.md | 6 -
gcc/config/rs6000/predicates.md | 66 -------
gcc/config/rs6000/rs6000-protos.h | 3 -
gcc/config/rs6000/rs6000.c | 198 ---------------------
gcc/config/rs6000/rs6000.md | 103 ++---------
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 32 +---
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 -------
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 -------
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ---
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 -------
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ------
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 -------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -------
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
17 files changed, 30 insertions(+), 840 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 7d594872a78..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,12 +213,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; A SF/DF scalar constant or a vector constant that can be loaded into vector
-;; registers with one prefixed instruction such as XXSPLTIDP.
-(define_constraint "eP"
- "A constant that can be loaded into a VSX register with one prefixed insn."
- (match_operand 0 "vsx_prefixed_constant"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index e6b48fadbfd..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,19 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_const vsx_const;
-
- if (TARGET_POWER10
- && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- {
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -622,45 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit floating point scalar constant or a
-;; vector constant that can be loaded to a VSX register with one prefixed
-;; instruction, such as XXSPLTIDP or XXSPLTIW.
-;;
-;; In addition regular constants, we also recognize constants formed with the
-;; VEC_DUPLICATE insn from scalar constants.
-;;
-;; We don't handle scalar integer constants here because the assumption is the
-;; normal integer constants will be loaded into GPR registers. For the
-;; constants that need to be loaded into vector registers, the instructions
-;; don't work well with TImode variables assigned a constant. This is because
-;; the 64-bit scalar constants are splatted into both halves of the register.
-
-(define_predicate "vsx_prefixed_constant"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- /* If we can generate the constant with 1-2 Altivec instructions, don't
- generate a prefixed instruction. */
- if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode))
- return false;
-
- /* Do we have prefixed instructions and are VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- rs6000_const vsx_const;
- if (!constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- return false;
-
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
-
- return false;
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -705,20 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- /* Constants that can be generated with ISA 3.1 instructions are
- easy. */
- rs6000_const vsx_const;
-
- if (TARGET_POWER10
- && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT))
- {
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 0b93bc3cc0e..a3fecbb7812 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -258,8 +257,6 @@ typedef struct {
extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *,
rs6000_const_splat);
-extern unsigned constant_generates_xxspltidp (rs6000_const *);
-extern unsigned constant_generates_xxspltiw (rs6000_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 9889e42241c..e2f48f5a1e2 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate XXSPLTIW or XXSPLTIDP, don't generate XXSPLTIB and a
- sign extend operation. */
- else if (vsx_prefixed_constant (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6995,28 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (TARGET_PREFIXED)
- {
- rs6000_const vsx_const;
- if (constant_to_bytes (vec, mode, &vsx_const,
- RS6000_CONST_SPLAT_16_BYTES))
- {
- unsigned imm = constant_generates_xxspltidp (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "xxspltidp %x0,%2";
- }
-
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26751,44 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether an instruction is a prefixed XXSPLTI* instruction. This is called
- from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_const vsx_const;
- if (constant_to_bytes (src, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- {
- if (constant_generates_xxspltidp (&vsx_const))
- return true;
-
- if (constant_generates_xxspltiw (&vsx_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28917,139 +28852,6 @@ constant_to_bytes (rtx op,
return true;
}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. Return zero if
- the XXSPLTIDP instruction cannot be used. Otherwise return the immediate
- value to be used with the XXSPLTIDP instruction. */
-
-unsigned
-constant_generates_xxspltidp (rs6000_const *vsx_const)
-{
- if (!TARGET_SPLAT_FLOAT_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX)
- return 0;
-
- /* Make sure that the two 64-bit segments are the same. */
- if (!vsx_const->all_double_words_same)
- return 0;
-
- /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP.
- Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */
- if (vsx_const->all_bytes_same
- || vsx_const->all_half_words_same
- || vsx_const->all_words_same)
- return 0;
-
- unsigned HOST_WIDE_INT value = vsx_const->double_words[0];
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and the signalling NaN bit pattern. Recognize infinity and
- negative infinity. */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define RS6000_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define RS6000_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define RS6000_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define RS6000_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (value != RS6000_CONST_DF_NAN
- && value != RS6000_CONST_DF_NANS
- && value != RS6000_CONST_DF_INF
- && value != RS6000_CONST_DF_NEG_INF)
- {
- /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for
- the exponent, and 52 bits for the mantissa (not counting the hidden
- bit used for normal numbers). NaN values have the exponent set to all
- 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */
-
- int df_exponent = (value >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return 0;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return 0;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vsx_const->words[0], vsx_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return 0;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return 0;
-
- /* Return the immediate to be used. */
- return sf_value;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. Return zero if
- the XXSPLTIW instruction cannot be used. Otherwise return the immediate
- value to be used with the XXSPLTIW instruction. */
-
-unsigned
-constant_generates_xxspltiw (rs6000_const *vsx_const)
-{
- if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX)
- return 0;
-
- if (!vsx_const->all_words_same)
- return 0;
-
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (vsx_const->all_bytes_same)
- return 0;
-
- /* See if we can use VSPLTISH or VSPLTISW. */
- if (vsx_const->all_half_words_same)
- {
- unsigned short h_word = vsx_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_h_word))
- return 0;
- }
-
- unsigned int word = vsx_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_word))
- return 0;
-
- return vsx_const->words[0];
-}
-
\f
struct gcc_target targetm = TARGET_INITIALIZER;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 19cd1ba7022..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -156,8 +156,6 @@
UNSPEC_PEXTD
UNSPEC_HASHST
UNSPEC_HASHCHK
- UNSPEC_XXSPLTIDP_CONST
- UNSPEC_XXSPLTIW_CONST
])
;;
@@ -316,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7766,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eP"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7798,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8067,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eP"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8095,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8136,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eP"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8170,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -8216,63 +8206,6 @@
(set_attr "length"
"*, *, *, *, *, 8,
12, 16, *")])
-
-;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
-;; constants that look like DFmode floating point values where both elements
-;; are the same. The constant has to be expressible as a SFmode constant that
-;; is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP_CONST))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxspltiw_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW_CONST))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:SFDF 0 "vsx_register_operand")
- (match_operand:SFDF 1 "vsx_prefixed_constant"))]
- "TARGET_POWER10"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
- rs6000_const vsx_const;
-
- if (!constant_to_bytes (src, <MODE>mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES))
- gcc_unreachable ();
-
- unsigned imm = constant_generates_xxspltidp (&vsx_const);
- if (imm)
- {
- emit_insn (gen_xxspltidp_<mode>_internal (dest, GEN_INT (imm)));
- DONE;
- }
-
- imm = constant_generates_xxspltiw (&vsx_const);
- if (imm)
- {
- emit_insn (gen_xxspltiw_<mode>_internal (dest, GEN_INT (imm)));
- DONE;
- }
-
- else
- gcc_unreachable ();
-})
-
\f
(define_expand "mov<mode>"
[(set (match_operand:FMOVE128 0 "general_operand")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index ec607a7aee7..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,14 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-msplat-float-constant
-Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the XXSPLTIDP instruction.
-
-msplat-word-constant
-Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save
-Generate (do not generate) code that uses the XXSPLTIW instruction.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0ceecc1975c..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI*
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eP,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI*
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eP,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,8 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-20 21:21 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-20 21:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:791797cc1855c096000e61b0b54c74e27de40614
commit 791797cc1855c096000e61b0b54c74e27de40614
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 20 17:20:58 2021 -0400
Revert patches.
2021-10-20 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/rs6000-protos.h (RS6000_CONST_*): New macros.
(rs6000_const_splat): New enum type.
(rs6000_const): New structure type.
(constant_to_bytes): New declaration.
* config/rs6000/rs6000.c (constant_integer_to_bytes): New helper
function.
(constant_floating_point_to_bytes): New helper function.
(constant_to_bytes): New function.
Diff:
---
gcc/config/rs6000/rs6000-protos.h | 35 -----
gcc/config/rs6000/rs6000.c | 263 --------------------------------------
2 files changed, 298 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index a3fecbb7812..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -222,41 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to constants that are converted to
- byte, half-word, word, and double-word values. All fields are kept in big
- endian order. */
-#define RS6000_CONST_MAX_BITS 128 /* Largest constant size. */
-#define RS6000_CONST_MAX_BYTES (RS6000_CONST_MAX_BITS / 8)
-#define RS6000_CONST_MAX_HALF_WORDS (RS6000_CONST_MAX_BITS / 16)
-#define RS6000_CONST_MAX_WORDS (RS6000_CONST_MAX_BITS / 32)
-#define RS6000_CONST_MAX_DOUBLE_WORDS (RS6000_CONST_MAX_BITS / 64)
-
-/* If the constant is small, whether we will splat the constant to fill a
- vector. */
-typedef enum {
- RS6000_CONST_NO_SPLAT, /* Do not splat the constant. */
- RS6000_CONST_SPLAT_16_BYTES /* Splat to fill 16-bytes. */
-} rs6000_const_splat;
-
-typedef struct {
- /* Constant as various sized items. */
- unsigned HOST_WIDE_INT double_words[RS6000_CONST_MAX_DOUBLE_WORDS];
- unsigned int words[RS6000_CONST_MAX_WORDS];
- unsigned short half_words[RS6000_CONST_MAX_HALF_WORDS];
- unsigned char bytes[RS6000_CONST_MAX_BYTES];
-
- unsigned total_size; /* Size in bytes of the constant. */
- unsigned original_size; /* Size before a possible splat. */
- bool fp_constant_p; /* Is the constant floating point? */
- bool all_double_words_same; /* Are the double words all equal? */
- bool all_words_same; /* Are the words all equal? */
- bool all_half_words_same; /* Are the halft words all equal? */
- bool all_bytes_same; /* Are the bytes all equal? */
-} rs6000_const;
-
-extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *,
- rs6000_const_splat);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index af37a556e94..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -28587,269 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the constant structure. */
-
-static void
-constant_integer_to_bytes (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_const *info)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- info->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the rs6000 constant structure. */
-
-static void
-constant_floating_point_to_bytes (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_const *info)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[RS6000_CONST_MAX_WORDS];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= RS6000_CONST_MAX_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- info->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-
- /* Mark that this constant involes floating point. */
- info->fp_constant_p = true;
-}
-
-/* Convert an RTL constant OP with mode MODE to an internal structure INFO. Possibly splat the constant to a larger size (SPLAT).
-
- Break out the constant out to bytes, half words, words, and double words.
- Return true if we have successfully broken out a constant.
-
- We handle CONST_INT, CONST_DOUBLE, CONST_VECTOR, and VEC_DUPLICATE of
- constants. */
-
-bool
-constant_to_bytes (rtx op,
- machine_mode mode,
- rs6000_const *info,
- rs6000_const_splat splat)
-{
- /* Initialize the constant structure. */
- memset ((void *)info, 0, sizeof (rs6000_const));
-
- /* Assume plain integer constants are DImode. */
- if (mode == VOIDmode)
- mode = CONST_INT_P (op) ? DImode : GET_MODE (op);
-
- if (mode == VOIDmode)
- return false;
-
- unsigned size = GET_MODE_SIZE (mode);
-
- if (size > RS6000_CONST_MAX_BYTES)
- return false;
-
- /* Set up the bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- constant_integer_to_bytes (op, mode, 0, info);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- {
- mode = DFmode;
- size = GET_MODE_SIZE (DFmode);
- }
-
- constant_floating_point_to_bytes (op, mode, 0, info);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t ele_size = GET_MODE_SIZE (ele_mode);
- size_t nunits = GET_MODE_NUNITS (mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = CONST_VECTOR_ELT (op, num);
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * ele_size;
-
- if (CONST_INT_P (ele))
- constant_integer_to_bytes (ele, ele_mode, byte_num, info);
- else if (CONST_DOUBLE_P (ele))
- constant_floating_point_to_bytes (ele, ele_mode, byte_num, info);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t ele_size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
- size_t nunits = GET_MODE_NUNITS (mode);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * ele_size;
-
- if (CONST_INT_P (ele))
- constant_integer_to_bytes (ele, ele_mode, byte_num, info);
- else
- constant_floating_point_to_bytes (ele, ele_mode, byte_num, info);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- unsigned total_size = size;
-
- /* Possibly splat the constant to fill a vector size. */
- if (splat == RS6000_CONST_SPLAT_16_BYTES)
- {
- if (size < 16)
- {
- total_size = 16;
- if ((total_size % size) != 0)
- return false;
-
- for (size_t offset = size; offset < total_size; offset += size)
- memcpy ((void *) &info->bytes[offset],
- (void *) &info->bytes[0],
- size);
- }
- }
-
- else if (splat != RS6000_CONST_NO_SPLAT)
- return false;
-
- /* Remember total/original sizes. */
- info->total_size = total_size;
- info->original_size = size;
-
- /* Determine if the bytes are all the same. */
- unsigned char first_byte = info->bytes[0];
- info->all_bytes_same = true;
- for (size_t i = 1; i < total_size; i++)
- if (first_byte != info->bytes[i])
- {
- info->all_bytes_same = false;
- break;
- }
-
- /* Pack half words together & determine if all of the half words are the
- same. */
- for (size_t i = 0; i < total_size; i += 2)
- info->half_words[i / 2] = ((info->bytes[i] << 8)
- | info->bytes[i + 1]);
-
- unsigned short first_hword = info->half_words[0];
- info->all_half_words_same = true;
- for (size_t i = 1; i < total_size / 2; i++)
- if (first_hword != info->half_words[i])
- {
- info->all_half_words_same = false;
- break;
- }
-
- /* Pack words together & determine if all of the words are the same. */
- for (size_t i = 0; i < total_size; i += 4)
- info->words[i / 4] = ((info->bytes[i] << 24)
- | (info->bytes[i + 1] << 16)
- | (info->bytes[i + 2] << 8)
- | info->bytes[i + 3]);
-
- unsigned int first_word = info->words[0];
- info->all_words_same = true;
- for (size_t i = 1; i < total_size / 4; i++)
- if (first_word != info->words[i])
- {
- info->all_words_same = false;
- break;
- }
-
- /* Pack double words together & determine if all of the double words are the
- same. */
- for (size_t i = 0; i < total_size; i += 8)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | info->bytes[i + j];
-
- info->double_words[i / 8] = d_word;
- }
-
- unsigned HOST_WIDE_INT first_dword = info->double_words[0];
- info->all_double_words_same = true;
- for (size_t i = 1; i < total_size / 8; i++)
- if (first_dword != info->double_words[i])
- {
- info->all_double_words_same = false;
- break;
- }
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-20 17:56 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-20 17:56 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a5378408a4899d89e45a1bba3a30642a201c2a59
commit a5378408a4899d89e45a1bba3a30642a201c2a59
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 20 13:54:38 2021 -0400
Revert patches.
2021-10-18 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(vsx_prefixed_constant): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (vec_const_use_xxspltiw): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec.
(xxspltiw_<mode>_internal): New insns.
(VSX prefixed constant splitter): Add XXSPLTIW support.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
2021-10-18 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eP): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(vsx_prefixed_constant): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec.
(prefixed attribute): Add support for prefixed instructions to load
* constants into VSX registers.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(xxspltidp_<mode>_internal): New insns.
(splitter for VSX prefix constants): New splitters.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eP constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
Diff:
---
gcc/config/rs6000/constraints.md | 11 -
gcc/config/rs6000/predicates.md | 87 ----
gcc/config/rs6000/rs6000-protos.h | 30 --
gcc/config/rs6000/rs6000.c | 486 ---------------------
gcc/config/rs6000/rs6000.md | 103 +----
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 32 +-
gcc/doc/md.texi | 7 -
.../gcc.target/powerpc/float128-constant.c | 160 -------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ---
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
19 files changed, 30 insertions(+), 1352 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index f5b524254ab..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,17 +213,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; A SF/DF scalar constant or a vector constant that can be loaded into vector
-;; registers with one prefixed instruction such as XXSPLTIDP.
-(define_constraint "eP"
- "A constant that can be loaded into a VSX register with one prefixed insn."
- (match_operand 0 "vsx_prefixed_constant"))
-
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c271b379f6d..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,21 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -624,62 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit floating point scalar constant or a
-;; vector constant that can be loaded to a VSX register with one prefixed
-;; instruction, such as XXSPLTIDP.
-;;
-;; In addition regular constants, we also recognize constants formed with the
-;; VEC_DUPLICATE insn from scalar constants.
-;;
-;; We don't handle scalar integer constants here because the assumption is the
-;; normal integer constants will be loaded into GPR registers. For the
-;; constants that need to be loaded into vector registers, the instructions
-;; don't work well with TImode variables assigned a constant. This is because
-;; the 64-bit scalar constants are splatted into both halves of the register.
-
-(define_predicate "vsx_prefixed_constant"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and are VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- /* If we can generate the constant with 1-2 Altivec instructions, don't
- generate a prefixed instruction. */
- if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode))
- return false;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- return false;
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_FLOAT128_HW || !TARGET_POWER10 || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_lxvkq (&vec_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -728,22 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 40a796d4461..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,35 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_HALF_WORDS (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_WORDS (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_DOUBLE_WORDS (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned HOST_WIDE_INT double_words[VECTOR_CONST_DOUBLE_WORDS];
- unsigned int words[VECTOR_CONST_WORDS];
- unsigned short half_words[VECTOR_CONST_HALF_WORDS];
- unsigned char bytes[VECTOR_CONST_BYTES];
-
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned int lxvkq_immediate; /* Immediate value for LXVKQ. */
- bool fp_constant_p; /* Is the constant floating point? */
- bool all_double_words_same; /* Are the double words all equal? */
- bool all_words_same; /* Are the words all equal? */
- bool all_half_words_same; /* Are the halft words all equal? */
- bool all_bytes_same; /* Are the bytes all equal? */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index fbcd307177c..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate XXSPLTIW, don't generate XXSPLTIB and a sign extend
- operation. */
- else if (vsx_prefixed_constant (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6995,28 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (TARGET_POWER10 && vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.words[0]);
- return "xxspltiw %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26751,41 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28649,430 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_WORDS];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-
- /* Mark that this constant involes floating point. */
- vec_const->fp_constant_p = true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- if (!vec_const->all_double_words_same)
- return false;
-
- /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP.
- Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */
- if (vec_const->all_bytes_same
- || vec_const->all_half_words_same
- || vec_const->all_words_same)
- return false;
-
- unsigned HOST_WIDE_INT value = vec_const->double_words[0];
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and the signalling NaN bit pattern. Recognize infinity and
- negative infinity. */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (value != VECTOR_CONST_DF_NAN
- && value != VECTOR_CONST_DF_NANS
- && value != VECTOR_CONST_DF_INF
- && value != VECTOR_CONST_DF_NEG_INF)
- {
- /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for
- the exponent, and 52 bits for the mantissa (not counting the hidden
- bit used for normal numbers). NaN values have the exponent set to all
- 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */
-
- int df_exponent = (value >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->xxspltidp_immediate = sf_value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const->all_words_same)
- return false;
-
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (vec_const->all_bytes_same)
- return false;
-
- /* See if we can use VSPLTISH or VSPLTISW. */
- if (vec_const->all_half_words_same)
- {
- unsigned short h_word = vec_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_h_word))
- return false;
- }
-
- unsigned int word = vec_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_word))
- return false;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_WORDS; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction, record the immediate needed for the
- instruction. */
- vec_const->lxvkq_immediate = immediate;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* Set up the vector bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- /* Scalars are treated as 64-bit integers. */
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_HALF_WORDS; i++)
- vec_const->half_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[(2 * i) + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_WORDS; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4 * i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_DOUBLE_WORDS; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8 * i) + j];
-
- vec_const->double_words[i] = d_word;
- }
-
- /* Determine if the double words, words, half words, and bytes are all
- equal. */
- unsigned HOST_WIDE_INT first_dword = vec_const->double_words[0];
- vec_const->all_double_words_same = true;
- for (size_t i = 1; i < VECTOR_CONST_DOUBLE_WORDS; i++)
- if (first_dword != vec_const->double_words[i])
- vec_const->all_double_words_same = false;
-
- unsigned int first_word = vec_const->words[0];
- vec_const->all_words_same = true;
- for (size_t i = 1; i < VECTOR_CONST_WORDS; i++)
- if (first_word != vec_const->words[i])
- vec_const->all_words_same = false;
-
- unsigned short first_hword = vec_const->half_words[0];
- vec_const->all_half_words_same = true;
- for (size_t i = 1; i < VECTOR_CONST_HALF_WORDS; i++)
- if (first_hword != vec_const->half_words[i])
- vec_const->all_half_words_same = false;
-
- unsigned char first_byte = vec_const->bytes[0];
- vec_const->all_bytes_same = true;
- for (size_t i = 1; i < VECTOR_CONST_BYTES; i++)
- if (first_byte != vec_const->bytes[i])
- vec_const->all_bytes_same = false;
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1963eb01ed7..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -156,8 +156,6 @@
UNSPEC_PEXTD
UNSPEC_HASHST
UNSPEC_HASHCHK
- UNSPEC_XXSPLTIDP_CONST
- UNSPEC_XXSPLTIW_CONST
])
;;
@@ -316,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7766,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eP"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7798,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8067,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eP"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8095,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8136,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eP"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8170,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -8216,63 +8206,6 @@
(set_attr "length"
"*, *, *, *, *, 8,
12, 16, *")])
-
-;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
-;; constants that look like DFmode floating point values where both elements
-;; are the same. The constant has to be expressible as a SFmode constant that
-;; is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_insn "xxspltidp_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP_CONST))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn "xxspltiw_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW_CONST))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:SFDF 0 "vsx_register_operand")
- (match_operand:SFDF 1 "vsx_prefixed_constant"))]
- "TARGET_POWER10"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
- rs6000_vec_const vec_const;
-
- if (!vec_const_to_bytes (src, <MODE>mode, &vec_const))
- gcc_unreachable ();
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- rtx imm = GEN_INT (vec_const.xxspltidp_immediate);
- emit_insn (gen_xxspltidp_<mode>_internal (dest, imm));
- DONE;
- }
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- rtx imm = GEN_INT (vec_const.words[0]);
- emit_insn (gen_xxspltiw_<mode>_internal (dest, imm));
- DONE;
- }
-
- else
- gcc_unreachable ();
-})
-
\f
(define_expand "mov<mode>"
[(set (match_operand:FMOVE128 0 "general_operand")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 015bf91b6d5..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,18 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index ce8402101ef..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eP, eQ,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa, wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eP, eQ,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *, *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10, p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index cd70e170955..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3336,13 +3336,6 @@ A constant whose negation is a signed 16-bit constant.
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eP
-A scalar floating point constant or a vector constant that can be
-loaded with one prefixed instruction to a VSX register.
-
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index f6becac1075..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,8 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-18 18:49 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-18 18:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d8efdc5887a864b8842e7d4053d9cff4e5324a64
commit d8efdc5887a864b8842e7d4053d9cff4e5324a64
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Oct 18 14:49:07 2021 -0400
Revert patches.
2021-10-18 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(vsx_prefixed_constant): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (vec_const_use_xxspltiw): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec.
(xxspltiw_<mode>_internal): New insns.
(VSX prefixed constant splitter): Add XXSPLTIW support.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/predicates.md | 14 -----
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 43 --------------
gcc/config/rs6000/rs6000.md | 17 ------
gcc/config/rs6000/rs6000.opt | 4 --
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ---------
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ----------------------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----------------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 --------------------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
10 files changed, 1 insertion(+), 287 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 40c4cba68ff..4b2bbdf40e8 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -608,9 +608,6 @@
{
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -647,14 +644,6 @@
if (!vec_const_to_bytes (op, mode, &vec_const))
return false;
- /* If we can generate the constant with 1-2 Altivec instructions, don't
- generate a prefixed instruction. */
- if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode))
- return false;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
if (vec_const_use_xxspltidp (&vec_const))
return true;
@@ -717,9 +706,6 @@
{
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
return easy_altivec_constant (op, mode);
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index b12f6b10c13..8eef955237a 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -249,7 +249,6 @@ typedef struct {
extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 20226169ba2..353ec2b572d 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate XXSPLTIW, don't generate XXSPLTIB and a sign extend
- operation. */
- else if (vsx_prefixed_constant (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -7003,12 +6998,6 @@ output_vec_const_move (rtx *operands)
operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
return "xxspltidp %x0,%2";
}
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.words[0]);
- return "xxspltiw %x0,%2";
- }
}
if (TARGET_P9_VECTOR
@@ -28795,38 +28784,6 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
return true;
}
-/* Determine if a vector constant can be loaded with XXSPLTIW. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const->all_words_same)
- return false;
-
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (vec_const->all_bytes_same)
- return false;
-
- /* See if we can use VSPLTISH or VSPLTISW. */
- if (vec_const->all_half_words_same)
- {
- unsigned short h_word = vec_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_h_word))
- return false;
- }
-
- unsigned int word = vec_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_word))
- return false;
-
- return true;
-}
-
/* Convert a vector constant to an internal structure, breaking it out to
bytes, half words, words, and double words. Return true if we have
successfully broken it out. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 1963eb01ed7..5d830e0db15 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -157,7 +157,6 @@
UNSPEC_HASHST
UNSPEC_HASHCHK
UNSPEC_XXSPLTIDP_CONST
- UNSPEC_XXSPLTIW_CONST
])
;;
@@ -8233,15 +8232,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-(define_insn "xxspltiw_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIW_CONST))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
(define_split
[(set (match_operand:SFDF 0 "vsx_register_operand")
(match_operand:SFDF 1 "vsx_prefixed_constant"))]
@@ -8262,13 +8252,6 @@
DONE;
}
- if (vec_const_use_xxspltiw (&vec_const))
- {
- rtx imm = GEN_INT (vec_const.words[0]);
- emit_insn (gen_xxspltiw_<mode>_internal (dest, imm));
- DONE;
- }
-
else
gcc_unreachable ();
})
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 332f61be0ba..1d7ce4cc94a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,10 +644,6 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..5f84930e1a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,7 +149,7 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-18 17:43 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-18 17:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:f70d3226e4df319f0b109c6e1e6505879c38be23
commit f70d3226e4df319f0b109c6e1e6505879c38be23
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Oct 18 13:42:24 2021 -0400
Revert patches.
2021-10-18 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eP): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(vsx_prefixed_constant): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (UNSPEC_VSX_PREFIXED_CONST): New unspec.
(prefixed attribute): Add support for prefixed instructions to load
* constants into VSX registers.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(xxspltidp_<mode>_internal): New insns.
(splitter for VSX prefix constants): New splitters.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eP constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
Diff:
---
gcc/config/rs6000/constraints.md | 6 -
gcc/config/rs6000/predicates.md | 51 ---
gcc/config/rs6000/rs6000-protos.h | 27 --
gcc/config/rs6000/rs6000.c | 387 ---------------------
gcc/config/rs6000/rs6000.md | 82 +----
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 32 +-
gcc/doc/md.texi | 4 -
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ----
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ----
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
14 files changed, 29 insertions(+), 809 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 7d594872a78..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,12 +213,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; A SF/DF scalar constant or a vector constant that can be loaded into vector
-;; registers with one prefixed instruction such as XXSPLTIDP.
-(define_constraint "eP"
- "A constant that can be loaded into a VSX register with one prefixed insn."
- (match_operand 0 "vsx_prefixed_constant"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4b2bbdf40e8..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,15 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -618,38 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit floating point scalar constant or a
-;; vector constant that can be loaded to a VSX register with one prefixed
-;; instruction, such as XXSPLTIDP.
-;;
-;; In addition regular constants, we also recognize constants formed with the
-;; VEC_DUPLICATE insn from scalar constants.
-;;
-;; We don't handle scalar integer constants here because the assumption is the
-;; normal integer constants will be loaded into GPR registers. For the
-;; constants that need to be loaded into vector registers, the instructions
-;; don't work well with TImode variables assigned a constant. This is because
-;; the 64-bit scalar constants are splatted into both halves of the register.
-
-(define_predicate "vsx_prefixed_constant"
- (match_code "const_double,const_vector,vec_duplicate")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and are VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- return false;
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -698,16 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 8eef955237a..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,32 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_HALF_WORDS (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_WORDS (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_DOUBLE_WORDS (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned HOST_WIDE_INT double_words[VECTOR_CONST_DOUBLE_WORDS];
- unsigned int words[VECTOR_CONST_WORDS];
- unsigned short half_words[VECTOR_CONST_HALF_WORDS];
- unsigned char bytes[VECTOR_CONST_BYTES];
-
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- bool fp_constant_p; /* Is the constant floating point? */
- bool all_double_words_same; /* Are the double words all equal? */
- bool all_words_same; /* Are the words all equal? */
- bool all_half_words_same; /* Are the halft words all equal? */
- bool all_bytes_same; /* Are the bytes all equal? */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 353ec2b572d..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6990,16 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (TARGET_POWER10 && vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26734,41 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28632,348 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_WORDS];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-
- /* Mark that this constant involes floating point. */
- vec_const->fp_constant_p = true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- if (!vec_const->all_double_words_same)
- return false;
-
- /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP.
- Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */
- if (vec_const->all_bytes_same
- || vec_const->all_half_words_same
- || vec_const->all_words_same)
- return false;
-
- unsigned HOST_WIDE_INT value = vec_const->double_words[0];
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and the signalling NaN bit pattern. Recognize infinity and
- negative infinity. */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (value != VECTOR_CONST_DF_NAN
- && value != VECTOR_CONST_DF_NANS
- && value != VECTOR_CONST_DF_INF
- && value != VECTOR_CONST_DF_NEG_INF)
- {
- /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for
- the exponent, and 52 bits for the mantissa (not counting the hidden
- bit used for normal numbers). NaN values have the exponent set to all
- 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */
-
- int df_exponent = (value >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->xxspltidp_immediate = sf_value;
-
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* Set up the vector bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- /* Scalars are treated as 64-bit integers. */
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_HALF_WORDS; i++)
- vec_const->half_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[(2 * i) + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_WORDS; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4 * i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_DOUBLE_WORDS; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8 * i) + j];
-
- vec_const->double_words[i] = d_word;
- }
-
- /* Determine if the double words, words, half words, and bytes are all
- equal. */
- unsigned HOST_WIDE_INT first_dword = vec_const->double_words[0];
- vec_const->all_double_words_same = true;
- for (size_t i = 1; i < VECTOR_CONST_DOUBLE_WORDS; i++)
- if (first_dword != vec_const->double_words[i])
- vec_const->all_double_words_same = false;
-
- unsigned int first_word = vec_const->words[0];
- vec_const->all_words_same = true;
- for (size_t i = 1; i < VECTOR_CONST_WORDS; i++)
- if (first_word != vec_const->words[i])
- vec_const->all_words_same = false;
-
- unsigned short first_hword = vec_const->half_words[0];
- vec_const->all_half_words_same = true;
- for (size_t i = 1; i < VECTOR_CONST_HALF_WORDS; i++)
- if (first_hword != vec_const->half_words[i])
- vec_const->all_half_words_same = false;
-
- unsigned char first_byte = vec_const->bytes[0];
- vec_const->all_bytes_same = true;
- for (size_t i = 1; i < VECTOR_CONST_BYTES; i++)
- if (first_byte != vec_const->bytes[i])
- vec_const->all_bytes_same = false;
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b0ead908fe9..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -156,7 +156,6 @@
UNSPEC_PEXTD
UNSPEC_HASHST
UNSPEC_HASHCHK
- UNSPEC_VSX_PREFIXED_CONST
])
;;
@@ -315,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7765,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eP"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7797,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8066,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eP"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8094,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8135,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eP"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8169,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -8215,43 +8206,6 @@
(set_attr "length"
"*, *, *, *, *, 8,
12, 16, *")])
-
-;; Split the VSX prefixed instruction to support SFmode and DFmode scalar
-;; constants that look like DFmode floating point values where both elements
-;; are the same. The constant has to be expressible as a SFmode constant that
-;; is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_insn "*xxspltidp_<mode>_internal"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_VSX_PREFIXED_CONST))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:SFDF 0 "vsx_register_operand")
- (match_operand:SFDF 1 "vsx_prefixed_constant"))]
- "TARGET_POWER10"
- [(set (match_dup 0)
- (unspec:SFDF [(match_dup 2)] UNSPEC_VSX_PREFIXED_CONST))]
-{
- rtx src = operands[1];
- rs6000_vec_const vec_const;
-
- if (!vec_const_to_bytes (src, <MODE>mode, &vec_const))
- gcc_unreachable ();
-
- if (vec_const_use_xxspltidp (&vec_const))
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
-
- else
- gcc_unreachable ();
-})
-
\f
(define_expand "mov<mode>"
[(set (match_operand:FMOVE128 0 "general_operand")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 1d7ce4cc94a..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,10 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c8518496339..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTIDP
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eP,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTIDP
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eP,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 13b56279565..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3336,10 +3336,6 @@ A constant whose negation is a signed 16-bit constant.
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eP
-A scalar floating point constant or a vector constant that can be
-loaded with one prefixed instruction to a VSX register.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 5f84930e1a7..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -150,7 +150,7 @@ main (int argc, char *argv [])
}
/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-18 14:07 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-18 14:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9a6ff130fbda39593fc2bf1db46a37207142cd0b
commit 9a6ff130fbda39593fc2bf1db46a37207142cd0b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Oct 18 10:06:25 2021 -0400
Revert patches.
2021-10-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_prefixed): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add field for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_simple_constant): New function.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eS): New constraint.
(eV): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(easy_scalar_constant_prefixed): New predicate.
(easy_vector_constant_prefixed): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for
insns that generate XXSPLTIDP.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal): New insn.
(XXSPLTIDP splitters): New splitters for XXSPLTIDP.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
Diff:
---
gcc/config/rs6000/constraints.md | 17 -
gcc/config/rs6000/predicates.md | 98 ----
gcc/config/rs6000/rs6000-protos.h | 26 -
gcc/config/rs6000/rs6000.c | 534 +--------------------
gcc/config/rs6000/rs6000.md | 58 +--
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 73 +--
gcc/doc/md.texi | 11 -
.../gcc.target/powerpc/float128-constant.c | 160 ------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ---
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ---
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 --
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 --
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---
.../gcc.target/powerpc/vec-splati-runnable.c | 4 +-
20 files changed, 36 insertions(+), 1477 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index e645f405588..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,23 +213,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; A scalar constant that can be loaded into vector registers with one prefixed
-;; instruction such as XXSPLTIDP.
-(define_constraint "eS"
- "A scalar constant that can be loaded with one prefixed instruction."
- (match_operand 0 "vsx_prefixed_scalar_constant"))
-
-;; A vector constant that can be loaded into vector registers with one prefixed
-;; instruction such as XXSPLTIDP
-(define_constraint "eV"
- "A vector constant that can be loaded with one prefixed instruction."
- (match_operand 0 "vsx_prefixed_vector_constant"))
-
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 252abbbaf9a..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,21 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -624,73 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with one prefixed instruction, such as XXSPLTIDP.
-
-(define_predicate "vsx_prefixed_scalar_constant"
- (match_code "const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- return false;
-})
-
-;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with one prefixed instruction, such as XXSPLTIDP or XXSPLTIW.
-;;
-;; We have to have separate predicates and constraints for scalars and vectors,
-;; otherwise things get messed up with TImode when you try to load very large
-;; integer constants.
-
-(define_predicate "vsx_prefixed_vector_constant"
- (match_code "const_vector,vec_duplicate")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- return false;
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_FLOAT128_HW || !TARGET_POWER10 || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_lxvkq (&vec_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -739,22 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 52f094dd410..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,31 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_16BIT (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_32BIT (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_64BIT (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned HOST_WIDE_INT d_words[VECTOR_CONST_64BIT];
- unsigned int words[VECTOR_CONST_32BIT];
- unsigned short h_words[VECTOR_CONST_16BIT];
- unsigned char bytes[VECTOR_CONST_BYTES];
- machine_mode orig_mode; /* Original mode. */
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
- unsigned int lxvkq_immediate; /* Immediate to use with LXVKQ. */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 838161fb23a..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6925,17 +6925,12 @@ xxspltib_constant_p (rtx op,
else
return false;
- /* See if we could generate vspltisw/vspltish/xxspltiw directly instead of
- xxspltib + sign extend. Special case 0/-1 to allow getting any VSX
- register instead of an Altivec register. */
- if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0))
- {
- if (EASY_VECTOR_15 (value))
- return false;
-
- if (TARGET_XXSPLTIW && TARGET_PREFIXED && TARGET_VSX)
- return false;
- }
+ /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
+ sign extend. Special case 0/-1 to allow getting any VSX register instead
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
+ return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
if (mode == V16QImode)
@@ -6995,68 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (TARGET_POWER10 && vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- HOST_WIDE_INT imm = vec_const.xxspltiw_immediate;
-
- /* See if we can generate the shorter VSPLTISB, VSPLTISH, or
- VSPLTISW instead of XXSPLTIW. */
- if (dest_vmx_p)
- {
- HOST_WIDE_INT sign_imm
- = ((imm & 0xffffffff) ^ 0x80000000) - 0x80000000;
-
- if (EASY_VECTOR_15 (sign_imm))
- {
- operands[2] = GEN_INT (sign_imm);
- return "vspltisw %0,%2";
- }
-
- if (vec_const.bytes[0] == vec_const.bytes[1]
- && vec_const.bytes[0] == vec_const.bytes[2]
- && vec_const.bytes[0] == vec_const.bytes[3])
- {
- HOST_WIDE_INT sign_imm8 = ((imm & 0xff) ^ 0x80) - 0x80;
- if (EASY_VECTOR_15 (sign_imm8))
- {
- operands[2] = GEN_INT (sign_imm8);
- return "vspltisb %0,%2";
- }
- }
-
- if (vec_const.h_words[0] == vec_const.h_words[1])
- {
- HOST_WIDE_INT sign_imm16
- = ((imm & 0xffff) ^ 0x8000) - 0x8000;
-
- if (EASY_VECTOR_15 (sign_imm16))
- {
- operands[2] = GEN_INT (sign_imm16);
- return "vspltish %0,%2";
- }
- }
- }
-
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26791,44 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28692,423 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_32BIT];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- unsigned HOST_WIDE_INT df_upper = vec_const->d_words[0];
- unsigned HOST_WIDE_INT df_lower = vec_const->d_words[1];
- if (df_upper != df_lower)
- return false;
-
- /* Avoid 0 since that is easy to generate without using XXSPLTIDP. */
- if (df_upper == 0)
- return false;
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and signalling NaN bit pattern. Recognize infinity and negative
- infinity.
-
- The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for the
- exponent, and 52 bits for the mantissa (not counting the hidden bit used
- for normal numbers). NaN values have the exponent set to all 1 bits, and
- the mantissa non-zero (mantissa == 0 is infinity). */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (df_upper != VECTOR_CONST_DF_NAN
- && df_upper != VECTOR_CONST_DF_NANS
- && df_upper != VECTOR_CONST_DF_INF
- && df_upper != VECTOR_CONST_DF_NEG_INF)
- {
- int df_exponent = (df_upper >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = df_upper & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->xxspltidp_immediate = sf_value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with VSPLTISW, VSPLTISH,
- VSPLTISB, or XXSPLTISB. */
- if (value == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = SImode;
-
- if (!FLOAT_MODE_P (mode))
- {
- /* Can we use VSPLTISW to load the constant? */
- int sign_value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_value))
- return false;
-
- /* Can we use VSPLTISH to load the constant? */
- if (vec_const->h_words[0] == vec_const->h_words[1])
- {
- int sign_value16 = ((value & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_value16))
- return false;
- }
-
- /* Can we use XXSPLTISB/VSPLTISB to load the constant? */
- if (vec_const->bytes[0] == vec_const->bytes[1]
- && vec_const->bytes[0] == vec_const->bytes[2]
- && vec_const->bytes[0] == vec_const->bytes[3])
- return false;
- }
-
- /* Record the immediate in the vec_const structure for XXSPLTIW. */
- vec_const->xxspltiw_immediate = value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_32BIT; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction, record the immediate needed for the
- instruction. */
- vec_const->lxvkq_immediate = immediate;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* Set up the vector bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- /* Scalars are treated as 64-bit integers. */
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_16BIT; i++)
- vec_const->h_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[2*i + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_32BIT; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4*i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_64BIT; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8*i) + j];
-
- vec_const->d_words[i] = d_word;
- }
-
- /* Remember original mode that the vector/scalar used. */
- vec_const->orig_mode = mode;
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 79ea4a82b4f..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eS"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eS"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eS"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eS,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eS,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 015bf91b6d5..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,18 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 07b0b671920..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eV, eQ,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa, wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eV, eQ,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *, *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10, p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -6478,47 +6458,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and vector constants that look like DFmode floating point
-;; values where both elements are the same. The constant has to be expressible
-;; as a SFmode constant that is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_mode_iterator XXSPLTIDP [DI SF DF])
-
-(define_insn "xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (match_operand:XXSPLTIDP 1 "vsx_prefixed_scalar_constant"))]
- "TARGET_POWER10"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
- rs6000_vec_const vec_const;
-
- if (!vec_const_to_bytes (src, <MODE>mode, &vec_const))
- gcc_unreachable ();
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- rtx imm = GEN_INT (vec_const.xxspltidp_immediate);
- emit_insn (gen_xxspltidp_<mode>_internal (dest, imm));
- DONE;
- }
-
- gcc_unreachable ();
-})
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 0e87ad1f200..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3336,17 +3336,6 @@ A constant whose negation is a signed 16-bit constant.
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eS
-A scalar constant that can be loaded with one prefixed instruction to
-a VSX register.
-
-@item eV
-A vector constant that can be loaded with one prefixed instruction to
-a VSX register.
-
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index f6becac1075..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..a135279b1d7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,8 +149,8 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-15 23:44 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-15 23:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ad4f1acb7a60bf0b36beea7b996871f130adc4c7
commit ad4f1acb7a60bf0b36beea7b996871f130adc4c7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 15 19:43:43 2021 -0400
Revert patches.
2021-10-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraint.md (eJ): New constraint.
(eK): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(vsx_prefixed_scalar_constant_2insn): New predicate.
(vsx_prefixed_vector_constant_2insn): New predicate.
(vsx_prefixed_constant_2insn): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add
xxsplti32dx fields.
(vec_const_use_xxsplti32dx): New declaration.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating XXSPLTI32DX. Also support generating XXSPLTISB instead
of VSPLTISB for XXSPLTIW.
(vec_const_simple_constant): New function, split from
vec_const_use_xxspltiw.
(vec_const_use_xxspltiw): Move some code to
vec_const_simple_constant.
(prefixed_xxsplti_p): Constants loaded with XXSPLTI32DX are
prefixed.
(vec_const_use_xxsplti32dx): New function.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New debug option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(vsx_mov<mode>_64bit): Add support for constants loaded with
XXSPLTI32DX.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTI32DX): New mode iterator.
(splitter for XXSPLTI32DX): Add splitter for constants loaded with
XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insns.
(xxsplti32dx_<mode>_second): New insns.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eJ and eK constraints.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-di-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test.
2021-10-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_prefixed): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add field for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/constraints.md | 12 --
gcc/config/rs6000/predicates.md | 85 +---------
gcc/config/rs6000/rs6000-protos.h | 5 -
gcc/config/rs6000/rs6000.c | 176 +--------------------
gcc/config/rs6000/rs6000.md | 123 ++++----------
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 111 ++-----------
gcc/doc/md.texi | 8 -
.../gcc.target/powerpc/vec-splat-constant-df-2.c | 24 ---
.../gcc.target/powerpc/vec-splat-constant-di-2.c | 38 -----
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ----
.../gcc.target/powerpc/vec-splat-constant-v2df-2.c | 24 ---
.../gcc.target/powerpc/vec-splat-constant-v2di-2.c | 29 ----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 --------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 --------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
17 files changed, 52 insertions(+), 800 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index cd10824edb9..e645f405588 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,18 +213,6 @@
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; A scalar constant that can be loaded into vector registers with two prefixed
-;; instructions such as XXSPLTI32DX.
-(define_constraint "eJ"
- "A scalar constant that can be loaded with two prefixed instructions."
- (match_operand 0 "vsx_prefixed_scalar_constant_2insn"))
-
-;; A vector constant that can be loaded into vector registers with two prefixed
-;; instructions such as XXSPLTI32DX.
-(define_constraint "eK"
- "A scalar constant that can be loaded with two prefixed instructions."
- (match_operand 0 "vsx_prefixed_vector_constant_2insn"))
-
;; A scalar constant that can be loaded into vector registers with one prefixed
;; instruction such as XXSPLTIDP.
(define_constraint "eS"
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index cdb8c25517d..517ce08f03d 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,12 +611,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -650,29 +644,7 @@
})
;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with two prefixed instructions, such as XXSPLTI32DX.
-
-(define_predicate "vsx_prefixed_scalar_constant_2insn"
- (match_code "const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return true;
-
- return false;
-})
-
-;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with one prefixed instruction, such as XXSPLTIDP or XXSPLTIW.
+;; register with one prefixed instruction, such as XXSPLTIDP.
;;
;; We have to have separate predicates and constraints for scalars and vectors,
;; otherwise things get messed up with TImode when you try to load very large
@@ -694,55 +666,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- return false;
-})
-
-;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with two prefixed instructions, such as XXSPLTI32DX.
-;;
-;; We have to have separate predicates and constraints for scalars and vectors,
-;; otherwise things get messed up with TImode when you try to load very large
-;; integer constants.
-
-(define_predicate "vsx_prefixed_vector_constant_2insn"
- (match_code "const_vector,vec_duplicate")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return true;
-
- return false;
- })
-
-;; Combination of the two prefixed vector constant predicates.
-(define_predicate "vsx_prefixed_constant_2insn"
- (match_code "const_int,const_double,const_vector,vec_duplicate")
-{
- rs6000_vec_const vec_const;
-
- /* Do we have prefixed instructions and VSX registers available? Is the
- constant recognized? */
- if (!TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return true;
-
return false;
})
@@ -821,12 +744,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return true;
}
return easy_altivec_constant (op, mode);
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 36666c9f2d6..6e8b81cb134 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -240,16 +240,11 @@ typedef struct {
unsigned char bytes[VECTOR_CONST_BYTES];
machine_mode orig_mode; /* Original mode. */
unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
unsigned int lxvkq_immediate; /* Immediate to use with LXVKQ. */
- unsigned int xxsplti32dx_upper; /* Upper value for XXSPLTI32DX. */
- unsigned int xxsplti32dx_lower; /* Lower value for XXSPLTI32DX. */
} rs6000_vec_const;
extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxsplti32dx (rs6000_vec_const *);
extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 332ca3ca400..d238dd84fe7 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6925,17 +6925,12 @@ xxspltib_constant_p (rtx op,
else
return false;
- /* See if we could generate vspltisw/vspltish/xxspltiw directly instead of
- xxspltib + sign extend. Special case 0/-1 to allow getting any VSX
- register instead of an Altivec register. */
- if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0))
- {
- if (EASY_VECTOR_15 (value))
- return false;
-
- if (TARGET_XXSPLTIW && TARGET_PREFIXED && TARGET_VSX)
- return false;
- }
+ /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
+ sign extend. Special case 0/-1 to allow getting any VSX register instead
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
+ return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
if (mode == V16QImode)
@@ -7009,53 +7004,6 @@ output_vec_const_move (rtx *operands)
operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
return "xxspltidp %x0,%2";
}
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- HOST_WIDE_INT imm = vec_const.xxspltiw_immediate;
-
- /* See if we can generate the shorter XXSPLTIB, VSPLTISH, or
- VSPLTISW instead of XXSPLTIW. In theory, the alternatives
- should take care of this, but just in case, handle it
- here. */
- if (vec_const.bytes[0] == vec_const.bytes[1]
- && vec_const.bytes[0] == vec_const.bytes[2]
- && vec_const.bytes[0] == vec_const.bytes[3])
- {
- operands[2] = GEN_INT (imm & 0xff);
- return "xxspltib %x0,%2";
- }
-
- else if (dest_vmx_p)
- {
- HOST_WIDE_INT sign_imm
- = ((imm & 0xffffffff) ^ 0x80000000) - 0x80000000;
-
- if (EASY_VECTOR_15 (sign_imm))
- {
- operands[2] = GEN_INT (sign_imm);
- return "vspltisw %0,%2";
- }
-
- if (vec_const.h_words[0] == vec_const.h_words[1])
- {
- HOST_WIDE_INT sign_imm16
- = ((imm & 0xffff) ^ 0x8000) - 0x8000;
-
- if (EASY_VECTOR_15 (sign_imm16))
- {
- operands[2] = GEN_INT (sign_imm16);
- return "vspltish %0,%2";
- }
- }
- }
-
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return "#";
}
if (TARGET_P9_VECTOR
@@ -26822,12 +26770,6 @@ prefixed_xxsplti_p (rtx_insn *insn)
{
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- if (vec_const_use_xxsplti32dx (&vec_const))
- return true;
}
return false;
@@ -28842,112 +28784,6 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
return true;
}
-/* Internal function to return true if a particular vector constant is simple
- to generate without using prefixed instructions. */
-
-static bool
-vec_const_simple_constant (rs6000_vec_const *vec_const,
- machine_mode default_int_mode)
-{
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Return true for values that are easy to create with other instructions
- (0.0 for floating point, and values that can be loaded with VSPLTISW,
- VSPLTISH, VSPLTISB, or XXSPLTISB. */
- if (value == 0)
- return true;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = default_int_mode;
-
- if (!FLOAT_MODE_P (mode))
- {
- /* Can we use VSPLTISW to load the constant? */
- int sign_value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_value))
- return true;
-
- /* Can we use VSPLTISH to load the constant? */
- if (vec_const->h_words[0] == vec_const->h_words[1])
- {
- int sign_value16 = ((value & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_value16))
- return true;
- }
-
- /* Can we use XXSPLTISB/VSPLTISB to load the constant? */
- if (vec_const->bytes[0] == vec_const->bytes[1]
- && vec_const->bytes[0] == vec_const->bytes[2]
- && vec_const->bytes[0] == vec_const->bytes[3])
- return true;
- }
-
- return false;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Do not use XXSPLTIW for values that are easy to create with other
- instructions (0.0 for floating point, and values that can be loaded with
- VSPLTISW, VSPLTISH, VSPLTISB, or XXSPLTISB. */
- if (vec_const_simple_constant (vec_const, SImode))
- return false;
-
- /* Record the immediate in the vec_const structure for XXSPLTIW. */
- vec_const->xxspltiw_immediate = value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with 2 XXSPLTI32DX
- instructions. If so, fill out the fields used to generate the
- instruction. */
-
-bool
-vec_const_use_xxsplti32dx (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTI32DX || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 2 64-bit segments are the same. */
- if (vec_const->d_words[0] != vec_const->d_words[1])
- return false;
-
- /* Do not use XXSPLTI32DX for values that can be created with simple
- non-prefixed instructions, or created by the other vector constant
- instructions (XXSPLTIDP, XXSPLTIW, or LXVKQ). */
- if (vec_const_simple_constant (vec_const, DImode)
- || vec_const_use_xxspltidp (vec_const)
- || vec_const_use_xxspltiw (vec_const)
- || vec_const_use_lxvkq (vec_const))
- return false;
-
- vec_const->xxsplti32dx_upper = vec_const->words[0];
- vec_const->xxsplti32dx_lower = vec_const->words[1];
-
- return true;
-}
-
/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
the fields used to generate the instruction. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8a19a9c2208..79ea4a82b4f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7764,17 +7764,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eS, eJ"))]
+ r, r, *h, 0, eS"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7797,24 +7797,15 @@
mt%0 %1
mf%1 %0
nop
- #
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *, p10")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8074,18 +8065,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR XXSPLTIDP
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eS, eJ"))]
+ r, Y, r, eS"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8103,29 +8094,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two, vecperm")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
+ 8, 8, 8, *")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "isa"
- "*, *, *, p9v, p9v,
- p7v, p7v, *, *, *,
- *, *, *, p10, p10")])
+ *, *, *, p10")])
;; STW LWZ MR G-const H-const F-const
@@ -8152,19 +8134,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eS, eJ"))]
+ 0, <f64_dm>, r, eS"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8187,29 +8169,18 @@
nop
mfvsrd %0,%x1
mtvsrd %x0,%1
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, p8v, p8v, p10")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9257,7 +9228,7 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP XXSPLTI32DX
+;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9265,13 +9236,13 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa, ^wa,
+ ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eS, eJ,
+ eS,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9287,7 +9258,6 @@
fmr %0,%1
#
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9302,35 +9272,23 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm, vecperm,
+ vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *, *,
+ *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10, p10,
+ p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
- p7v")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, 2,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, 2,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *")])
+ p7v")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand")
@@ -9363,7 +9321,7 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP XXSPLTI32DX
+;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9374,7 +9332,7 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa, ^wa,
+ ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9384,7 +9342,7 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eS, eJ,
+ eS,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9404,7 +9362,6 @@
lis %0,%v1
li %0,%1
#
- #
stfd%U0%X0 %1,%0
lfd%U1%X1 %0,%1
fmr %0,%1
@@ -9427,7 +9384,7 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm, vecperm,
+ vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9438,7 +9395,7 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *, *,
+ *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9448,34 +9405,14 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10, p10,
+ p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *,
p7v, p7v,
*, *, *,
- p8v, p8v")
- (set_attr "num_insns"
- "*, *, *,
- *, 2,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- 8, *,
- *, *, *,
- *, *")
- (set_attr "max_prefixed_insns"
- "*, *, *,
- *, 2,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- 8, *,
- *, *, *,
- *, *")])
+ p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
; instruction.
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 25c56238861..c9eb78952d6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,18 +640,10 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxsplti32dx
-Target Undocumented Var(TARGET_XXSPLTI32DX) Init(1) Save
-Generate (do not generate) XXSPLTI32DX instructions.
-
mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 5058addd9ae..15a22525000 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -376,7 +376,6 @@
UNSPEC_XXSPLTIW
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1193,19 +1192,19 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ XXSPLTI32DX
+;; XXLSPLTIDP LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa, wa,
+ wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eV, eQ, eK,
+ eV, eQ,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1217,46 +1216,46 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm, vecperm,
+ vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *, 2,
+ *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, 2,
+ *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *, *,
+ *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10, p10,
+ p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ XXSPLTI32DX
+;; XXSPLTIDP LXVKQ
;; VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa,
- wa, wa, wa,
+ wa, wa,
v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM,
- eV, eQ, eK,
+ eV, eQ,
W, <nW>,
v, wZ"))]
@@ -1269,26 +1268,20 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple,
- vecperm, vecperm, vecperm,
+ vecperm, vecperm,
*, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *,
- *, *, *,
+ *, *,
20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>,
- p10, p10, p10,
+ p10, p10,
*, *,
- *, *")
- (set_attr "num_insns"
- "*, *, *, 4, 4, 4,
- *, *, *,
- *, *, 2,
- 5, 4,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -6586,82 +6579,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [DI SF DF V16QI V8HI V4SI V4SF V2DI V2DF])
-
-;; Don't split DImode before register allocation, so that it has a better
-;; chance of winding up in a GPR register.
-(define_split
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand")
- (match_operand:XXSPLTI32DX 1 "vsx_prefixed_constant_2insn"))]
- "TARGET_POWER10 && (reload_completed || <MODE>mode != DImode)"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- HOST_WIDE_INT high;
- HOST_WIDE_INT low;
- rs6000_vec_const vec_const;
-
- if (!vec_const_to_bytes (operands[1], <MODE>mode, &vec_const))
- gcc_unreachable ();
-
- if (!vec_const_use_xxsplti32dx (&vec_const))
- gcc_unreachable ();
-
- high = vec_const.xxsplti32dx_upper;
- low = vec_const.xxsplti32dx_lower;
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB/XXLXOR/XXLORC instruction instead of the first
- XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-})
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxlxor %x0,%x0,%x0
- xxlorc %x0,%x0,%x0
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "veclogical,veclogical,vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
;; XXBLEND built-in function support
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 794c5de9516..0e87ad1f200 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3336,14 +3336,6 @@ A constant whose negation is a signed 16-bit constant.
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eJ
-A scalar constant that can be loaded with two prefixed instructions to
-a VSX register.
-
-@item eK
-A vector constant that can be loaded with two prefixed instructions to
-a VSX register.
-
@item eS
A scalar constant that can be loaded with one prefixed instruction to
a VSX register.
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c
deleted file mode 100644
index 3b4b4e01d1b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-#define M_PI 3.14159265358979323846
-#define SUBNORMAL 0x1p-149f
-
-/* Test generation of floating point constants with XXSPLTI32DX. */
-
-double
-df_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-/* This float subnormal cannot be loaded with XXSPLTIDP. */
-
-double
-v2df_double_denorm (void)
-{
- return SUBNORMAL; /* XXLXOR, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c
deleted file mode 100644
index 30ad33388e8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-/* Test generation of integer constants loaded into the vector registers with
- the ISA 3.1 (power10) instruction XXSPLTI32DX. We use asm to force the
- value into vector registers. */
-
-#define LARGE_BITS 0x12345678ABCDEF01LL
-#define SUBNORMAL 0x8000000000000001LL
-
-/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can
- be generated with XXSPLTI32DX but not XXSLTIDP. */
-double
-scalar_float_subnormal (void)
-{
- /* 2x XXSPLTI32DX. */
- double d;
- long long ll = SUBNORMAL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x
- XXSPLTI32DX instructions. */
-double
-scalar_large_constant (void)
-{
- /* 2x XXSPLTI32DX. */
- double d;
- long long ll = LARGE_BITS;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c
deleted file mode 100644
index 8bc119ad41f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-#define M_PI 3.14159265358979323846
-#define SUBNORMAL 0x1p-149f
-
-/* Test generation of floating point constants with XXSPLTI32DX. */
-
-vector double
-v2df_double_pi (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector double) { M_PI, M_PI };
-}
-
-vector double
-v2df_double_denorm (void)
-{
- /* XXLXOR, XXSPLTI32DX. */
- return (vector double) { SUBNORMAL, SUBNORMAL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c
deleted file mode 100644
index 2730742752a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-/* Test generation of integer constants loaded into the vector registers with
- the ISA 3.1 (power10) instruction XXSPLTI32DX. */
-
-#define LARGE_BITS 0x12345678ABCDEF01LL
-#define SUBNORMAL 0x8000000000000001LL
-
-/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can
- be generated with XXSPLTI32DX but not XXSLTIDP. */
-vector long long
-vector_float_subnormal (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector long long) { SUBNORMAL, SUBNORMAL };
-}
-
-/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x
- XXSPLTI32DX instructions. */
-vector long long
-vector_large_constant (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector long long) { LARGE_BITS, LARGE_BITS };
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..5f84930e1a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,7 +149,7 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-15 15:12 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-15 15:12 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:640a067ba6bf93576f4e6ddddbafa7ba56dcf2f9
commit 640a067ba6bf93576f4e6ddddbafa7ba56dcf2f9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Oct 15 11:12:19 2021 -0400
Revert patches.
2021-10-15 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_prefixed): Likewise.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add field for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment.
(vsx_mov<mode>_32bit): Likewise.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/vec-splati-runnable.c: Update insn count.
Diff:
---
gcc/config/rs6000/predicates.md | 11 +-
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 119 ++-------------------
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 4 +-
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 -----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ------------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -----------
.../gcc.target/powerpc/vec-splati-runnable.c | 2 +-
10 files changed, 10 insertions(+), 339 deletions(-)
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 252abbbaf9a..517ce08f03d 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,9 +611,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -647,7 +644,7 @@
})
;; Return 1 if the operand is a scalar constant that can be loaded to a VSX
-;; register with one prefixed instruction, such as XXSPLTIDP or XXSPLTIW.
+;; register with one prefixed instruction, such as XXSPLTIDP.
;;
;; We have to have separate predicates and constraints for scalars and vectors,
;; otherwise things get messed up with TImode when you try to load very large
@@ -669,9 +666,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
return false;
})
@@ -750,9 +744,6 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
return easy_altivec_constant (op, mode);
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 52f094dd410..6e8b81cb134 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -240,13 +240,11 @@ typedef struct {
unsigned char bytes[VECTOR_CONST_BYTES];
machine_mode orig_mode; /* Original mode. */
unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
unsigned int lxvkq_immediate; /* Immediate to use with LXVKQ. */
} rs6000_vec_const;
extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4400e344787..d238dd84fe7 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6925,17 +6925,12 @@ xxspltib_constant_p (rtx op,
else
return false;
- /* See if we could generate vspltisw/vspltish/xxspltiw directly instead of
- xxspltib + sign extend. Special case 0/-1 to allow getting any VSX
- register instead of an Altivec register. */
- if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0))
- {
- if (EASY_VECTOR_15 (value))
- return false;
-
- if (TARGET_XXSPLTIW && TARGET_PREFIXED && TARGET_VSX)
- return false;
- }
+ /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
+ sign extend. Special case 0/-1 to allow getting any VSX register instead
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
+ return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
if (mode == V16QImode)
@@ -7009,52 +7004,6 @@ output_vec_const_move (rtx *operands)
operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
return "xxspltidp %x0,%2";
}
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- HOST_WIDE_INT imm = vec_const.xxspltiw_immediate;
-
- /* See if we can generate the shorter VSPLTISB, VSPLTISH, or
- VSPLTISW instead of XXSPLTIW. */
- if (dest_vmx_p)
- {
- HOST_WIDE_INT sign_imm
- = ((imm & 0xffffffff) ^ 0x80000000) - 0x80000000;
-
- if (EASY_VECTOR_15 (sign_imm))
- {
- operands[2] = GEN_INT (sign_imm);
- return "vspltisw %0,%2";
- }
-
- if (vec_const.bytes[0] == vec_const.bytes[1]
- && vec_const.bytes[0] == vec_const.bytes[2]
- && vec_const.bytes[0] == vec_const.bytes[3])
- {
- HOST_WIDE_INT sign_imm8 = ((imm & 0xff) ^ 0x80) - 0x80;
- if (EASY_VECTOR_15 (sign_imm8))
- {
- operands[2] = GEN_INT (sign_imm8);
- return "vspltisb %0,%2";
- }
- }
-
- if (vec_const.h_words[0] == vec_const.h_words[1])
- {
- HOST_WIDE_INT sign_imm16
- = ((imm & 0xffff) ^ 0x8000) - 0x8000;
-
- if (EASY_VECTOR_15 (sign_imm16))
- {
- operands[2] = GEN_INT (sign_imm16);
- return "vspltish %0,%2";
- }
- }
- }
-
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
}
if (TARGET_P9_VECTOR
@@ -26821,9 +26770,6 @@ prefixed_xxsplti_p (rtx_insn *insn)
{
if (vec_const_use_xxspltidp (&vec_const))
return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
}
return false;
@@ -28838,59 +28784,6 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
return true;
}
-/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with VSPLTIW.. */
- if (value == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = SImode;
-
- if (!FLOAT_MODE_P (mode))
- {
- /* Can we use VSPLTISW to load the constant? */
- int sign_value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_value))
- return false;
-
- /* Can we use XXSPLTISB to load the constant? */
- if (vec_const->bytes[0] == vec_const->bytes[1]
- && vec_const->bytes[0] == vec_const->bytes[2]
- && vec_const->bytes[0] == vec_const->bytes[3])
- return false;
-
- /* Can we use VSPLTISH to load the constant? */
- if (vec_const->h_words[0] == vec_const->h_words[1])
- {
- int sign_value16 = ((value & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_value16))
- return false;
- }
- }
-
- /* Record the immediate in the vec_const structure for XXSPLTIW. */
- vec_const->xxspltiw_immediate = value;
-
- return true;
-}
-
/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
the fields used to generate the instruction. */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 015bf91b6d5..c9eb78952d6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,10 +644,6 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 07b0b671920..15a22525000 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,7 +1192,7 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTI* LXVKQ
+;; XXLSPLTIDP LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
@@ -1241,7 +1241,7 @@
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTI* LXVKQ
+;; XXSPLTIDP LXVKQ
;; VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
index 6c01666b625..5f84930e1a7 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c
@@ -149,7 +149,7 @@ main (int argc, char *argv [])
return 0;
}
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */
/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-14 23:43 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-14 23:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7041d42e0374e0d95bc586a45a2700b2f5c64b27
commit 7041d42e0374e0d95bc586a45a2700b2f5c64b27
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 14 19:41:38 2021 -0400
Revert patches.
2021-10-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_32bit_element): New predicate.
(easy_vector_constant): Add support for XXSPLTIW.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add fields for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eW constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for
insns that generate XXSPLTIDP.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal): New insn.
(XXSPLTIDP splitters): New splitters for XXSPLTIDP.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 15 -
gcc/config/rs6000/predicates.md | 80 ---
gcc/config/rs6000/rs6000-protos.h | 26 -
gcc/config/rs6000/rs6000.c | 546 +--------------------
gcc/config/rs6000/rs6000.md | 58 +--
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 65 +--
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/float128-constant.c | 160 ------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ---
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 -
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ---
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 --
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 --
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---
19 files changed, 34 insertions(+), 1454 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d2a1c088995..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,26 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; A scalar or vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eD"
- "A constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
-;; A scalar or vector constant that can be loaded with the XXSPLTIW instruction.
-(define_constraint "eW"
- "A constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "easy_vector_constant_32bit_element"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2a2bdbe463a..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,21 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -624,55 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_xxspltidp (&vec_const));
-})
-
-;; Return 1 if the operand is a 32-bit vector constant that can be loaded via
-;; the XXSPLTIW instruction.
-
-(define_predicate "easy_vector_constant_32bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we do the XXSPLTIW instruction? */
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_xxspltiw (&vec_const));
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_FLOAT128_HW || !TARGET_POWER10 || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_lxvkq (&vec_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -721,22 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index db0ad716968..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,31 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_16BIT (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_32BIT (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_64BIT (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned HOST_WIDE_INT d_words[VECTOR_CONST_64BIT];
- unsigned int words[VECTOR_CONST_32BIT];
- unsigned short h_words[VECTOR_CONST_16BIT];
- unsigned char bytes[VECTOR_CONST_BYTES];
- machine_mode orig_mode; /* Original mode. */
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
- unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1bd3f7c9c52..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6925,17 +6925,12 @@ xxspltib_constant_p (rtx op,
else
return false;
- /* See if we could generate vspltisw/vspltish/xxspltiw directly instead of
- xxspltib + sign extend. Special case 0/-1 to allow getting any VSX
- register instead of an Altivec register. */
- if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0))
- {
- if (EASY_VECTOR_15 (value))
- return false;
-
- if (TARGET_XXSPLTIW && TARGET_PREFIXED && TARGET_VSX)
- return false;
- }
+ /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
+ sign extend. Special case 0/-1 to allow getting any VSX register instead
+ of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
+ && EASY_VECTOR_15 (value))
+ return false;
/* Return # of instructions and the constant byte for XXSPLTIB. */
if (mode == V16QImode)
@@ -6995,68 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (TARGET_POWER10 && vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- HOST_WIDE_INT imm = vec_const.xxspltiw_immediate;
-
- /* See if we can generate the shorter VSPLTISB, VSPLTISH, or
- VSPLTISW instead of XXSPLTIW. */
- if (dest_vmx_p)
- {
- HOST_WIDE_INT sign_imm
- = ((imm & 0xffffffff) ^ 0x80000000) - 0x80000000;
-
- if (EASY_VECTOR_15 (sign_imm))
- {
- operands[2] = GEN_INT (sign_imm);
- return "vspltisw %0,%2";
- }
-
- if (vec_const.bytes[0] == vec_const.bytes[1]
- && vec_const.bytes[0] == vec_const.bytes[2]
- && vec_const.bytes[0] == vec_const.bytes[3])
- {
- HOST_WIDE_INT sign_imm8 = ((imm & 0xff) ^ 0x80) - 0x80;
- if (EASY_VECTOR_15 (sign_imm8))
- {
- operands[2] = GEN_INT (sign_imm8);
- return "vspltisb %0,%2";
- }
- }
-
- if (vec_const.h_words[0] == vec_const.h_words[1])
- {
- HOST_WIDE_INT sign_imm16
- = ((imm & 0xffff) ^ 0x8000) - 0x8000;
-
- if (EASY_VECTOR_15 (sign_imm16))
- {
- operands[2] = GEN_INT (sign_imm16);
- return "vspltish %0,%2";
- }
- }
- }
-
- operands[2] = GEN_INT (imm);
- return "xxspltiw %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26791,44 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28692,435 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_32BIT];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- unsigned HOST_WIDE_INT df_upper = vec_const->d_words[0];
- unsigned HOST_WIDE_INT df_lower = vec_const->d_words[1];
- if (df_upper != df_lower)
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with XXSPLTIB and sign
- extension for integer. */
- if (df_upper == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = DImode;
-
- if (!FLOAT_MODE_P (mode) && IN_RANGE (df_upper, -128, 127))
- return false;
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and signalling NaN bit pattern. Recognize infinity and negative
- infinity.
-
- The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for the
- exponent, and 52 bits for the mantissa (not counting the hidden bit used
- for normal numbers). NaN values have the exponent set to all 1 bits, and
- the mantissa non-zero (mantissa == 0 is infinity). */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (df_upper != VECTOR_CONST_DF_NAN
- && df_upper != VECTOR_CONST_DF_NANS
- && df_upper != VECTOR_CONST_DF_INF
- && df_upper != VECTOR_CONST_DF_NEG_INF)
- {
- int df_exponent = (df_upper >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = df_upper & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->xxspltidp_immediate = sf_value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with VSPLTIW.. */
- if (value == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = SImode;
-
- if (!FLOAT_MODE_P (mode))
- {
- /* Can we use VSPLTISW to load the constant? */
- int sign_value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
- if (EASY_VECTOR_15 (sign_value))
- return false;
-
- /* Can we use VSPLTISB to load the constant? */
- if (vec_const->bytes[0] == vec_const->bytes[1]
- && vec_const->bytes[0] == vec_const->bytes[2]
- && vec_const->bytes[0] == vec_const->bytes[3])
- {
- int sign_value8 = ((value & 0xff) ^ 0x80) - 0x80;
- if (EASY_VECTOR_15 (sign_value8))
- return false;
- }
-
- /* Can we use VSPLTISH to load the constant? */
- if (vec_const->h_words[0] == vec_const->h_words[1])
- {
- int sign_value16 = ((value & 0xffff) ^ 0x8000) - 0x8000;
- if (EASY_VECTOR_15 (sign_value16))
- return false;
- }
- }
-
- /* Record the immediate in the vec_const structure for XXSPLTIW. */
- vec_const->xxspltiw_immediate = value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_32BIT; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction, record the immediate needed for the
- instruction. */
- vec_const->lxvkq_immediate = immediate;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* Set up the vector bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- /* Scalars are treated as 64-bit integers. */
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_16BIT; i++)
- vec_const->h_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[2*i + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_32BIT; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4*i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_64BIT; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8*i) + j];
-
- vec_const->d_words[i] = d_word;
- }
-
- /* Remember original mode that the vector/scalar used. */
- vec_const->orig_mode = mode;
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cf42b6d2058..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eD,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eD,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 015bf91b6d5..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,18 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0d0609b5d0b..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTIDP LXVKQ XXSPLTIW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eD, eQ, eW,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTIDP LXVKQ XXSPLTIW
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa, wa, wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eD, eQ, eW,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm, vecperm, vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *, *, *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10, p10, p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -6478,39 +6458,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and vector constants that look like DFmode floating point
-;; values where both elements are the same. The constant has to be expressible
-;; as a SFmode constant that is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_mode_iterator XXSPLTIDP [DI SF DF])
-
-(define_insn "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (match_operand:XXSPLTIDP 1 "easy_vector_constant_64bit_element"))]
- "TARGET_POWER10"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- rs6000_vec_const vec_const;
- if (!vec_const_to_bytes (operands[1], <MODE>mode, &vec_const)
- || !vec_const_use_xxspltidp (&vec_const))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
-})
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 501e0069ebb..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,15 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index f6becac1075..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-14 16:47 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-14 16:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:74e8ff97ee30c844ed326994dd9d763c4cab639b
commit 74e8ff97ee30c844ed326994dd9d763c4cab639b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 14 12:46:57 2021 -0400
Revert patches.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for
insns that generate XXSPLTIDP.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal): New insn.
(XXSPLTIDP splitters): New splitters for XXSPLTIDP.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 -
gcc/config/rs6000/predicates.md | 58 ---
gcc/config/rs6000/rs6000-protos.h | 24 --
gcc/config/rs6000/rs6000.c | 423 ---------------------
gcc/config/rs6000/rs6000.md | 58 +--
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 65 +---
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/float128-constant.c | 160 --------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ----
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---
15 files changed, 28 insertions(+), 1097 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index a15b659d9d7..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,21 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; A scalar or vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eD"
- "A constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index de191fff08a..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,18 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -621,39 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_xxspltidp (&vec_const));
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_FLOAT128_HW || !TARGET_POWER10 || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_lxvkq (&vec_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -702,19 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 43c0f96aab5..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,29 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_16BIT (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_32BIT (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_64BIT (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned HOST_WIDE_INT d_words[VECTOR_CONST_64BIT];
- unsigned int words[VECTOR_CONST_32BIT];
- unsigned short h_words[VECTOR_CONST_16BIT];
- unsigned char bytes[VECTOR_CONST_BYTES];
- machine_mode orig_mode; /* Original mode. */
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 359379348bb..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6990,22 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (TARGET_POWER10 && vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26740,41 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28638,378 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_32BIT];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- unsigned HOST_WIDE_INT df_upper = vec_const->d_words[0];
- unsigned HOST_WIDE_INT df_lower = vec_const->d_words[1];
- if (df_upper != df_lower)
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with XXSPLTIB and sign
- extension for integer. */
- if (df_upper == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = DImode;
-
- if (!FLOAT_MODE_P (mode) && IN_RANGE (df_upper, -128, 127))
- return false;
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and signalling NaN bit pattern. Recognize infinity and negative
- infinity.
-
- The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for the
- exponent, and 52 bits for the mantissa (not counting the hidden bit used
- for normal numbers). NaN values have the exponent set to all 1 bits, and
- the mantissa non-zero (mantissa == 0 is infinity). */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (df_upper != VECTOR_CONST_DF_NAN
- && df_upper != VECTOR_CONST_DF_NANS
- && df_upper != VECTOR_CONST_DF_INF
- && df_upper != VECTOR_CONST_DF_NEG_INF)
- {
- int df_exponent = (df_upper >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = df_upper & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->xxspltidp_immediate = sf_value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_32BIT; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction, record the immediate needed for the
- instruction. */
- vec_const->lxvkq_immediate = immediate;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* Set up the vector bits. */
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- /* Scalars are treated as 64-bit integers. */
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* Fail if the floating point constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- /* SFmode stored as scalars are stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. */
- case CONST_VECTOR:
- {
- /* Fail if the vector constant is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Treat VEC_DUPLICATE of a constant just like a vector constant. */
- case VEC_DUPLICATE:
- {
- /* Fail if the vector duplicate is the wrong mode. */
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- else if (GET_MODE (op) != mode)
- return false;
-
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
- rtx ele = XEXP (op, 0);
-
- if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele))
- return false;
-
- for (size_t num = 0; num < nunits; num++)
- {
- size_t byte_num = num * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_16BIT; i++)
- vec_const->h_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[2*i + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_32BIT; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4*i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_64BIT; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8*i) + j];
-
- vec_const->d_words[i] = d_word;
- }
-
- /* Remember original mode that the vector/scalar used. */
- vec_const->orig_mode = mode;
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cf42b6d2058..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eD,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eD,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c9eb78952d6..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,14 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b36bbcd2b4e..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTIDP LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eD, eQ,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTIDP LXVKQ
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa, wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eD, eQ,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *, *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10, p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -6478,39 +6458,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and vector constants that look like DFmode floating point
-;; values where both elements are the same. The constant has to be expressible
-;; as a SFmode constant that is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_mode_iterator XXSPLTIDP [DI SF DF])
-
-(define_insn "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (match_operand:XXSPLTIDP 1 "easy_vector_constant_64bit_element"))]
- "TARGET_POWER10"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- rs6000_vec_const vec_const;
- if (!vec_const_to_bytes (operands[1], <MODE>mode, &vec_const)
- || !vec_const_use_xxspltidp (&vec_const))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
-})
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 501e0069ebb..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,15 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index f6becac1075..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-14 15:35 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-14 15:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8426d482b7af47a4ea7e1c4af5ada7fbd2c16f26
commit 8426d482b7af47a4ea7e1c4af5ada7fbd2c16f26
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 14 11:34:16 2021 -0400
Revert patches.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-14 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for
insns that generate XXSPLTIDP.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal): New insn.
(XXSPLTIDP splitters): New splitters for XXSPLTIDP.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 -
gcc/config/rs6000/predicates.md | 59 ----
gcc/config/rs6000/rs6000-protos.h | 24 --
gcc/config/rs6000/rs6000.c | 382 ---------------------
gcc/config/rs6000/rs6000.md | 58 +---
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 65 +---
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/float128-constant.c | 160 ---------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ----
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ----
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ----
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---
15 files changed, 28 insertions(+), 1057 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index a15b659d9d7..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,21 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; A scalar or vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eD"
- "A constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 21eff6c1ec2..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,18 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* Constants that can be generated with ISA 3.1 instructions are easy. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -621,40 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_xxspltidp (&vec_const));
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we generate the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_FLOAT128_HW || !TARGET_VSX)
- return false;
-
- /* Convert the vector constant to bytes. */
- return (vec_const_to_bytes (op, mode, &vec_const)
- && vec_const_use_lxvkq (&vec_const));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -703,19 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (TARGET_POWER10 && vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 43c0f96aab5..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,29 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_16BIT (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_32BIT (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_64BIT (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned HOST_WIDE_INT d_words[VECTOR_CONST_64BIT];
- unsigned int words[VECTOR_CONST_32BIT];
- unsigned short h_words[VECTOR_CONST_16BIT];
- unsigned char bytes[VECTOR_CONST_BYTES];
- machine_mode orig_mode; /* Original mode. */
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 326920bbad9..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6990,22 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (TARGET_POWER10 && vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26740,41 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28638,337 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_32BIT];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- unsigned HOST_WIDE_INT df_upper = vec_const->d_words[0];
- unsigned HOST_WIDE_INT df_lower = vec_const->d_words[1];
- if (df_upper != df_lower)
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with XXSPLTIB and sign
- extension for integer. */
- if (df_upper == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = DImode;
-
- if (!FLOAT_MODE_P (mode) && IN_RANGE (df_upper, -128, 127))
- return false;
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and signalling NaN bit pattern. Recognize infinity and negative
- infinity.
-
- The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for the
- exponent, and 52 bits for the mantissa (not counting the hidden bit used
- for normal numbers). NaN values have the exponent set to all 1 bits, and
- the mantissa non-zero (mantissa == 0 is infinity). */
-
- /* Bit representation of DFmode normal quiet NaN. */
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-
- /* Bit representation of DFmode normal signaling NaN. */
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-
- /* Bit representation of DFmode positive infinity. */
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-
- /* Bit representation of DFmode negative infinity. */
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (df_upper != VECTOR_CONST_DF_NAN
- && df_upper != VECTOR_CONST_DF_NANS
- && df_upper != VECTOR_CONST_DF_INF
- && df_upper != VECTOR_CONST_DF_NEG_INF)
- {
- int df_exponent = (df_upper >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = df_upper & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->xxspltidp_immediate = sf_value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_32BIT; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction, record the immediate needed for the
- instruction. */
- vec_const->lxvkq_immediate = immediate;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* If we don't know the size of the constant, punt. */
- if (mode == VOIDmode)
- return false;
-
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- /* Scalars are treated as 64-bit integers. */
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* SFmode stored as scalars is stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. Also handle VEC_DUPLICATE. */
- case CONST_VECTOR:
- case VEC_DUPLICATE:
- {
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_16BIT; i++)
- vec_const->h_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[2*i + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_32BIT; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4*i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_64BIT; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8*i) + j];
-
- vec_const->d_words[i] = d_word;
- }
-
- /* Remember original mode that the vector/scalar used. */
- vec_const->orig_mode = mode;
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cf42b6d2058..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eD,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eD,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c9eb78952d6..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,14 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index baf2e78e7dc..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,16 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTIDP LXVKQ
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- wD, wQ,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,47 +1213,36 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTIDP LXVKQ
-;; VMX const GPR const
+;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, v, ?wa,
- wa, wa,
- v, <??r>,
+ wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- wE, jwM, ?jwM,
- eD, eQ,
- W, <nW>,
+ wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1267,21 +1253,15 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
- *, *,
+ vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
- *, *,
- 20, 16,
+ *, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p9v, *, <VSisa>,
- p10, p10,
- *, *,
+ p9v, *, <VSisa>, *, *,
*, *")])
;; Explicit load/store expanders for the builtin functions
@@ -6478,39 +6458,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and vector constants that look like DFmode floating point
-;; values where both elements are the same. The constant has to be expressible
-;; as a SFmode constant that is not a SFmode denormal value.
-;;
-;; We don't need splitters for the 128-bit types, since the function
-;; rs6000_output_move_128bit handles the generation of XXSPLTIDP.
-(define_mode_iterator XXSPLTIDP [DI SF DF])
-
-(define_insn "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_split
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (match_operand:XXSPLTIDP 1 "easy_vector_constant_64bit_element"))]
- "TARGET_POWER10"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- rs6000_vec_const vec_const;
- if (!vec_const_to_bytes (operands[1], <MODE>mode, &vec_const)
- || !vec_const_use_xxspltidp (&vec_const))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
-})
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 501e0069ebb..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,15 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index f6becac1075..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-14 13:43 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-14 13:43 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:34e987c850319d1570404590531bfc46cfaa7205
commit 34e987c850319d1570404590531bfc46cfaa7205
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 14 09:41:25 2021 -0400
Revert patches.
2021-10-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_32bit_element): New predicate.
(easy_vector_constant): Add support for XXSPLTIW.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add fields for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eW constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New
declaration.
(VECTOR_CONST_*): New macros.
(rs6000_vec_const): New structure to hold information about vector
constants.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
XXSPLTIDP.
(prefixed_xxsplti_p): New function.
(vec_const_integer): New helper function.
(vec_const_floating_poin): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for
insns that generate XXSPLTIDP.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
XXSPLTIDP.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal): New insn.
(XXSPLTIDP splitters): New splitters for XXSPLTIDP.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 15 -
gcc/config/rs6000/predicates.md | 90 -----
gcc/config/rs6000/rs6000-protos.h | 32 --
gcc/config/rs6000/rs6000.c | 428 ---------------------
gcc/config/rs6000/rs6000.md | 58 +--
gcc/config/rs6000/rs6000.opt | 12 -
gcc/config/rs6000/vsx.md | 66 +---
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/float128-constant.c | 160 --------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ---
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---
19 files changed, 36 insertions(+), 1351 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index d2a1c088995..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,26 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; A scalar or vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eD"
- "A constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
-;; A scalar or vector constant that can be loaded with the XXSPLTIW instruction.
-(define_constraint "eW"
- "A constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "easy_vector_constant_32bit_element"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index cb7af8b33c4..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,22 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- if (vec_const_use_lxvkq (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -625,64 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Convert the vector constant to bytes. */
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- return vec_const_use_xxspltidp (&vec_const);
-})
-
-;; Return 1 if the operand is a 32-bit vector constant that can be loaded via
-;; the XXSPLTIW instruction.
-
-(define_predicate "easy_vector_constant_32bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we do the XXSPLTIW instruction? */
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Convert the vector constant to bytes. */
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- return vec_const_use_xxspltiw (&vec_const);
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we do the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Convert the vector constant to bytes. */
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- return vec_const_use_lxvkq (&vec_const);
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -731,22 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
-
- if (vec_const_use_lxvkq (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 089e1b33c43..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,37 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_16BIT (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_32BIT (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_64BIT (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned char bytes[VECTOR_CONST_BYTES];
- unsigned short h_words[VECTOR_CONST_16BIT];
- unsigned int words[VECTOR_CONST_32BIT];
- unsigned HOST_WIDE_INT d_words[VECTOR_CONST_64BIT];
- machine_mode orig_mode; /* Original mode. */
- enum rtx_code orig_code; /* Original rtx code. */
- bool is_xxspltidp; /* Use XXSPLTIDP to load constant. */
- machine_mode xxspltidp_mode; /* Mode to use for XXSPLTIDP. */
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- bool is_xxspltiw; /* Use XXSPLTIDP to load constant. */
- unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
- bool is_lxvkq; /* LXVKQ can load the constant. */
- unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */
- bool is_prefixed; /* Prefixed instruction used. */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4b800ab7d52..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6990,28 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
-
- if (vec_const_use_xxspltiw (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltiw_immediate);
- return "xxspltiw %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26746,47 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const.is_prefixed)
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_xxspltiw (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28650,371 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_32BIT];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- unsigned HOST_WIDE_INT df_upper = vec_const->d_words[0];
- unsigned HOST_WIDE_INT df_lower = vec_const->d_words[1];
- if (df_upper != df_lower)
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with XXSPLTIB and sign
- extension for integer. */
- if (df_upper == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = DImode;
-
- if (!FLOAT_MODE_P (mode) && IN_RANGE (df_upper, -128, 127))
- return false;
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and signalling NaN bit pattern. Recognize infinity and negative
- infinity.
-
- The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for the
- exponent, and 52 bits for the mantissa (not counting the hidden bit used
- for normal numbers). NaN values have the exponent set to all 1 bits, and
- the mantissa non-zero (mantissa == 0 is infinity). */
-
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (df_upper != VECTOR_CONST_DF_NAN
- && df_upper != VECTOR_CONST_DF_NANS
- && df_upper != VECTOR_CONST_DF_INF
- && df_upper != VECTOR_CONST_DF_NEG_INF)
- {
- int df_exponent = (df_upper >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = df_upper & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->is_xxspltidp = true;
- vec_const->is_prefixed = true;
- vec_const->xxspltidp_immediate = sf_value;
- vec_const->xxspltidp_mode = FLOAT_MODE_P (mode) ? E_DFmode : E_DImode;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that each of the 4 32-bit segments are the same. */
- unsigned int value = vec_const->words[0];
- if (value != vec_const->words[1]
- || value != vec_const->words[2]
- || value != vec_const->words[3])
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with XXSPLTIB and sign
- extension for integer. */
- if (value == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = SImode;
-
- if (!FLOAT_MODE_P (mode) && IN_RANGE (value, -128, 127))
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIW. */
- vec_const->is_xxspltiw = true;
- vec_const->is_prefixed = true;
- vec_const->xxspltiw_immediate = value;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_32BIT; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction. */
- vec_const->lxvkq_immediate = immediate;
- vec_const->is_lxvkq = true;
- vec_const->is_prefixed = false;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* If we don't know the size of the constant, punt. */
- if (mode == VOIDmode)
- return false;
-
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* SFmode stored as scalars is stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. Also handle VEC_DUPLICATE. */
- case CONST_VECTOR:
- case VEC_DUPLICATE:
- {
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_16BIT; i++)
- vec_const->h_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[2*i + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_32BIT; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4*i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_64BIT; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8*i) + j];
-
- vec_const->d_words[i] = d_word;
- }
-
- /* Remember original mode and code. */
- vec_const->orig_mode = mode;
- vec_const->orig_code = GET_CODE (op);
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index cf42b6d2058..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eD,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eD,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 015bf91b6d5..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,18 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 95b29dd38dd..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,20 +1192,17 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) XXLSPLTIDP
-;; LXVKQ XXLSPLTIW
+;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?wa, v, <??r>, wZ, v, wa,
- wa, wa")
+ ?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ, eD,
- eQ, eW"))]
+ ?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1216,42 +1213,37 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecsimple, *, *, vecstore, vecload, vecperm,
- vecperm, vecperm")
+ vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, 5, 2, *, *, *,
- *, *")
+ *, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *, *, *, *,
- *, *")
+ *, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, 20, 8, *, *, *,
- *, *")
+ *, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- <VSisa>, *, *, *, *, p10,
- p10, p10")])
+ <VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
-;; LVX (VMX) STVX (VMX) XXSPLTID LXVKQ XXSPLTIW
+;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa, v, <??r>,
- wZ, v, wa, wa, wa")
+ wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM, W, <nW>,
- v, wZ, eD, eQ, eW"))]
+ v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1262,15 +1254,15 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple, *, *,
- vecstore, vecload, vecperm, vecperm, vecperm")
+ vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *, 20, 16,
- *, *, *, *, *")
+ *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>, *, *,
- *, *, p10, p10, p10")])
+ *, *")])
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
@@ -6466,36 +6458,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-(define_mode_iterator XXSPLTIDP [DI SF DF V16QI V8HI V4SI V4SF V2DF V2DI])
-
-(define_insn "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and vector constants that look like DFmode floating point
-;; values where both elements are the same. The constant has to be expressible
-;; as a SFmode constant that is not a SFmode denormal value.
-(define_split
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (match_operand:XXSPLTIDP 1 "easy_vector_constant_64bit_element"))]
- "TARGET_POWER10"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- rs6000_vec_const vec_const;
- if (!vec_const_to_bytes (operands[1], <MODE>mode, &vec_const)
- || !vec_const_use_xxspltidp (&vec_const))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
-})
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 501e0069ebb..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,15 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index f6becac1075..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-vector long long
-return_longlong_neg_0 (void)
-{
- /* This vector is the same pattern as -0.0F128. */
-#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-#define FIRST 0x8000000000000000
-#define SECOND 0x0000000000000000
-
-#else
-#define FIRST 0x0000000000000000
-#define SECOND 0x8000000000000000
-#endif
-
- return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index 2cefe3ffa70..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIB/VEXTSB2W. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIB/VEXTSB2W. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvextsb2w\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 18+ messages in thread
* [gcc(refs/users/meissner/heads/work071)] Revert patches.
@ 2021-10-14 2:59 Michael Meissner
0 siblings, 0 replies; 18+ messages in thread
From: Michael Meissner @ 2021-10-14 2:59 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a3064386c0c96e21159f151050bdf5ffcf9a1217
commit a3064386c0c96e21159f151050bdf5ffcf9a1217
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 13 22:57:00 2021 -0400
Revert patches.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating the LXVKQ instruction.
(easy_vector_constant_ieee128): New predicate.
(easy_vector_constant): Add support for generating the LXVKQ
instruction.
* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
for generating LXVKQ.
* config/rs6000/rs6000.c (output_vec_const_move): Add support for
generating LXVKQ.
(vec_const_use_lxvkq): New function.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
generating LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/predicates.md (easy_fp_constant): Move to using
vec_const instead of calling easy_vector_constant_64bit_element.
(easy_vector_constant): Likewise.
* config/rs6000/rs6000.c (output_vec_const_move): Rework code
slightly to improve future patches.
(prefixed_xxsplti_p): Likewise.
(vec_const_to_bytes): SFmode as a scalar in registers uses the
DFmode format.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add XXSPLTIDP
support.
(vsx_mov<mode>_32bit): Likewise.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/rs6000.c (vec_const_to_bytes): Fix typo.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/predicates.md
(easy_vector_constant_64bit_element): Switch to use
rs6000_vec_const.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate):
Delete.
(convert_vector_constant_to_bytes): Likewise.
(convert_scalar_64bit_constant_to_bytes): Likewise.
(prefixed_xxsplti_p): Likewise.
(VECTOR_CONST_*): New defines.
(rs6000_vec_const): New data structure.
(vec_const_to_bytes): New function.
(vec_const_use_xxspltidp): New function.
* config/rs6000/rs6000.c (convert_vector_constant_to_bytes):
Delete.
(convert_scalar_64bit_constant_to_bytes): Likewise.
(xxspltidp_constant_immediate): Likewise.
(output_vec_const_move): Switch to use rs6000_vec_const.
(prefixed_xxsplti_p): Likewise.
(vec_const_integer): New helper function.
(vec_const_floating_point): New helper function.
(vec_const_use_xxspltidp): New function.
(vec_const_to_bytes): New function.
* config/rs6000/vsx.md (XXSPLTIDP splitters): Switch to use
rs6000_vec_const.
2021-10-12 Michael Meissner <meissner@the-meissners.org>
gcc/
Revert patches.
* config/rs6000/constraints.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
generating XXSPLTIDP.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): Add support for generating XXSPLTIDP.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate):
New declaration.
(convert_vector_constant_to_bytes): Likewise.
(convert_scalar_64bit_constant_to_bytes): Likewise.
(prefixed_xxsplti_p): Likewise.
* config/rs6000/rs6000.c (convert_vector_constant_to_bytes): New
helper function.
(convert_scalar_64bit_constant_to_bytes): Likewise.
(xxspltidp_constant_immediate): Likewise.
(output_vec_const_move): Add support for XXSPLTIDP.
(prefixed_xxsplti_p): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for
insns that generate XXSPLTIDP.
(movsf_hardfloat): Add support for XXSPLTIDP.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New debug option.
* config/rs6000/vsx.md (XXSPLTIDP): New mode iterator.
(xxspltidp_<mode>_internal): New insn.
(XXSPLTIDP splitters): New splitters for XXSPLTIDP.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 -
gcc/config/rs6000/predicates.md | 65 ----
gcc/config/rs6000/rs6000-protos.h | 29 --
gcc/config/rs6000/rs6000.c | 382 ---------------------
gcc/config/rs6000/rs6000.md | 58 +---
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 66 +---
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/float128-constant.c | 144 --------
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ----
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ----
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ----
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ----
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---
15 files changed, 36 insertions(+), 1045 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index a15b659d9d7..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,21 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; A scalar or vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eD"
- "A constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; 128-bit IEEE 128-bit constant
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_vector_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 2c9c0a29845..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,19 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_lxvkq (&vec_const))
- return true;
- }
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -622,45 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Convert the vector constant to bytes. */
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- return vec_const_use_xxspltidp (&vec_const);
-})
-
-;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
-;; via the LXVKQ instruction.
-
-(define_predicate "easy_vector_constant_ieee128"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- rs6000_vec_const vec_const;
-
- /* Can we do the LXVKQ instruction? */
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Convert the vector constant to bytes. */
- if (!vec_const_to_bytes (op, mode, &vec_const))
- return false;
-
- return vec_const_use_lxvkq (&vec_const);
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -709,19 +657,6 @@
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
- /* See if the constant can be generated with the ISA 3.1
- instructions. */
- rs6000_vec_const vec_const;
-
- if (vec_const_to_bytes (op, mode, &vec_const))
- {
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
-
- if (vec_const_use_lxvkq (&vec_const))
- return true;
- }
-
return easy_altivec_constant (op, mode);
}
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 388fe18e314..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
@@ -223,34 +222,6 @@ address_is_prefixed (rtx addr,
return (iform == INSN_FORM_PREFIXED_NUMERIC
|| iform == INSN_FORM_PCREL_LOCAL);
}
-
-/* Functions and data structures relating to 128-bit vector constants. All
- fields are kept in big endian order. */
-#define VECTOR_CONST_BITS 128
-#define VECTOR_CONST_BYTES (VECTOR_CONST_BITS / 8)
-#define VECTOR_CONST_16BIT (VECTOR_CONST_BITS / 16)
-#define VECTOR_CONST_32BIT (VECTOR_CONST_BITS / 32)
-#define VECTOR_CONST_64BIT (VECTOR_CONST_BITS / 64)
-
-typedef struct {
- /* Vector constant as various sized items. */
- unsigned char bytes[VECTOR_CONST_BYTES];
- unsigned short h_words[VECTOR_CONST_16BIT];
- unsigned int words[VECTOR_CONST_32BIT];
- unsigned HOST_WIDE_INT d_words[VECTOR_CONST_64BIT];
- machine_mode orig_mode; /* Original mode. */
- enum rtx_code orig_code; /* Original rtx code. */
- bool is_xxspltidp; /* Use XXSPLTIDP to load constant. */
- machine_mode xxspltidp_mode; /* Mode to use for XXSPLTIDP. */
- unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
- bool is_lxvkq; /* LXVKQ can load the constant. */
- unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */
- bool is_prefixed; /* Prefixed instruction used. */
-} rs6000_vec_const;
-
-extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
-extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
-extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
#ifdef TREE_CODE
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2a038ea7dea..acba4d9f26c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6990,22 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (vec, mode, &vec_const))
- {
- if (vec_const_use_lxvkq (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.lxvkq_immediate);
- return "lxvkq %x0,%2";
- }
-
- if (vec_const_use_xxspltidp (&vec_const))
- {
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
- return "xxspltidp %x0,%2";
- }
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26740,44 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- if (GET_CODE (src) == UNSPEC)
- {
- int unspec = XINT (src, 1);
- return (unspec == UNSPEC_XXSPLTIW
- || unspec == UNSPEC_XXSPLTIDP
- || unspec == UNSPEC_XXSPLTI32DX);
- }
-
- rs6000_vec_const vec_const;
- if (vec_const_to_bytes (src, mode, &vec_const))
- {
- if (vec_const.is_prefixed)
- return true;
-
- if (vec_const_use_xxspltidp (&vec_const))
- return true;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
@@ -28641,334 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value)
fprintf (file, "\n");
}
-\f
-/* Copy an integer constant to the vector constant structure. */
-
-static void
-vec_const_integer (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned HOST_WIDE_INT uvalue = UINTVAL (op);
- unsigned bitsize = GET_MODE_BITSIZE (mode);
-
- for (int shift = bitsize - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
-}
-
-/* Copy an floating point constant to the vector constant structure. */
-
-static void
-vec_const_floating_point (rtx op,
- machine_mode mode,
- size_t byte_num,
- rs6000_vec_const *vec_const)
-{
- unsigned bitsize = GET_MODE_BITSIZE (mode);
- unsigned num_words = bitsize / 32;
- const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op);
- long real_words[VECTOR_CONST_32BIT];
-
- /* Make sure we don't overflow the real_words array and that it is
- filled completely. */
- gcc_assert (bitsize <= VECTOR_CONST_BITS && (bitsize % 32) == 0);
-
- real_to_target (real_words, rtype, mode);
-
- /* Iterate over each 32-bit word in the floating point constant. The
- real_to_target function puts out words in endian fashion. We need
- to arrange so the words are written in big endian order. */
- for (unsigned num = 0; num < num_words; num++)
- {
- unsigned endian_num = (BYTES_BIG_ENDIAN
- ? num
- : num_words - 1 - num);
-
- unsigned uvalue = real_words[endian_num];
- for (int shift = 32 - 8; shift >= 0; shift -= 8)
- vec_const->bytes[byte_num++] = (uvalue >> shift) & 0xff;
- }
-}
-
-/* Determine if a vector constant can be loaded with XXSPLTIDP. If so,
- fill out the fields used to generate the instruction. */
-
-bool
-vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
-{
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Make sure that the two 64-bit segments are the same. */
- unsigned HOST_WIDE_INT df_upper = vec_const->d_words[0];
- unsigned HOST_WIDE_INT df_lower = vec_const->d_words[1];
- if (df_upper != df_lower)
- return false;
-
- /* Avoid values that are easy to create with other instructions (0.0 for
- floating point, and values that can be loaded with XXSPLTIB and sign
- extension for integer. */
- if (df_upper == 0)
- return false;
-
- machine_mode mode = vec_const->orig_mode;
- if (mode == VOIDmode)
- mode = DImode;
-
- if (!FLOAT_MODE_P (mode) && IN_RANGE (df_upper, -128, 127))
- return false;
-
- /* Avoid values that look like DFmode NaN's, except for the normal NaN bit
- pattern and signalling NaN bit pattern. Recognize infinity and negative
- infinity.
-
- The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for the
- exponent, and 52 bits for the mantissa (not counting the hidden bit used
- for normal numbers). NaN values have the exponent set to all 1 bits, and
- the mantissa non-zero (mantissa == 0 is infinity). */
-
-#define VECTOR_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000)
-#define VECTOR_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000)
-#define VECTOR_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000)
-#define VECTOR_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000)
-
- if (df_upper != VECTOR_CONST_DF_NAN
- && df_upper != VECTOR_CONST_DF_NANS
- && df_upper != VECTOR_CONST_DF_INF
- && df_upper != VECTOR_CONST_DF_NEG_INF)
- {
- int df_exponent = (df_upper >> 52) & 0x7ff;
- unsigned HOST_WIDE_INT df_mantissa
- = df_upper & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers have
- the exponent all 0 bits, and the mantissa non-zero. If the value is
- subnormal, then the hidden bit in the mantissa is not set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
- }
-
- /* Change the representation to DFmode constant. */
- long df_words[2] = { vec_const->words[0], vec_const->words[1] };
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE rv_type;
- real_from_target (&rv_type, df_words, DFmode);
-
- const REAL_VALUE_TYPE *rv = &rv_type;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- /* Record the information in the vec_const structure for XXSPLTIDP. */
- vec_const->is_xxspltidp = true;
- vec_const->is_prefixed = true;
- vec_const->xxspltidp_immediate = sf_value;
- vec_const->xxspltidp_mode = FLOAT_MODE_P (mode) ? E_DFmode : E_DImode;
-
- return true;
-}
-
-/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
- the fields used to generate the instruction. */
-
-bool
-vec_const_use_lxvkq (rs6000_vec_const *vec_const)
-{
- unsigned immediate;
-
- if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- /* Verify that all of the bottom 3 words in the constants loaded by the
- LXVKQ instruction are zero. */
- for (size_t i = 1; i < VECTOR_CONST_32BIT; i++)
- if (vec_const->words[i] != 0)
- return false;
-
- /* See if we have a match. */
- switch (vec_const->words[0])
- {
- case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */
- case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */
- case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */
- case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */
- case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */
- case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */
- case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */
- case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */
- case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */
- case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */
- case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */
- case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */
- case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */
- case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */
- case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */
- case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */
- case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */
- case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */
-
- /* anything else cannot be loaded. */
- default:
- return false;
- }
-
- /* We can use the LXVKQ instruction. */
- vec_const->lxvkq_immediate = immediate;
- vec_const->is_lxvkq = true;
- vec_const->is_prefixed = false;
- return true;
-}
-
-/* Convert a vector constant to an internal structure, breaking it out to
- bytes, half words, words, and double words. Return true if we have
- successfully broken it out. */
-
-bool
-vec_const_to_bytes (rtx op,
- machine_mode mode,
- rs6000_vec_const *vec_const)
-{
- /* Initialize vec const structure. */
- memset ((void *)vec_const, 0, sizeof (rs6000_vec_const));
-
- /* If we don't know the size of the constant, punt. */
- if (mode == VOIDmode)
- return false;
-
- switch (GET_CODE (op))
- {
- /* Integer constants, default to double word. */
- case CONST_INT:
- {
- if (mode == VOIDmode)
- mode = DImode;
-
- vec_const_integer (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Floating point constants. */
- case CONST_DOUBLE:
- {
- /* SFmode stored as scalars is stored in DFmode format. */
- if (mode == SFmode)
- mode = DFmode;
-
- vec_const_floating_point (op, mode, 0, vec_const);
-
- /* Splat the constant to the rest of the vector constant structure. */
- unsigned size = GET_MODE_SIZE (mode);
- gcc_assert (size <= VECTOR_CONST_BYTES);
- gcc_assert ((VECTOR_CONST_BYTES % size) == 0);
-
- for (size_t splat = size; splat < VECTOR_CONST_BYTES; splat += size)
- memcpy ((void *) &vec_const->bytes[splat],
- (void *) &vec_const->bytes[0],
- size);
- break;
- }
-
- /* Vector constants, iterate each element. On little endian systems, we
- have to reverse the element numbers. Also handle VEC_DUPLICATE. */
- case CONST_VECTOR:
- case VEC_DUPLICATE:
- {
- machine_mode ele_mode = GET_MODE_INNER (mode);
- size_t nunits = GET_MODE_NUNITS (mode);
- size_t size = GET_MODE_SIZE (ele_mode);
-
- for (size_t num = 0; num < nunits; num++)
- {
- rtx ele = (GET_CODE (op) == VEC_DUPLICATE
- ? XEXP (op, 0)
- : CONST_VECTOR_ELT (op, num));
- size_t byte_num = (BYTES_BIG_ENDIAN
- ? num
- : nunits - 1 - num) * size;
-
- if (CONST_INT_P (ele))
- vec_const_integer (ele, ele_mode, byte_num, vec_const);
- else if (CONST_DOUBLE_P (ele))
- vec_const_floating_point (ele, ele_mode, byte_num, vec_const);
- else
- return false;
- }
-
- break;
- }
-
- /* Any thing else, just return failure. */
- default:
- return false;
- }
-
- /* Pack half words together. */
- for (size_t i = 0; i < VECTOR_CONST_16BIT; i++)
- vec_const->h_words[i] = ((vec_const->bytes[2*i] << 8)
- | vec_const->bytes[2*i + 1]);
-
- /* Pack words together. */
- for (size_t i = 0; i < VECTOR_CONST_32BIT; i++)
- {
- unsigned word = 0;
- for (size_t j = 0; j < 4; j++)
- word = (word << 8) | vec_const->bytes[(4*i) + j];
-
- vec_const->words[i] = word;
- }
-
- /* Pack double words together. */
- for (size_t i = 0; i < VECTOR_CONST_64BIT; i++)
- {
- unsigned HOST_WIDE_INT d_word = 0;
- for (size_t j = 0; j < 8; j++)
- d_word = (d_word << 8) | vec_const->bytes[(8*i) + j];
-
- vec_const->d_words[i] = d_word;
- }
-
- /* Remember original mode and code. */
- vec_const->orig_mode = mode;
- vec_const->orig_code = GET_CODE (op);
-
- return true;
-}
-
-\f
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rs6000.h"
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9ac5b8df173..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eD"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eD"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eD"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eD,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eD,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c9eb78952d6..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,14 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index eddbf395e77..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,20 +1192,17 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) XXLSPLTIDP
-;; LXVKQ
+;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?wa, v, <??r>, wZ, v, wa,
- wa")
+ ?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ, eD,
- eQ"))]
+ ?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1216,42 +1213,37 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecsimple, *, *, vecstore, vecload, vecperm,
- vecperm")
+ vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, 5, 2, *, *, *,
- *")
+ *, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *, *, *, *,
- *")
+ *, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, 20, 8, *, *, *,
- *")
+ *, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- <VSisa>, *, *, *, *, p10,
- p10")])
+ <VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
-;; LVX (VMX) STVX (VMX) XXSPLTID LXVKQ
+;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa, v, <??r>,
- wZ, v, wa, wa")
+ wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM, W, <nW>,
- v, wZ, eD, eQ"))]
+ v, wZ"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1262,15 +1254,15 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple, *, *,
- vecstore, vecload, vecperm, vecperm")
+ vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *, 20, 16,
- *, *, *, *")
+ *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>, *, *,
- *, *, p10, p10")])
+ *, *")])
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
@@ -6466,36 +6458,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-(define_mode_iterator XXSPLTIDP [DI SF DF V16QI V8HI V4SI V4SF V2DF V2DI])
-
-(define_insn "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
- "TARGET_POWER10"
- "xxspltidp %x0,%1"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and vector constants that look like DFmode floating point
-;; values where both elements are the same. The constant has to be expressible
-;; as a SFmode constant that is not a SFmode denormal value.
-(define_split
- [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand")
- (match_operand:XXSPLTIDP 1 "easy_vector_constant_64bit_element"))]
- "TARGET_POWER10"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- rs6000_vec_const vec_const;
- if (!vec_const_to_bytes (operands[1], <MODE>mode, &vec_const)
- || !vec_const_use_xxspltidp (&vec_const))
- gcc_unreachable ();
-
- operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
-})
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 501e0069ebb..41f1850bf6e 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,15 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-A constant that can be loaded with the LXVKQ instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index 23ee7e85d84..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
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