[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:3dce5092f5040beca628c4f9194c7ae5d39c5bc7

commit 3dce5092f5040beca628c4f9194c7ae5d39c5bc7
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 12:55:26 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 9db64884a54..bcf384fdf41 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -4,7 +4,7 @@ Improve vsx_extract_<mode>
 In looking at PR target/99293, I noticed that the insn "type" attribute is
 incorrect.  This patch fixes those attributes.
 
-2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
 	PR target/99392

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:cd5e86a0662bea0d9632c3bc9524a2e92bf0a232

commit cd5e86a0662bea0d9632c3bc9524a2e92bf0a232
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 14:24:36 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bcf384fdf41..6b50a1daeb2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,20 @@
+==================== Work082, patch #11:
+Allow vsx_extract_<mode> to use Altivec registers
+
+In looking at PR target/99293, I noticed that the vsx_extract_<mode>
+pattern for V2DImode and V2DFmode only allowed traditional floating point
+registers, and it did not allow Altivec registers.  The original code was
+written a few years ago when we used the old register allocator, and
+support for scalar floating point in Altivec registers was just being
+added to GCC.
+
+2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_extract_<mode>): Allow destination
+	to be an Altivec register.
+
 ==================== Work082, patch #10:
 Improve vsx_extract_<mode>

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:3b1cf8a2aae57953c1a6e6371f598747a4d71dd2

commit 3b1cf8a2aae57953c1a6e6371f598747a4d71dd2
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 12:53:02 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 8cf11cf85b4..9db64884a54 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,16 @@
+==================== Work082, patch #10:
+Improve vsx_extract_<mode>
+
+In looking at PR target/99293, I noticed that the insn "type" attribute is
+incorrect.  This patch fixes those attributes.
+
+2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_extract_<mode>): Use the correct
+	insn type for the alternatives.
+
 ==================== Work082, patch #9 (reverted):
 
 ==================== Work082, patch #8:

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:048a4d58b235e3d9f102529394c97594c02f43b6

commit 048a4d58b235e3d9f102529394c97594c02f43b6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 23 21:34:57 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 23 +----------------------
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 993dca92e4f..8cf11cf85b4 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,25 +1,4 @@
-==================== Work082, patch #9:
-Improve vsx_extract_<mode>
-
-In looking at PR target/99293, I noticed that the code in
-vsx_extract_<mode> could be improved.
-
-When the element being extracted is the element in the upper 64-bits, we
-should do an insn_split to convert this to a simple move.  This would
-allow the post reload passes to eliminate the move completely.
-
-The insn type attribute was incorrect in that it used "mfvsr" instead of
-"vecperm" when a xxpermdi would be generated.  Also, when a "mvfsrld"
-would be generated, the type should be "mfvsr".
-
-2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
-
-gcc/
-	PR target/99392
-	* config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
-	that are just a move to being a move insn.  Use the correct insn
-	type for the alternatives.
-	(insn splitter for vsx_extract_<mode>): Add new splitter.
+==================== Work082, patch #9 (reverted):
 
 ==================== Work082, patch #8:
 Improve vsx_splat_<mode>_reg

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:ebfdc2c7d4c22bbbf88b8e73818ff95519989262

commit ebfdc2c7d4c22bbbf88b8e73818ff95519989262
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 23 19:33:24 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index f07d4226576..993dca92e4f 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,4 +1,41 @@
-==================== Work082, patch #8 (reverted):
+==================== Work082, patch #9:
+Improve vsx_extract_<mode>
+
+In looking at PR target/99293, I noticed that the code in
+vsx_extract_<mode> could be improved.
+
+When the element being extracted is the element in the upper 64-bits, we
+should do an insn_split to convert this to a simple move.  This would
+allow the post reload passes to eliminate the move completely.
+
+The insn type attribute was incorrect in that it used "mfvsr" instead of
+"vecperm" when a xxpermdi would be generated.  Also, when a "mvfsrld"
+would be generated, the type should be "mfvsr".
+
+2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
+	that are just a move to being a move insn.  Use the correct insn
+	type for the alternatives.
+	(insn splitter for vsx_extract_<mode>): Add new splitter.
+
+==================== Work082, patch #8:
+Improve vsx_splat_<mode>_reg
+
+In looking at PR target/99293, I noticed that the code in
+vsx_splat_<mode>_reg used "vecmove" as the "type" insn attribute when the
+"mtvsrdd" is generated.  It should use "mfvsr".  I also added a "p9v" isa
+attribute for that alternative.
+
+2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_splat_<mode>_reg): Use the correct
+	insn type attribute.  Add "p9v" isa attribute as needed.
+
 
 ==================== Work082, patch #7 (reverted):

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:4fe51e53ebdcddd624ca3f26dad7550d46730b83

commit 4fe51e53ebdcddd624ca3f26dad7550d46730b83
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 23 12:56:13 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 37ced301982..b28bab31f0a 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,46 @@
+==================== Work082, patch #8:
+Improve vsx_splat_<mode>_reg
+
+In looking at PR target/99293, I noticed that the code in
+vsx_splat_<mode>_reg used "vecmove" as the "type" insn attribute when the
+"mtvsrdd" is generated.  It should use "mfvsr".  I also added a "p9v" isa
+attribute for that alternative.
+
+2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_splat_<mode>_reg): Use the correct
+	insn type attribute.  Add "p9v" isa attribute as needed.
+
+
+==================== Work082, patch #7:
+Improve vsx_extract_<mode>
+
+In looking at PR target/99293, I noticed that the code in
+vsx_extract_<mode> could be improved.
+
+When the element being extracted is the element in the upper 64-bits, we
+should do an insn_split to convert this to a simple move.  This would
+allow the post reload passes to eliminate the move completely.
+
+The code was written before we moved to LRA for register allocation and it
+restricted the target register to just traditional floating point
+registers.  I have changed this to target any VSX register.
+
+The insn type attribute was incorrect in that it used "mfvsr" instead of
+"vecperm" when a xxpermdi would be generated.  Also, when a "mvfsrld"
+would be generated, the type should be "mfvsr".
+
+2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
+	that are just a move to being a move insn.  Use the correct insn
+	type for the alternatives.
+	(insn splitter for vsx_extract_<mode>): Add new splitter.
+
 ==================== Work082, patch #6:
 Optimize vec_splats of constant vec_extract for V2DI/V2DF.

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:4e9c51e9364bfc88b05b9d0808dfc9bfdff3cc55

commit 4e9c51e9364bfc88b05b9d0808dfc9bfdff3cc55
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 23 01:21:07 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 53691a0dc53..37ced301982 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,52 @@
+==================== Work082, patch #6:
+Optimize vec_splats of constant vec_extract for V2DI/V2DF.
+
+In PR target/99293, it was pointed out that doing:
+
+	vector long long dest0, dest1, src;
+	/* ... */
+	dest0 = vec_splats (vec_extract (src, 0));
+	dest1 = vec_splats (vec_extract (src, 1));
+
+would generate slower code.
+
+It generates the following code on power8:
+
+	;; vec_splats (vec_extract (src, 0))
+	xxpermdi 0,34,34,3
+	xxpermdi 34,0,0,0
+
+	;; vec_splats (vec_extract (src, 1))
+	xxlor 0,34,34
+	xxpermdi 34,0,0,0
+
+However on power9 and power10 it generates:
+
+	;; vec_splats (vec_extract (src, 0))
+	mfvsld 3,34
+	mtvsrdd 34,9,9
+
+	;; vec_splats (vec_extract (src, 1))
+	mfvsrd 9,34
+	mtvsrdd 34,9,9
+
+This is due to the power9 having the mfvsrld instruction which can extract
+either 64-bit element into a GPR.
+
+However in this case, it is better to have a single combiner pattern that
+can generate a single xxpermdi, instead of 2 insnsn.
+
+2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/vsx.md (vsx_splat_const_extract_<mode>): New
+	insn.
+
+gcc/testsuite:
+	PR target/99392
+	* gcc.target/powerpc/pr99293.c: New test.
+
 ==================== Work082, patch #5:
 Generate vadduqm and vsubuqm for TImode add/subtract

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:107cdf9c04e9b81539aa7661bcdae63afa671c1d

commit 107cdf9c04e9b81539aa7661bcdae63afa671c1d
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Mar 22 21:28:53 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-22   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c79a5a5e387..53691a0dc53 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,20 @@
+==================== Work082, patch #5:
+Generate vadduqm and vsubuqm for TImode add/subtract
+
+If the TImode variable is in an Altivec register instead of a GPR
+register, then generate vadduqm and vsubuqm instead of having to move the
+value to the GPR registers and doing the add and subtract with carry
+instructions.  To do this, we have to delay the splitting of the addition
+and subtraction until after register allocation.
+
+2022-03-22   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/rs6000.md (addti3): Generate vadduqm if we are
+	using the Altivec registers.
+	(subti3): Generate vsubuqm if we using the Altivec registers.
+	(negti3): New insn.
+
 ==================== Work082, patch #4:
 
 Optimize multiply/add of DImode extended to TImode.
@@ -47,10 +64,10 @@ instructions.  In order to support recognizing the multiply and add
 combination, we need to keep the addti3 and subti3 as complete insns
 through the combiner phase.
 
-2022-03-18   Michael Meissner  <meissner@linux.ibm.com>
+2022-03-22   Michael Meissner  <meissner@linux.ibm.com>
 
 gcc/
-	* config/rs6000/rs6000.md (addti3): Don't immediate expand the
+	* config/rs6000/rs6000.md (addti3): Don't immediately expand the
 	insn, delay expansion until the split passes.
 	(subti3): Likewise.

[gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:d5f025d7022531724762135158f77ae153ec4436

commit d5f025d7022531724762135158f77ae153ec4436
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Mar 22 16:10:34 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-22   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 99 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 895ddd829ff..c79a5a5e387 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,102 @@
+==================== Work082, patch #4:
+
+Optimize multiply/add of DImode extended to TImode.
+
+On power9 and power10 systems, we have instructions that support doing
+64-bit integers converted to 128-bit integers and producing 128-bit
+results.  This patch adds support to generate these instructions.
+
+Previously we had define_expands to handle conversion of the 64-bit extend
+to 128-bit and multiply.  This patch changes these define_expands to
+define_insn_and_split and then it provides combiner patterns to generate
+thes multiply/add instructions.
+
+To support using this optimization on power9, we extend the sign extend
+DImode to TImode to also run on power9 (added for PR target/104698).
+
+We add support for doing an unsigned DImode to TImode conversion.  We need
+these conversions to exist on power9 so that the combiner can properly
+combine the extend, multiply, and add instructions.
+
+2022-03-22   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/103109
+	* config/rs6000/rs6000.md (su_int32): New code attribute.
+	(<u>mul<mode><dmode>3): Convert from define_expand to
+	define_insn_and_split.
+	(maddld<mode>4): Add generator function.
+	(<u>mulditi3_<u>adddi3): New insn.
+	(<u>mulditi3_add_const): New insn.
+	(<u>mulditi3_<u>adddi3_upper): New insn.
+
+gcc/testsuite/
+	PR target/103109
+	* gcc.target/powerpc/pr103109.c: New test.
+
+
+==================== Work082, patch #3:
+
+Make addti3/subti3 be define_insn_and_split, instead of define_expand
+
+This patch makes addti3 and subti3 be define_insn_and_split instead of
+define_expand.  This patch will be a building block to support in a future
+patch PR target/103109 which wants to optimize 128-bit some integer
+multiply-add combinations to use the power9 maddld, maddhd, maddhdu
+instructions.  In order to support recognizing the multiply and add
+combination, we need to keep the addti3 and subti3 as complete insns
+through the combiner phase.
+
+2022-03-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/rs6000.md (addti3): Don't immediate expand the
+	insn, delay expansion until the split passes.
+	(subti3): Likewise.
+
+==================== Work082, patch #2:
+
+Add zero_extendditi2 for power9.
+
+This patch provides a zero_extendditi2 pattern for power9 and power10.  On
+power8 and previous systems, the generic machine indepenent code will be
+used.  This patch will be a building block to support in a future patch PR
+target/103109 which wants to optimize 128-bit some integer multiply-add
+combinations to use the power9 maddld, maddhd, maddhdu instructions.
+
+2022-03-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/vsx.md (zero_extendditi2): New insn.
+
+==================== Work082, patch #1:
+
+Improve extendditi2 on PowerPC.
+
+This patch allows using extenditi2 on power9 systems as well as power10
+systems.  On power8 and previous systems, the generic machine indepenent
+code will be used.  This patch will be a building block to support in a
+future patch PR target/103109 which wants to optimize 128-bit some integer
+multiply-add combinations to use the power9 maddld, maddhd, maddhdu
+instructions.
+
+This patch improves code generation when extending a GPR to a vector
+register by generating the sign extend part in a GPR register before
+moving the value over to the vector register with the mtvsrdd
+instruction.
+
+2022-03-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/vsx.md (extendditi2): Add power9 support.  Improve
+	code generation when doing direct moves.
+
+gcc/testsuite/
+	* gcc.target/powerpc/pr104698-2.c: Update insn counts.
+
+
+==================== Initial:
+
 2022-03-17   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch