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* [gcc(refs/users/meissner/heads/dmf002)] Update ChangeLog.meissner.
@ 2022-10-27 4:45 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2022-10-27 4:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8d5d9c8de2e7438a8b90a8f5c40c791121f4c22b
commit 8d5d9c8de2e7438a8b90a8f5c40c791121f4c22b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 27 00:44:42 2022 -0400
Update ChangeLog.meissner.
2022-10-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 51 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index c515dc53d7e..92cbc846671 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,54 @@
+==================== Dmf002, patch004.
+
+Add support for 1,024 bit DMR registers.
+
+2022-10-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
+ (UNSPEC_DM_INSERT512_LOWER): Likewise.
+ (UNSPEC_DM_EXTRACT512): Likewise.
+ (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
+ (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
+ (movtdo): New define_expand and define_insn_and_split to implement 1,024
+ bit DMR registers.
+ (movtdo_insert512_upper): New insn.
+ (movtdo_insert512_lower): Likewise.
+ (movtdo_extract512): Likewise.
+ (reload_dmr_from_memory): Likewise.
+ (reload_dmr_to_memory): Likewise.
+ * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
+ support.
+ (rs6000_init_builtins): Add support for __dmr keyword.
+ * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
+ __DENSE_MATH__ if we have dense math support.
+ * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support
+ for TDOmode.
+ (rs6000_function_arg): Likewise.
+ * config/rs6000/rs6000-modes.def (TDOmode): New mode.
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
+ support for TDOmode.
+ (rs6000_hard_regno_mode_ok_uncached): Likewise.
+ (rs6000_hard_regno_mode_ok): Likewise.
+ (rs6000_modes_tieable_p): Likewise.
+ (rs6000_debug_reg_global): Likewise.
+ (rs6000_setup_reg_addr_masks): Likewise.
+ (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload
+ hooks for DMR mode.
+ (reg_offset_addressing_ok_p): Add support for TDOmode.
+ (rs6000_emit_move): Likewise.
+ (rs6000_secondary_reload_simple_move): Likewise.
+ (rs6000_secondary_reload_class): Likewise.
+ (rs6000_mangle_type): Add mangling for __dmr type.
+ (rs6000_dmr_register_move_cost): Add support for TDOmode.
+ (rs6000_split_multireg_move): Likewise.
+ (rs6000_invalid_conversion): Likewise.
+ * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
+ (enum rs6000_builtin_type_index): Add DMR type nodes.
+ (dmr_type_node): Likewise.
+ (ptr_dmr_type_node): Likewise.
+
==================== Dmf002, patch003.
Switch to dense math names for all MMA operations.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/dmf002)] Update ChangeLog.meissner.
@ 2022-11-03 2:14 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2022-11-03 2:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:aaf20de12c43a91721255dc678cb1bf46a92b436
commit aaf20de12c43a91721255dc678cb1bf46a92b436
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Nov 2 22:13:51 2022 -0400
Update ChangeLog.meissner.
2022-11-02 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index f131db29c46..3f7545a3c3d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,20 @@
+==================== Dmf002, patch006.
+
+Make wD match either FLOAT_REGS or DM_REGS.
+
+2022-11-02 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/constraint.md (wD): Match FLOAT_REGS on power10, DM_REGS
+ if dense math.
+ * config/rs6000/rs6000.md (rs6000_debug_reg_global): For -mdebug=reg,
+ print the register class for wD.
+ (rs6000_init_hard_regno_mode_ok): Set the register class for wD.
+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): New enumaation
+ value for wD.
+ * doc/md.texi (PowerPC constraints): Document wD constraint.
+
==================== Dmf002, patch005.
Add LAGEN and PLAGEN support.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/dmf002)] Update ChangeLog.meissner.
@ 2022-10-27 5:10 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2022-10-27 5:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:4746170d9175a271f0684ca428c62c4779762258
commit 4746170d9175a271f0684ca428c62c4779762258
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 27 01:09:50 2022 -0400
Update ChangeLog.meissner.
2022-10-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 92cbc846671..f131db29c46 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,21 @@
+==================== Dmf002, patch005.
+
+Add LAGEN and PLAGEN support.
+
+2022-10-27 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mlagen.
+ * config/rs6000/rs6000.cc (rs6000_file_start): Add macros for fake lagen
+ and plagen instructions.
+ (rs6000_opt_masks): Add -mlagen.
+ * config/rs6000/rs6000.md (lagendi3): New insn for -mlagen.
+ (plagendi3_nora): Likewise.
+ (plagendi3): Likewise.
+ (plagendi3_noshift): Likewise.
+ * config/rs6000/rs6000.opt (-mlagen): New option.
+
==================== Dmf002, patch004.
Add support for 1,024 bit DMR registers.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/dmf002)] Update ChangeLog.meissner.
@ 2022-10-27 4:07 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2022-10-27 4:07 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8b7d87db840eb121697eb75b2f156627d47c7bbb
commit 8b7d87db840eb121697eb75b2f156627d47c7bbb
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 27 00:06:52 2022 -0400
Update ChangeLog.meissner.
2022-10-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index a34e7c9446b..c515dc53d7e 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,37 @@
+==================== Dmf002, patch003.
+
+Switch to dense math names for all MMA operations.
+
+2022-10-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/mma.md (vvi4i4i8_dm): New int attribute.
+ (avvi4i4i8_dm): Likewise.
+ (vvi4i4i2_dm): Likewise.
+ (avvi4i4i2_dm): Likewise.
+ (vvi4i4_dm): Likewise.
+ (avvi4i4_dm): Likewise.
+ (pvi4i2_dm): Likewise.
+ (apvi4i2_dm): Likewise.
+ (vvi4i4i4_dm): Likewise.
+ (avvi4i4i4_dm): Likewise.
+ (mma_<vv>): Add support for running on DMF systems, generating the dense
+ math instruction and using the dense math accumulator.
+ (mma_<avv>): Likewise.
+ (mma_<pv>): Likewise.
+ (mma_<apv>): Likewise.
+ (mma_<vvi4i4i8>): Likewise.
+ (mma_<avvi4i4i8>): Likewise.
+ (mma_<vvi4i4i2>): Likewise.
+ (mma_<avvi4i4i2>): Likewise.
+ (mma_<vvi4i4>): Likewise.
+ (mma_<avvi4i4): Likewise.
+ (mma_<pvi4i2>): Likewise.
+ (mma_<apvi4i2): Likewise.
+ (mma_<vvi4i4i4>): Likewise.
+ (mma_<avvi4i4i4>): Likewise.
+
==================== Dmf002, patch002.
Add support for accumulators in DMR registers.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/dmf002)] Update ChangeLog.meissner.
@ 2022-10-27 4:00 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2022-10-27 4:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d2565968c6b33085aa7ad67871977a71be41e1be
commit d2565968c6b33085aa7ad67871977a71be41e1be
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 27 00:00:20 2022 -0400
Update ChangeLog.meissner.
2022-10-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index d6d53f6ac60..a34e7c9446b 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,88 @@
+==================== Dmf002, patch002.
+
+Add support for accumulators in DMR registers.
+
+2022-10-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/constraints.md (wD constraint): New constraint.
+ * config/rs6000/mma.md (UNSPEC_DM_ASSEMBLE_ACC): New unspec.
+ (movxo): Convert into define_expand.
+ (movxo_p10): Power10 version of movxo.
+ (movxo_dm): Dense math version of movxo.
+ (mma_assemble_acc): Add dense match support to define_expand.
+ (mma_assemble_acc_p10): Rename from mma_assemble_acc, and restrict it to
+ non dense math.
+ (mma_assemble_acc_dm): Dense math version of mma_assemble_acc.
+ (mma_disassemble_acc): Add dense math support to define_expand.
+ (mma_disassemble_acc_p10): Rename from mma_disassemble_acc, and restrict
+ it to non dense math.
+ (mma_disassemble_acc_dm): Dense math version of mma_disassemble_acc.
+ (mma_<acc>): New define_expand to handle mma_<acc> for dense math and
+ non dense math.
+ (mma_<acc> insn): Restrict to non dense math.
+ (mma_xxsetaccz): Convert to define_expand to handle non dense math and
+ dense math.
+ (mma_xxsetaccz_p10): Rename from mma_xxsetaccz and restrict usage to non
+ dense math.
+ (mma_xxsetaccz_dm): Dense math version of mma_xxsetaccz.
+ (mma_<vv>): Add support for dense math.
+ (mma_<avv>): Likewise.
+ (mma_<pv>): Likewise.
+ (mma_<apv>): Likewise.
+ (mma_<vvi4i4i8>): Likewise.
+ (mma_<avvi4i4i8>): Likewise.
+ (mma_<vvi4i4i2>): Likewise.
+ (mma_<avvi4i4i2>): Likewise.
+ (mma_<vvi4i4>): Likewise.
+ (mma_<avvi4i4>): Likewise.
+ (mma_<pvi4i2>): Likewise.
+ (mma_<apvi4i2>): Likewise.
+ (mma_<vvi4i4i4>): Likewise.
+ (mma_<avvi4i4i4>): Likewise.
+ * config/rs6000/predicates.md (dmr_operand): New predicate.
+ (accumulator_operand): Likewise.
+ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add -mdense-math.
+ (POWERPC_MASKS): Likewise.
+ * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE.
+ (enum rs6000_reload_reg_type): Add RELOAD_REG_DMR.
+ (LAST_RELOAD_REG_CLASS): Add support for DMR registers.
+ (reload_reg_map): Likewise.
+ (rs6000_reg_names): Likewise.
+ (alt_reg_names): Likewise.
+ (rs6000_hard_regno_nregs_internal): Likewise.
+ (rs6000_hard_regno_mode_ok_uncached): Likewise.
+ (rs6000_debug_reg_global): Likewise.
+ (rs6000_setup_reg_addr_masks): Likewise.
+ (rs6000_init_hard_regno_mode_ok): Likewise.
+ (rs6000_option_override_internal): Add checking for -mdense-math.
+ (rs6000_secondary_reload_memory): Add support for DMR registers.
+ (rs6000_secondary_reload_simple_move): Likewise.
+ (rs6000_preferred_reload_class): Likewise.
+ (rs6000_secondary_reload_class): Likewise.
+ (print_operand): Make %A handle both FPRs and DMRs.
+ (rs6000_dmr_register_move_cost): New helper function.
+ (rs6000_register_move_cost): Add support for DMR registers.
+ (rs6000_memory_move_cost): Likewise.
+ (rs6000_compute_pressure_classes): Likewise.
+ (rs6000_debugger_regno): Likewise.
+ (rs6000_opt_masks): Add -mdense-math.
+ (rs6000_split_multireg_move): Add support for DMRs.
+ * config/rs6000/rs6000.h (UNITS_PER_DMR_WORD): New macro.
+ (FIRST_PSEUDO_REGISTER): Update for DMRs.
+ (FIXED_REGISTERS): Add DMRs.
+ (CALL_REALLY_USED_REGISTERS): Likewise.
+ (REG_ALLOC_ORDER): Likewise.
+ (enum reg_class): Add DM_REGS.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Likewise.
+ * config/rs6000/rs6000.md (FIRST_DMR_REGNO): New constant.
+ (LAST_DMR_REGNO): Likewise.
+ (isa attribute): Add 'dm' and 'not_dm' attributes.
+ (enabled attribute): Support 'dm' and 'not_dm' attributes.
+ * config/rs6000/rs6000.opt (-mdense-math): New switch.
+
==================== Dmf002, patch001.
Add -mcpu=future.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/dmf002)] Update ChangeLog.meissner.
@ 2022-10-26 20:58 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2022-10-26 20:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0817e0466abd7da9997ae0e36e9102904c71ddba
commit 0817e0466abd7da9997ae0e36e9102904c71ddba
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 26 16:57:56 2022 -0400
Update ChangeLog.meissner.
2022-10-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4639387ed0b..d6d53f6ac60 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,29 @@
+==================== Dmf002, patch001.
+
+Add -mcpu=future.
+
+2022-10-26 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/
+
+ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro.
+ (POWERPC_MASKS): Add -mblock-ops-vector-pair.
+ * config/rs6000/rs6000-opts.h (enum processor_type): Add
+ PROCESSOR_FUTURE.
+ * config/rs6000/rs6000-tables.opt: Regenerate.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
+ -mcpu=future support.
+ (rs6000_machine_from_flags): Likewise.
+ (rs6000_adjust_cost): Likewise.
+ (rs6000_issue_rate): Likewise.
+ (rs6000_sched_reorder): Likewise.
+ (rs6000_sched_reorder2): Likewise.
+ (rs6000_register_move_cost): Likewise.
+ * config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise.
+ * config/rs6000/rs6000.md (cpu attribute): Likewise.
+
+==================== Dmf002, initial branch.
+
2022-10-26 Michael Meissner <meissner@linux.ibm.com>
Clone branch
^ permalink raw reply [flat|nested] 6+ messages in thread
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