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* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-06-02 14:45 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-06-02 14:45 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1542a6653d3961b658bd9baeb16f30d2892a3f10
commit 1542a6653d3961b658bd9baeb16f30d2892a3f10
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Jun 2 10:45:27 2023 -0400
Revert patches
Diff:
---
gcc/ChangeLog.meissner | 28 +-------
gcc/config/rs6000/altivec.md | 51 --------------
gcc/config/rs6000/predicates.md | 63 -----------------
gcc/testsuite/gcc.target/powerpc/pr89213.c | 107 -----------------------------
4 files changed, 1 insertion(+), 248 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4d9fec8a92f..a72fff69d53 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,30 +1,4 @@
-==================== Branch work121, patch #40 ====================
-
-PR target/89213 - Optimize vector shift by a constant.
-
-On power9 and power10 systems, optimize vector shifts by a constant, taking
-advantage that the shift instructions only look at the bits within the element.
-
-2023-06-02 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- PR target/89213
- * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec.
- (VSHIFT_MODE): New mode iterator.
- (vshift_code): New code iterator.
- (vshift_attr): New code attribute.
- (altivec_<mode>_<vshift_attr>_const): New pattern to optimize
- vector long long/int shifts by a constant.
- (altivec_<mode>_shift_const): New helper insn to load up a
- constant used by the shift operation.
- * config/rs6000/predicates.md (vector_shift_constant): New
- predicate.
-
-gcc/testsuite/
-
- PR target/89213
- * gcc.target/powerpc/pr89213.c: New test.
+==================== Branch work121, patch #40 was reverted ====================
==================== Branch work121, patch #37 ====================
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index e9f432d4812..ad1224e0b57 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -171,7 +171,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_VECTOR_SHIFT
])
(define_c_enum "unspecv"
@@ -2078,56 +2077,6 @@
"vsro %0,%1,%2"
[(set_attr "type" "vecperm")])
-;; Optimize V2DI shifts by constants. This relies on the shift instructions
-;; only looking at the bits needed to do the shift. This means we can use
-;; VSPLTISW or XXSPLTIB to load up the constant, and not worry about the bits
-;; that the vector shift instructions will not use.
-(define_mode_iterator VSHIFT_MODE [(V4SI "TARGET_P9_VECTOR")
- (V2DI "TARGET_P8_VECTOR")])
-
-(define_code_iterator vshift_code [ashift ashiftrt lshiftrt])
-(define_code_attr vshift_attr [(ashift "ashift")
- (ashiftrt "ashiftrt")
- (lshiftrt "lshiftrt")])
-
-(define_insn_and_split "*altivec_<mode>_<vshift_attr>_const"
- [(set (match_operand:VSHIFT_MODE 0 "register_operand" "=v")
- (vshift_code:VSHIFT_MODE
- (match_operand:VSHIFT_MODE 1 "register_operand" "v")
- (match_operand:VSHIFT_MODE 2 "vector_shift_constant" "")))
- (clobber (match_scratch:VSHIFT_MODE 3 "=&v"))]
- "((<MODE>mode == V2DImode && TARGET_P8_VECTOR)
- || (<MODE>mode == V4SImode && TARGET_P9_VECTOR))"
- "#"
- "&& 1"
- [(set (match_dup 3)
- (unspec:VSHIFT_MODE [(match_dup 4)] UNSPEC_VECTOR_SHIFT))
- (set (match_dup 0)
- (vshift_code:VSHIFT_MODE (match_dup 1)
- (match_dup 3)))]
-{
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (<MODE>mode);
-
- operands[4] = ((GET_CODE (operands[2]) == CONST_VECTOR)
- ? CONST_VECTOR_ELT (operands[2], 0)
- : XEXP (operands[2], 0));
-})
-
-(define_insn "*altivec_<mode>_shift_const"
- [(set (match_operand:VSHIFT_MODE 0 "register_operand" "=v")
- (unspec:VSHIFT_MODE [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_VECTOR_SHIFT))]
- "TARGET_P8_VECTOR"
-{
- if (UINTVAL (operands[1]) <= 15)
- return "vspltisw %0,%1";
- else if (TARGET_P9_VECTOR)
- return "xxspltib %x0,%1";
- else
- gcc_unreachable ();
-})
-
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index f1e93453c18..a16ee30f0c0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -850,69 +850,6 @@
return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
})
-;; Return 1 if the operand is a V2DI or V4SI const_vector, where each element
-;; is the same constant, and the constant can be used for a shift operation.
-;; This is to prevent sub-optimal code, that needs to load up the constant and
-;; then zero extend it 32 or 64-bit vectors or load up the constant from the
-;; literal pool.
-;;
-;; For V4SImode, we only recognize shifts by 16..31 on ISA 3.0, since shifts by
-;; 1..15 can be handled by the normal VSPLTISW and vector shift instruction.
-;; For V2DImode, we do this all of the time, since there is no convenient
-;; instruction to load up a vector long long splatted constant.
-;;
-;; If we can use XXSPLTIB, then allow constants up to 63. If not, we restrict
-;; the constant to 0..15 that can be loaded with VSPLTISW. V4SI shifts are
-;; only optimized for ISA 3.0 when the shift value is >= 16 and <= 31. Values
-;; between 0 and 15 can use a normal VSPLTISW to load the value, and it doesn't
-;; need this optimization.
-(define_predicate "vector_shift_constant"
- (match_code "const_vector,vec_duplicate")
-{
- unsigned HOST_WIDE_INT min_value;
-
- if (mode == V2DImode)
- {
- min_value = 0;
- if (!TARGET_P8_VECTOR)
- return 0;
- }
- else if (mode == V4SImode)
- {
- min_value = 16;
- if (!TARGET_P9_VECTOR)
- return 0;
- }
- else
- return 0;
-
- unsigned HOST_WIDE_INT max_value = TARGET_P9_VECTOR ? 63 : 15;
-
- if (GET_CODE (op) == CONST_VECTOR)
- {
- unsigned HOST_WIDE_INT first = UINTVAL (CONST_VECTOR_ELT (op, 0));
- unsigned nunits = GET_MODE_NUNITS (mode);
- unsigned i;
-
- if (!IN_RANGE (first, min_value, max_value))
- return 0;
-
- for (i = 1; i < nunits; i++)
- if (first != UINTVAL (CONST_VECTOR_ELT (op, i)))
- return 0;
-
- return 1;
- }
- else
- {
- rtx op0 = XEXP (op, 0);
- if (!CONST_INT_P (op0))
- return 0;
-
- return IN_RANGE (UINTVAL (op0), min_value, max_value);
- }
-})
-
;; Return 1 if operand is 0.0.
(define_predicate "zero_fp_constant"
(and (match_code "const_double")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr89213.c b/gcc/testsuite/gcc.target/powerpc/pr89213.c
deleted file mode 100644
index 601f9166d6e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr89213.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2" } */
-
-/* Optimize vector shifts by constants. */
-
-#include <altivec.h>
-
-typedef vector long long vi64_t;
-typedef vector unsigned long long vui64_t;
-
-typedef vector int vi32_t;
-typedef vector unsigned int vui32_t;
-
-vi64_t
-shiftra_test64_4 (vi64_t a)
-{
- vui64_t x = {4, 4};
- return (vi64_t) vec_vsrad (a, x);
-}
-
-vi64_t
-shiftrl_test64_4 (vi64_t a)
-{
- vui64_t x = {4, 4};
- return (vi64_t) vec_vsrd (a, x);
-}
-
-vi64_t
-shiftl_test64_4 (vi64_t a)
-{
- vui64_t x = {4, 4};
- return (vi64_t) vec_vsld (a, x);
-}
-
-vi64_t
-shiftra_test64_29 (vi64_t a)
-{
- vui64_t x = {29, 29};
- return (vi64_t) vec_vsrad (a, x);
-}
-
-vi64_t
-shiftrl_test64_29 (vi64_t a)
-{
- vui64_t x = {29, 29};
- return (vi64_t) vec_vsrd (a, x);
-}
-
-vi64_t
-shiftl_test64_29 (vi64_t a)
-{
- vui64_t x = {29, 29};
- return (vi64_t) vec_vsld (a, x);
-}
-
-vi32_t
-shiftra_test32_4 (vi32_t a)
-{
- vui32_t x = {4, 4, 4, 4};
- return (vi32_t) vec_vsraw (a, x);
-}
-
-vi32_t
-shiftrl_test32_4 (vi32_t a)
-{
- vui32_t x = {4, 4, 4, 4};
- return (vi32_t) vec_vsrw (a, x);
-}
-
-vi32_t
-shiftl_test32_4 (vi32_t a)
-{
- vui32_t x = {4, 4, 4, 4};
- return (vi32_t) vec_vslw (a, x);
-}
-
-vi32_t
-shiftra_test32_29 (vi32_t a)
-{
- vui32_t x = {29, 29, 29, 29};
- return (vi32_t) vec_vsraw (a, x);
-}
-
-vi32_t
-shiftrl_test32_29 (vi32_t a)
-{
- vui32_t x = {29, 29, 29, 29};
- return (vi32_t) vec_vsrw (a, x);
-}
-
-vi32_t
-shiftl_test32_29 (vi32_t a)
-{
- vui32_t x = {29, 29, 29, 29};
- return (vi32_t) vec_vslw (a, x);
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mvsld\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mvsrd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsrw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsrad\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsraw\M} 2 } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-06-03 4:03 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-06-03 4:03 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:389ffe9d483a4871bc57b7978ac8db42b651d73a
commit 389ffe9d483a4871bc57b7978ac8db42b651d73a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sat Jun 3 00:03:06 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/altivec.md | 53 --------------
gcc/config/rs6000/predicates.md | 56 ---------------
gcc/testsuite/gcc.target/powerpc/pr89213.c | 107 -----------------------------
3 files changed, 216 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index e982d968e3b..ad1224e0b57 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -171,7 +171,6 @@
UNSPEC_VSTRIL
UNSPEC_SLDB
UNSPEC_SRDB
- UNSPEC_VECTOR_SHIFT
])
(define_c_enum "unspecv"
@@ -240,10 +239,6 @@
;; Vector negate
(define_mode_iterator VNEG [V4SI V2DI])
-;; Vector shift by constant vector optimizations
-(define_mode_iterator V4SI_V2DI [V4SI V2DI])
-(define_code_iterator vshift_code [ashift ashiftrt lshiftrt])
-
;; Vector move instructions.
(define_insn "*altivec_mov<mode>"
[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,?Y,?*r,?*r,v,v,?*r")
@@ -2082,54 +2077,6 @@
"vsro %0,%1,%2"
[(set_attr "type" "vecperm")])
-;; Optimize V2DI/V4SI shifts by constants. We don't have a VSPLTISD or
-;; VSPLTISW instruction, but we can use XXSPLITB to load constants that would
-;; be used by shifts. The shift instructions only looking at the bits needed
-;; to do the shift.
-
-(define_insn_and_split "*altivec_<code>_const_<mode>"
- [(set (match_operand:V4SI_V2DI 0 "register_operand" "=v")
- (vshift_code:V4SI_V2DI
- (match_operand:V4SI_V2DI 1 "register_operand" "v")
- (match_operand:V4SI_V2DI 2 "vector_shift_constant" "")))
- (clobber (match_scratch:V4SI_V2DI 3 "=&v"))]
- "TARGET_P8_VECTOR"
- "#"
- "&& 1"
- [(set (match_dup 3)
- (unspec:V4SI_V2DI [(match_dup 4)] UNSPEC_VECTOR_SHIFT))
- (set (match_dup 0)
- (vshift_code:V4SI_V2DI (match_dup 1)
- (match_dup 3)))]
-{
- rtx vec_const = operands[2];
-
- if (GET_CODE (operands[3]) == SCRATCH)
- operands[3] = gen_reg_rtx (<MODE>mode);
-
- if (GET_CODE (vec_const) == CONST_VECTOR)
- operands[4] = CONST_VECTOR_ELT (vec_const, 0);
-
- else if (GET_CODE (vec_const) == VEC_DUPLICATE)
- operands[4] = XEXP (vec_const, 0);
-
- else
- gcc_unreachable ();
-})
-
-(define_insn "*altivec_shift_const_<mode>"
- [(set (match_operand:V4SI_V2DI 0 "register_operand" "=v")
- (unspec:V4SI_V2DI [(match_operand 1 "const_int_operand" "n")]
- UNSPEC_VECTOR_SHIFT))]
- "(TARGET_P8_VECTOR && UINTVAL (operands[1]) <= 15)
- || (TARGET_P9_VECTOR && UINTVAL (operands[1]) <= 63)"
-{
- return (UINTVAL (operands[1]) <= 15
- ? "vspltisw %0,%1"
- : "xxspltib %x0,%1");
-}
- [(set_attr "type" "vecperm")])
-
(define_insn "altivec_vsum4ubs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index ad1d64fbe48..a16ee30f0c0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -850,62 +850,6 @@
return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
})
-;; Return 1 if the operand is a V2DI or V4SI const_vector, where each element
-;; is the same constant, and the constant can be used for a shift operation.
-;; This is to prevent sub-optimal code, that needs to load up the constant and
-;; then zero extend it 32 or 64-bit vectors or load up the constant from the
-;; literal pool.
-;;
-;; For V4SImode, we only recognize shifts by 16..31 on ISA 3.0, since shifts by
-;; 1..15 can be handled by the normal VSPLTISW and vector shift instruction.
-;; For V2DImode, we do this all of the time, since there is no convenient
-;; instruction to load up a vector long long splatted constant.
-;;
-;; If we can use XXSPLTIB, then allow constants up to 63. If not, we restrict
-;; the constant to 0..15 that can be loaded with VSPLTISW. V4SI shifts are
-;; only optimized for ISA 3.0 when the shift value is >= 16 and <= 31. Values
-;; between 0 and 15 can use a normal VSPLTISW to load the value, and it doesn't
-;; need this optimization.
-(define_predicate "vector_shift_constant"
- (match_code "const_vector,vec_duplicate")
-{
- unsigned HOST_WIDE_INT min_value;
-
- if (mode == V2DImode)
- min_value = 0;
- else if (mode == V4SImode)
- {
- min_value = 16;
- if (!TARGET_P9_VECTOR)
- return 0;
- }
- else
- return 0;
-
- unsigned HOST_WIDE_INT max_value = TARGET_P9_VECTOR ? 63 : 15;
-
- if (GET_CODE (op) == CONST_VECTOR)
- {
- rtx first = CONST_VECTOR_ELT (op, 0);
- unsigned nunits = GET_MODE_NUNITS (mode);
-
- if (!IN_RANGE (UINTVAL (first), min_value, max_value))
- return 0;
-
- for (unsigned i = 1; i < nunits; i++)
- if (!rtx_equal_p (first, CONST_VECTOR_ELT (op, i)))
- return 0;
-
- return 1;
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE
- && CONST_INT_P (XEXP (op, 0)))
- return IN_RANGE (UINTVAL (XEXP (op, 0)), min_value, max_value);
-
- return 0;
-})
-
;; Return 1 if operand is 0.0.
(define_predicate "zero_fp_constant"
(and (match_code "const_double")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr89213.c b/gcc/testsuite/gcc.target/powerpc/pr89213.c
deleted file mode 100644
index 601f9166d6e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr89213.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9 -O2" } */
-
-/* Optimize vector shifts by constants. */
-
-#include <altivec.h>
-
-typedef vector long long vi64_t;
-typedef vector unsigned long long vui64_t;
-
-typedef vector int vi32_t;
-typedef vector unsigned int vui32_t;
-
-vi64_t
-shiftra_test64_4 (vi64_t a)
-{
- vui64_t x = {4, 4};
- return (vi64_t) vec_vsrad (a, x);
-}
-
-vi64_t
-shiftrl_test64_4 (vi64_t a)
-{
- vui64_t x = {4, 4};
- return (vi64_t) vec_vsrd (a, x);
-}
-
-vi64_t
-shiftl_test64_4 (vi64_t a)
-{
- vui64_t x = {4, 4};
- return (vi64_t) vec_vsld (a, x);
-}
-
-vi64_t
-shiftra_test64_29 (vi64_t a)
-{
- vui64_t x = {29, 29};
- return (vi64_t) vec_vsrad (a, x);
-}
-
-vi64_t
-shiftrl_test64_29 (vi64_t a)
-{
- vui64_t x = {29, 29};
- return (vi64_t) vec_vsrd (a, x);
-}
-
-vi64_t
-shiftl_test64_29 (vi64_t a)
-{
- vui64_t x = {29, 29};
- return (vi64_t) vec_vsld (a, x);
-}
-
-vi32_t
-shiftra_test32_4 (vi32_t a)
-{
- vui32_t x = {4, 4, 4, 4};
- return (vi32_t) vec_vsraw (a, x);
-}
-
-vi32_t
-shiftrl_test32_4 (vi32_t a)
-{
- vui32_t x = {4, 4, 4, 4};
- return (vi32_t) vec_vsrw (a, x);
-}
-
-vi32_t
-shiftl_test32_4 (vi32_t a)
-{
- vui32_t x = {4, 4, 4, 4};
- return (vi32_t) vec_vslw (a, x);
-}
-
-vi32_t
-shiftra_test32_29 (vi32_t a)
-{
- vui32_t x = {29, 29, 29, 29};
- return (vi32_t) vec_vsraw (a, x);
-}
-
-vi32_t
-shiftrl_test32_29 (vi32_t a)
-{
- vui32_t x = {29, 29, 29, 29};
- return (vi32_t) vec_vsrw (a, x);
-}
-
-vi32_t
-shiftl_test32_29 (vi32_t a)
-{
- vui32_t x = {29, 29, 29, 29};
- return (vi32_t) vec_vslw (a, x);
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mvsld\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mvsrd\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsrw\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsrad\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvsraw\M} 2 } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-18 4:58 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-18 4:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:31143c77357a0be5b4033426ae3f849313b02724
commit 31143c77357a0be5b4033426ae3f849313b02724
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu May 18 00:58:13 2023 -0400
Revert patches
Diff:
---
| 2 +-
| 3 ++-
| 2 +-
| 3 ++-
| 2 +-
5 files changed, 7 insertions(+), 5 deletions(-)
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
index 68eeeede4b3..4b1d75ee26d 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
@@ -26,7 +26,7 @@
/* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
#include <altivec.h>
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
index 418762e3948..3729a1646e9 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
@@ -10,7 +10,8 @@
// P7 variables: li, addi, stxvw4x, lwa/lwz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
/* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
index d1e3b62373f..75eaf25943b 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
@@ -30,7 +30,7 @@
/* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
index 46e943faa6a..a495d9f3928 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
@@ -10,7 +10,8 @@
// P7 (be) constants: li, addi, stxvw4x, lha/lhz
/* { dg-final { scan-assembler-times {\mli\M} 6 } } */
-/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
/* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */
/* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */
--git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
index 00685aca136..0ddecb4e4b5 100644
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
@@ -32,7 +32,7 @@
/* add and rlwinm instructions only on the variable tests. */
/* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-15 20:42 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-15 20:42 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d21140ed2955e15d852a5dbd474f51663e719a62
commit d21140ed2955e15d852a5dbd474f51663e719a62
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 15 16:41:57 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/rs6000.md | 3 -
gcc/config/rs6000/vsx.md | 102 ---------------------
| 41 ---------
| 40 --------
| 40 --------
| 41 ---------
6 files changed, 267 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 9354fe183e7..ec783803820 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -664,9 +664,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr fp_int_extend [(float "sign_extend")
- (unsigned_float "zero_extend")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 83c64ea36c5..77316e048f2 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4105,56 +4105,6 @@
(set_attr "length" "*, *, 8, *, 8")
(set_attr "isa" "*, *, *, p9v, p9v")])
-;; Fold extracting a V4SI element with a constant element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (any_float:SFDF
- (vec_select:SI
- (match_operand:V4SI 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=wa,wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Fold extracting a V8HI/V16QI element with a constant element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
- (unsigned_float:SFDF
- (vec_select:<VSX_EXTRACT_I2:VEC_base>
- (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Z,Q")
- (parallel [(match_operand:QI 2 "const_int_operand" "O,n")]))))
- (clobber (match_scratch:DI 3 "=X,&b"))
- (clobber (match_scratch:DI 4 "=v,v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
;; Fold extracting a V8HI element with a constant element with sign extension
;; to either DImode or SImode.
;; Reg: Element: Addr: need scratch
@@ -4287,58 +4237,6 @@
}
[(set_attr "type" "load")])
-;; Fold extracting a V4SI element with a variable element with either sign or
-;; zero extension to SFmode or DFmode into LFIWAX/LFIWZX and FCFID.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<uns><mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (any_float:SFDF
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=wa"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (<fp_int_extend>:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
-;; Fold extracting a V8HI/V16QI element with a variable element with zero
-;; extension to SFmode or DFmode into LXSIBZX/LXSIHZX and FCFID
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_uns<SFDF:mode>"
- [(set (match_operand:SFDF 0 "register_operand" "=wa")
- (unsigned_float:SFDF
- (unspec:<VSX_EXTRACT_I2:VEC_base>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q")
- (match_operand:DI 2 "register_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))
- (clobber (match_scratch:DI 4 "=v"))]
- "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_P9_VECTOR"
- "#"
- "&& reload_completed"
- [(set (match_dup 4)
- (zero_extend:DI (match_dup 5)))
- (set (match_dup 0)
- (float:SFDF (match_dup 4)))]
-{
- operands[5] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:VEC_base>mode);
-}
- [(set_attr "type" "fpload")
- (set_attr "length" "8")])
-
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
deleted file mode 100644
index a537dfe2350..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- QImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIBZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v16qi_0 (vector unsigned char *p)
-{
- return vec_extract (*p, 0); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v16qi_1 (vector unsigned char *p)
-{
- return vec_extract (*p, 1); /* lxsibzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v16qi_element_0_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 0); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v16qi_element_3_index_4 (vector unsigned char *p)
-{
- return vec_extract (p[4], 3); /* lxsibzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsibzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp} 2 } } */
-/* { dg-final { scan-assembler-not {\mlbzx?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
deleted file mode 100644
index 95805325e9e..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v4si_0 (vector unsigned int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v4si_1 (vector unsigned int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v4si_element_0_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v4si_element_3_index_4 (vector unsigned int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
deleted file mode 100644
index 3cf9bafd4f3..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-5.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- SImode and convert it to signed floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. */
-
-#include <altivec.h>
-
-double
-extract_dbl_sign_v4si_0 (vector int *p)
-{
- return vec_extract (*p, 0); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_sign_v4si_1 (vector int *p)
-{
- return vec_extract (*p, 1); /* lfiwzx/lxsiwzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_sign_v4si_element_0_index_4 (vector int *p)
-{
- return vec_extract (p[4], 0); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_sign_v4si_element_3_index_4 (vector int *p)
-{
- return vec_extract (p[4], 3); /* lfiwzx/lxsiwzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
deleted file mode 100644
index 533a80d3d52..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-4.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- HImode and convert it to unsigned floating point, by loading the value
- directly to a vector register, rather than loading up a GPR and transfering
- the result to a vector register. This tests whether the ISA 3.0 LXSIHZX
- instruction is generated. */
-
-#include <altivec.h>
-
-double
-extract_dbl_uns_v8hi_0 (vector unsigned short *p)
-{
- return vec_extract (*p, 0); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-double
-extract_dbl_uns_v8hi_1 (vector unsigned short *p)
-{
- return vec_extract (*p, 1); /* lxsihzx, fcfid/xscvsxddp. */
-}
-
-float
-extract_flt_uns_v8hi_element_0_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 0); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-float
-extract_flt_uns_v8hi_element_3_index_4 (vector unsigned short *p)
-{
- return vec_extract (p[4], 3); /* lxsihzx, fcfids/xscvsxdsp. */
-}
-
-/* { dg-final { scan-assembler-times {\mlxsihzx\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mfcfid\M|\mxscvsxddp\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mfcfids\M|\mxscvsxdsp\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlh[az]x?\M} } } */
-/* { dg-final { scan-assembler-not {\mmtvsr} } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 23:09 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 23:09 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:79e868a33f8315afdc97590fbf5317fac09a612a
commit 79e868a33f8315afdc97590fbf5317fac09a612a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri May 12 19:09:04 2023 -0400
Revert patches
Diff:
---
gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c | 0
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index e69de29bb2d..00000000000
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 22:54 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 22:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:10ad543da83a1f4819fe431c0e8a5ae5d03b6034
commit 10ad543da83a1f4819fe431c0e8a5ae5d03b6034
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri May 12 18:54:51 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 73 +++-------------------
| 29 ---------
| 0
3 files changed, 7 insertions(+), 95 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 1686c7f335b..2d513784a90 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,33 +3549,12 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-;; 8: GPR 0 any normal address no
-;; 9: GPR 0-3 any offsettable address no
-;; 10: GPR 0-3 any single register yes
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand"
- "=f, f, f, v, v, v, v,
- r, r, r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o,
- m, o, Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "O, n, n, O, n, O, n,
- O, n, n")])))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X,
- X, X, &b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
"&& reload_completed"
@@ -3584,47 +3563,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload,
- load, load, load")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v,
- *, *, *")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand"
- "=f, f, f, v, v, v, v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "=X, X, &b, X, &b, X, X")]))))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..e69de29bb2d
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 21:58 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 21:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:06acc2f6eb825f3825958bd7a0b8bcb65271efb2
commit 06acc2f6eb825f3825958bd7a0b8bcb65271efb2
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri May 12 17:58:38 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 182 ++-------------------
| 29 ----
| 22 ---
| 31 ----
| 19 ---
5 files changed, 15 insertions(+), 268 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b873e600ad2..2d513784a90 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3555,33 +3549,12 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-;; 8: GPR 0 any normal address no
-;; 9: GPR 0-3 any offsettable address no
-;; 10: GPR 0-3 any single register yes
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand"
- "=f, f, f, v, v, v, v,
- r, r, r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o,
- m, o, Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "O, n, n, O, n, O, n,
- O, n, n")])))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X,
- X, X, &b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
"&& reload_completed"
@@ -3590,47 +3563,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload,
- load, load, load")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v,
- *, *, *")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand"
- "=f, f, f, v, v, v, v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "=X, X, &b, X, &b, X, X")]))))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3652,7 +3587,7 @@
;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,r")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
@@ -3667,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -4052,89 +3968,21 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory.
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,wa")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VEC_base>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
-
-;; Variable V4SI extract from memory with sign or zero conversion to DImode.
-(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
- (any_extend:DI
- (unspec:SI
- [(match_operand:V4SI 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (any_extend:DI (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- SImode);
-}
- [(set_attr "type" "load,fpload")])
-
-;; Variable V8HI/V16QI extract from memory with zero conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,wa")
- (zero_extend:GPR
- (unspec:<VSX_EXTRACT_I2:MODE>
- [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (zero_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- <VSX_EXTRACT_I2:MODE>mode);
-}
- [(set_attr "type" "load,fpload")
- (set_attr "isa" "*,p9v")])
-
-;; Variable V8HI extract from memory with sign conversion to either
-;; SImode or DImode.
-(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
- [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
- (sign_extend:GPR
- (unspec:HI
- [(match_operand:V8HI 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (sign_extend:GPR (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
- operands[2], operands[3],
- HImode);
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
}
[(set_attr "type" "load")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 2561aa930b6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
deleted file mode 100644
index f6b027db3bc..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- SImode and fold both zero and sign extension into the load. Both uses
- generate a rldicl to clear the bits in the variable element number, but this
- test verifies that there is no rldicl after the lwzx to do the zero
- extension. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v4si_var (vector int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-unsigned long long
-extract_uns_v4si_var (vector unsigned int *p, size_t n)
-{
- return vec_extract (*p, n); /* lwzx, no extra rldicl. */
-}
-
-/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsw\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
deleted file mode 100644
index a1d3947fabb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-options "-O2 -mvsx" } */
-/* { dg-require-effective-target powerpc_vsx_ok } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- HImode and fold sign extension into the load. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-long long
-extract_sign_v8hi_var (vector short *p, size_t n)
-{
- return vec_extract (*p, n); /* lwax, no extsw. */
-}
-
-/* { dg-final { scan-assembler {\mlhax\M} } } */
-/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
-/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 21:33 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 21:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:27ef909046b398f55b08c0ba93b3ea6984da8d83
commit 27ef909046b398f55b08c0ba93b3ea6984da8d83
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri May 12 17:33:43 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/vsx.md | 178 +++++++++------------
| 29 ----
| 22 ---
| 31 ++++
| 19 +++
5 files changed, 129 insertions(+), 150 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2809dc6b011..fe19b35dbbe 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,12 +223,6 @@
(V8HI "v")
(V4SI "wa")])
-;; Mode attribute to give the isa constraint for accessing Altivec registers
-;; with vector extract and insert operations.
-(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
- (V8HI "p9v")
- (V4SI "p8v")])
-
;; Mode iterator for binary floating types other than double to
;; optimize convert to that floating point type from an extract
;; of an integer type
@@ -3555,33 +3549,12 @@
[(set_attr "length" "8")
(set_attr "type" "fp")])
-;; V4SF extract from memory with constant element number.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-;; 8: GPR 0 any normal address no
-;; 9: GPR 0-3 any offsettable address no
-;; 10: GPR 0-3 any single register yes
(define_insn_and_split "*vsx_extract_v4sf_load"
- [(set (match_operand:SF 0 "register_operand"
- "=f, f, f, v, v, v, v,
- r, r, r")
+ [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
(vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o,
- m, o, Q")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "O, n, n, O, n, O, n,
- O, n, n")])))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X,
- X, X, &b"))]
+ (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
+ (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode)"
"#"
"&& reload_completed"
@@ -3590,47 +3563,9 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload,
- load, load, load")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v,
- *, *, *")])
-
-;; V4SF extract from memory with constant element number and convert to DFmode.
-;; Alternatives:
-;; Reg: Ele: Cpu: Addr: need scratch
-;; 1: FPR 0 any normal address no
-;; 2: FPR 1-3 any offsettable address no
-;; 3: FPR 1-3 any single register yes
-;; 4: VMX 0 p8 reg+reg or reg no
-;; 5: VMX 1-3 p8 single register yes
-;; 6: VMX 0 p9 normal address no
-;; 7: VMX 1-3 p9 offsettable address no
-(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
- [(set (match_operand:DF 0 "register_operand"
- "=f, f, f, v, v, v, v")
- (float_extend:DF
- (vec_select:SF
- (match_operand:V4SF 1 "memory_operand"
- "m, o, Q, Z, Q, m, o")
- (parallel [(match_operand:QI 2 "const_0_to_3_operand"
- "=X, X, &b, X, &b, X, X")]))))
- (clobber (match_scratch:P 3
- "=X, X, &b, X, &b, X, X"))]
- "VECTOR_MEM_VSX_P (V4SFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type"
- "fpload, fpload, fpload, fpload, fpload, fpload, fpload")
- (set_attr "isa"
- "*, *, *, p8v, p8v, p9v, p9v")])
+ [(set_attr "type" "fpload,fpload,fpload,load")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p7v,p9v,*")])
;; Variable V4SF extract from a register
(define_insn_and_split "vsx_extract_v4sf_var"
@@ -3652,7 +3587,7 @@
;; Variable V4SF extract from memory
(define_insn_and_split "*vsx_extract_v4sf_var_load"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,r")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
@@ -3667,25 +3602,6 @@
}
[(set_attr "type" "fpload,load")])
-;; V4SF extract from memory with variable element number and convert to DFmode.
-(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
- [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
- (float_extend:DF
- (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
- (match_operand:DI 2 "gpc_reg_operand" "r")]
- UNSPEC_VSX_EXTRACT)))
- (clobber (match_scratch:DI 3 "=&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
- "#"
- "&& reload_completed"
- [(set (match_dup 0)
- (float_extend:DF (match_dup 4)))]
-{
- operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
- operands[3], SFmode);
-}
- [(set_attr "type" "fpload")])
-
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
@@ -4052,25 +3968,89 @@
}
[(set_attr "isa" "p9v,*")])
-;; Variable V16QI/V8HI/V4SI extract from memory.
+;; Variable V16QI/V8HI/V4SI extract from memory
(define_insn_and_split "*vsx_extract_<mode>_var_load"
- [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,wa")
+ [(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r")
(unspec:<VEC_base>
- [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q,Q")
- (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
+ (clobber (match_scratch:DI 3 "=&b"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 4))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], <VEC_base>mode);
+}
+ [(set_attr "type" "load")])
+
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,wa")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
operands[2], operands[3],
- <VEC_base>mode);
+ <VSX_EXTRACT_I2:MODE>mode);
}
[(set_attr "type" "load,fpload")
- (set_attr "isa" "*,<VSX_EX_ISA>")])
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
deleted file mode 100644
index 4670e261ba8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with constant element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-
-void
-extract_v4sf_gpr_0 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 0);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-void
-extract_v4sf_gpr_1 (vector float *p, float *q)
-{
- float x = vec_extract (*p, 1);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
deleted file mode 100644
index 2561aa930b6..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* { dg-do compile { target lp64 } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
-
-/* Test to verify that the vec_extract with variable element numbers can load
- float elements into a GPR register without doing a LFS/STFS. */
-
-#include <altivec.h>
-#include <stddef.h>
-
-void
-extract_v4sf_gpr_n (vector float *p, float *q, size_t n)
-{
- float x = vec_extract (*p, n);
- __asm__ (" # %0" : "+r" (x)); /* lwz, no lfs/stfs. */
- *q = x;
-}
-
-/* { dg-final { scan-assembler-times {\mlwzx?\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mstw\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlfsx?\M|\mlxsspx?\M} } } */
-/* { dg-final { scan-assembler-not {\mstfsx?\M|\mstxsspx?\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..f6b027db3bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
new file mode 100644
index 00000000000..a1d3947fabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:51 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:63db371696e93cfeb62c72e33e67f420c697a691
commit 63db371696e93cfeb62c72e33e67f420c697a691
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed May 10 11:08:54 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 +-
gcc/config/rs6000/genfusion.pl | 260 ++++++++-------------
gcc/testsuite/g++.target/powerpc/pr105325.C | 26 ---
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 +-
4 files changed, 100 insertions(+), 207 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 836dbd20948..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -45,181 +45,103 @@ print <<'EOF';
EOF
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- Integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- Sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- Memory format ("d" or "ds").
-# cmpl -- Suffix for compare ("l" or "")
-# const_pred -- Predicate for constant (i.e. -1/0/1 or 0/1).
-# extend -- "sign", "zero", or "none".
-# echr -- Suffix for load ("a", "z", or "").
-# load -- Load instruction (i.e. "ld", "lwa", "lwz", etc.)
-# np -- enum non_prefixed_form for memory type
-# constraint -- constraint to use
-# mem_pred -- predicate for the memory operation
-
-sub print_ld_cmpi_p10
+sub mode_to_ldst_char
{
- my ($lmode, $result, $ccmode, $cmpl, $const_pred,
- $extend, $load, $np, $constraint, $mem_pred) = @_;
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^[HQ]I$/) ? "GPR" : $lmode;
-
- # Break long print statements into smaller lines.
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- my $name = join ("",
- "${load}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mem_pred}\" \"${constraint}\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
- print ";; ${info}\n";
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- # Do not match prefixed loads. The machine only fuses non-prefixed loads
- # with compare immediate. Take into account whether the load is a ds-form
- # or a d-form instruction.
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"${load}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign")
- {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
+ my ($mode) = @_;
+ my %x = (DI => 'd', SI => 'w', HI => 'h', QI => 'b');
+ return $x{$mode} if exists $x{$mode};
+ return '?';
}
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mem_format, $extend);
-
- # Map mode to load instruction
- my %signed_load = ("DI" => "ld",
- "SI" => "lwa",
- "HI" => "lha");
-
- my %unsigned_load = ("DI" => "ld",
- "SI" => "lwz",
- "HI" => "lhz",
- "QI" => "lbz");
-
- # Memory predicate to use. For LWA, use the special LWA_OPERAND.
- my %signed_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "lwa_operand",
- "HI" => "non_update_memory_operand");
-
- my %unsigned_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "non_update_memory_operand",
- "HI" => "non_update_memory_operand",
- "QI" => "non_update_memory_operand");
-
- # Internal format of the memory instruction (enum non_prefixed_form) to use.
- my %np = ("ds" => "NON_PREFIXED_DS",
- "d" => "NON_PREFIXED_D");
-
- # Constraint to use.
- my %constraint = ("ds" => "YZ",
- "d" => "m");
-
- # Result modes to use. Clobber is used when you are comparing the load to
- # -1/0/1, but you are not using it otherwise. EXTDI does not exist. We
- # cannot directly use HI/QI results because we only have word and double word
- # compared. For promotion, don't allow EXTQI because that would allow HI
- # results which we can't do (use GPR instead).
- my %result_modes = ("DI" => ["clobber", "DI"],
- "SI" => ["clobber", "SI", "EXTSI" ],
- "HI" => ["clobber", "EXTHI" ],
- "QI" => ["clobber", "GPR" ]);
-
- foreach $lmode ("DI", "SI", "HI", "QI")
- {
- foreach $result (@{ $result_modes{$lmode} })
- {
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't
- # have a LBA instruction, so skip QImode. Both LD and LWA are
- # DS-form instructions for signed loads.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^[DS]I$/) ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "sign");
-
- print_ld_cmpi_p10 ($lmode, $result, "CC", "",
- "const_m1_to_1_operand", $extend,
- $signed_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $signed_memory_predicate{$lmode});
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # LD is DS-form, but LWZ is not for unsigned loads.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "zero");
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", "l",
- "const_0_to_1_operand", $extend,
- $unsigned_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $unsigned_memory_predicate{$lmode});
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index d0e66a0b897..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. The -fstack-protector option is needed to show the
- bug. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:51 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:91dbe5f7e15bf4e666d825d3eb769ddc210b4c1a
commit 91dbe5f7e15bf4e666d825d3eb769ddc210b4c1a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 9 16:33:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 +-
gcc/config/rs6000/genfusion.pl | 260 ++++++++-------------
gcc/testsuite/g++.target/powerpc/pr105325.C | 26 ---
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 +-
4 files changed, 100 insertions(+), 207 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 836dbd20948..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -45,181 +45,103 @@ print <<'EOF';
EOF
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- Integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- Sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- Memory format ("d" or "ds").
-# cmpl -- Suffix for compare ("l" or "")
-# const_pred -- Predicate for constant (i.e. -1/0/1 or 0/1).
-# extend -- "sign", "zero", or "none".
-# echr -- Suffix for load ("a", "z", or "").
-# load -- Load instruction (i.e. "ld", "lwa", "lwz", etc.)
-# np -- enum non_prefixed_form for memory type
-# constraint -- constraint to use
-# mem_pred -- predicate for the memory operation
-
-sub print_ld_cmpi_p10
+sub mode_to_ldst_char
{
- my ($lmode, $result, $ccmode, $cmpl, $const_pred,
- $extend, $load, $np, $constraint, $mem_pred) = @_;
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^[HQ]I$/) ? "GPR" : $lmode;
-
- # Break long print statements into smaller lines.
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- my $name = join ("",
- "${load}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mem_pred}\" \"${constraint}\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
- print ";; ${info}\n";
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- # Do not match prefixed loads. The machine only fuses non-prefixed loads
- # with compare immediate. Take into account whether the load is a ds-form
- # or a d-form instruction.
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"${load}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign")
- {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
+ my ($mode) = @_;
+ my %x = (DI => 'd', SI => 'w', HI => 'h', QI => 'b');
+ return $x{$mode} if exists $x{$mode};
+ return '?';
}
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mem_format, $extend);
-
- # Map mode to load instruction
- my %signed_load = ("DI" => "ld",
- "SI" => "lwa",
- "HI" => "lha");
-
- my %unsigned_load = ("DI" => "ld",
- "SI" => "lwz",
- "HI" => "lhz",
- "QI" => "lbz");
-
- # Memory predicate to use. For LWA, use the special LWA_OPERAND.
- my %signed_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "lwa_operand",
- "HI" => "non_update_memory_operand");
-
- my %unsigned_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "non_update_memory_operand",
- "HI" => "non_update_memory_operand",
- "QI" => "non_update_memory_operand");
-
- # Internal format of the memory instruction (enum non_prefixed_form) to use.
- my %np = ("ds" => "NON_PREFIXED_DS",
- "d" => "NON_PREFIXED_D");
-
- # Constraint to use.
- my %constraint = ("ds" => "YZ",
- "d" => "m");
-
- # Result modes to use. Clobber is used when you are comparing the load to
- # -1/0/1, but you are not using it otherwise. EXTDI does not exist. We
- # cannot directly use HI/QI results because we only have word and double word
- # compared. For promotion, don't allow EXTQI because that would allow HI
- # results which we can't do (use GPR instead).
- my %result_modes = ("DI" => ["clobber", "DI"],
- "SI" => ["clobber", "SI", "EXTSI" ],
- "HI" => ["clobber", "EXTHI" ],
- "QI" => ["clobber", "GPR" ]);
-
- foreach $lmode ("DI", "SI", "HI", "QI")
- {
- foreach $result (@{ $result_modes{$lmode} })
- {
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't
- # have a LBA instruction, so skip QImode. Both LD and LWA are
- # DS-form instructions for signed loads.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^[DS]I$/) ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "sign");
-
- print_ld_cmpi_p10 ($lmode, $result, "CC", "",
- "const_m1_to_1_operand", $extend,
- $signed_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $signed_memory_predicate{$lmode});
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # LD is DS-form, but LWZ is not for unsigned loads.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "zero");
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", "l",
- "const_0_to_1_operand", $extend,
- $unsigned_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $unsigned_memory_predicate{$lmode});
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index d0e66a0b897..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. The -fstack-protector option is needed to show the
- bug. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:51 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7ee4398d1f9b7edcdb254b245a7507f916c10ced
commit 7ee4398d1f9b7edcdb254b245a7507f916c10ced
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 9 12:28:18 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 ++++++--------
gcc/config/rs6000/genfusion.pl | 17 +++++---------
gcc/testsuite/g++.target/powerpc/pr105325.C | 26 ----------------------
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 ++--
4 files changed, 14 insertions(+), 50 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index ca16ee8576d..de55f224912 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -85,12 +85,11 @@ sub print_ld_cmpi_p10
# DI-mode doesn't do sign/zero extension.
my $echr = ($lmode eq "DI") ? "" : $a_or_z;
- # Handle DS vs. D format memory. Special case using lwa_operand for SImode.
- my $ds_load = ($lmode eq "SI") ? "lwa_operand" : "ds_form_mem_operand";
- my ($np, $constraint, $mempred)
+ # Handle DS vs. D format memory.
+ my ($np, $mempred)
= (($mem_format eq "ds")
- ? ("NON_PREFIXED_DS", "YZ", $ds_load)
- : ("NON_PREFIXED_D", "m", "non_update_memory_operand"));
+ ? ("NON_PREFIXED_DS", "ds_form_mem_operand")
+ : ("NON_PREFIXED_D", "non_update_memory_operand"));
# Break long print statements into smaller lines.
my $info = join (" ",
@@ -101,7 +100,7 @@ sub print_ld_cmpi_p10
"l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
"_${result}_${ccmode}_${extend}");
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"${constraint}\")";
+ my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
my $spaces = " " x (length ($ccmode) + 18);
@@ -149,12 +148,6 @@ sub print_ld_cmpi_p10
print " \"\"\n";
print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign")
- {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
print " (set_attr \"length\" \"8\")])\n";
print "\n";
}
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index d0e66a0b897..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. The -fstack-protector option is needed to show the
- bug. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:50 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5657ef3c2d03a8cdeee359ab40f3beada0949145
commit 5657ef3c2d03a8cdeee359ab40f3beada0949145
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 19:26:08 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 +++++++++++++++++------------------------
1 file changed, 86 insertions(+), 126 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index b053005fa92..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,135 +53,95 @@ sub mode_to_ldst_char
return '?';
}
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- memory format ("d" or "ds").
-
-sub print_ld_cmpi_p10
-{
- my ($lmode, $result, $ccmode, $mem_format) = @_;
-
- my $ldst = mode_to_ldst_char($lmode);
-
- # Set various things based on whether the comparisons are signed or
- # unsigned.
- my ($cmpl, $const_pred, $sign_zero, $a_or_z)
- = (($ccmode eq "CCUNS")
- ? ("l", "const_0_to_1_operand", "zero", "z")
- : ("", "const_m1_to_1_operand", "sign", "a"));
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
-
- # We always need extension if result > lmode.
- my $extend = (($result =~ m/^EXT/
- || $result eq "GPR"
- || $clobbermode eq "GPR") ? $sign_zero : "none");
-
- # DI-mode doesn't do sign/zero extension.
- my $echr = ($lmode eq "DI") ? "" : $a_or_z;
-
- # Handle DS vs. D format memory.
- my ($np, $mempred) = (($mem_format eq "ds")
- ? ("NON_PREFIXED_DS", "ds_form_mem_operand")
- : ("NON_PREFIXED_D", "non_update_memory_operand"));
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- print ";; ${info}\n";
-
- my $name = join ("",
- "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
-}
-
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mempred, $np, $mem_format);
-
- foreach $lmode ("DI","SI", "HI", "QI")
- {
- foreach $result ("clobber", $lmode, "EXT${lmode}")
- {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next if ($result =~ m/^(EXTDI|HI|QI)$/);
-
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if ($result eq "EXTQI");
-
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
- # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
- # instructions.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
- print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # ld is DS-form, but lwz is not.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:50 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a2ebb2efec6227b9dbafe5704d3a59f7ca1fcf9c
commit a2ebb2efec6227b9dbafe5704d3a59f7ca1fcf9c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 19:21:26 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 +++++++++++++++++------------------------
1 file changed, 86 insertions(+), 126 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 84de9ac3542..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,135 +53,95 @@ sub mode_to_ldst_char
return '?';
}
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- memory format ("d" or "ds").
-
-sub print_ld_cmpi_p10
-{
- my ($lmode, $result, $ccmode, $mem_format) = @_;
-
- my $ldst = mode_to_ldst_char($lmode);
-
- # Set various things based on whether the comparisons are signed or
- # unsigned.
- my ($cmpl, $const_pred, $sign_zero, $a_or_z)
- = (($ccmode eq "CCUNS")
- ? ("l", "const_0_to_1_operand", "zero", "z")
- : ("", "const_m1_to_1_operand", "sign", "a"));
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
-
- # We always need extension if result > lmode.
- my $extend = (($result =~ m/^EXT/
- || $result eq "GPR"
- || $clobbermode eq "GPR") ? $sign_zero : "none");
-
- # DI-mode doesn't do sign/zero extension.
- my $echr = ($lmode eq "DI") ? "" : $a_or_z;
-
- # Handle DS vs. D format memory.
- my ($mempred, $np) = (($mem_format eq "ds")
- ? ("ds_form_mem_operand", "NON_PREFIXED_DS")
- : ("non_update_memory_operand", "NON_PREFIXED_D"));
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- print ";; ${info}\n";
-
- my $name = join ("",
- "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
-}
-
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mempred, $np, $mem_format);
-
- foreach $lmode ("DI","SI", "HI", "QI")
- {
- foreach $result ("clobber", $lmode, "EXT${lmode}")
- {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next if ($result =~ m/^(EXTDI|HI|QI)$/);
-
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if ($result eq "EXTQI");
-
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
- # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
- # instructions.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
- print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # ld is DS-form, but lwz is not.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:50 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:51686c6780d3ab8a9bf819ebbd88b364c9e256ec
commit 51686c6780d3ab8a9bf819ebbd88b364c9e256ec
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 19:20:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 ++++++++++++++++++++++++-----------------
1 file changed, 126 insertions(+), 86 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index e4db352e0ce..84de9ac3542 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,95 +53,135 @@ sub mode_to_ldst_char
return '?';
}
+# Print the insns for load and compare with -1/0/1.
+# Arguments:
+# lmode -- integer mode ("DI", "SI", "HI", or "QI").
+# result -- "clobber", "GPR", or $lmode
+# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
+# mem_format -- memory format ("d" or "ds").
+
+sub print_ld_cmpi_p10
+{
+ my ($lmode, $result, $ccmode, $mem_format) = @_;
+
+ my $ldst = mode_to_ldst_char($lmode);
+
+ # Set various things based on whether the comparisons are signed or
+ # unsigned.
+ my ($cmpl, $const_pred, $sign_zero, $a_or_z)
+ = (($ccmode eq "CCUNS")
+ ? ("l", "const_0_to_1_operand", "zero", "z")
+ : ("", "const_m1_to_1_operand", "sign", "a"));
+
+ # For clobber, we need a SI/DI reg in case we split because we have to
+ # sign/zero extend.
+ my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
+
+ # We always need extension if result > lmode.
+ my $extend = (($result =~ m/^EXT/
+ || $result eq "GPR"
+ || $clobbermode eq "GPR") ? $sign_zero : "none");
+
+ # DI-mode doesn't do sign/zero extension.
+ my $echr = ($lmode eq "DI") ? "" : $a_or_z;
+
+ # Handle DS vs. D format memory.
+ my ($mempred, $np) = (($mem_format eq "ds")
+ ? ("ds_form_mem_operand", "NON_PREFIXED_DS")
+ : ("non_update_memory_operand", "NON_PREFIXED_D"));
+
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+
+ my $info = join (" ",
+ "load mode is ${lmode} result mode is ${result}",
+ "compare mode is ${ccmode} extend is ${extend}");
+
+ print ";; ${info}\n";
+
+ my $name = join ("",
+ "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
+ "_${result}_${ccmode}_${extend}");
+
+ my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
+
+ my $spaces = " " x (length ($ccmode) + 18);
+
+ print "(define_insn_and_split \"*${name}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} ${cmp_op1}\n";
+ print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
+
+ if ($result eq "clobber")
+ {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ }
+
+ else
+ {
+ my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
+ my $load_op1 = (($result eq $lmode)
+ ? "(match_dup 1)"
+ : "(${extend}_extend:${result} (match_dup 1))");
+ print " (set ${load_op0} ${load_op1})]\n";
+ }
+
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none")
+ {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ }
+
+ else
+ {
+ my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+}
+
sub gen_ld_cmpi_p10
{
- my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
- $mempred, $ccmode, $np, $extend, $resultmode);
- LMODE: foreach $lmode ('DI','SI','HI','QI') {
- $ldst = mode_to_ldst_char($lmode);
- $clobbermode = $lmode;
- # For clobber, we need a SI/DI reg in case we
- # split because we have to sign/zero extend.
- if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
- RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if $result eq "EXTQI";
- CCMODE: foreach $ccmode ('CC','CCUNS') {
- $np = "NON_PREFIXED_D";
- $mempred = "non_update_memory_operand";
- if ( $ccmode eq 'CC' ) {
- next CCMODE if $lmode eq 'QI';
- if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
- # ld and lwa are both DS-FORM.
- $np = "NON_PREFIXED_DS";
- $mempred = "ds_form_mem_operand";
- }
- $cmpl = "";
- $echr = "a";
- $constpred = "const_m1_to_1_operand";
- } else {
- if ( $lmode eq 'DI' ) {
- # ld is DS-form, but lwz is not.
- $np = "NON_PREFIXED_DS";
- $mempred = "ds_form_mem_operand";
- }
- $cmpl = "l";
- $echr = "z";
- $constpred = "const_0_to_1_operand";
- }
- if ($lmode eq 'DI') { $echr = ""; }
- if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
- # We always need extension if result > lmode.
- if ( $ccmode eq 'CC' ) {
- $extend = "sign";
- } else {
- $extend = "zero";
- }
- } else {
- # Result of SI/DI does not need sign extension.
- $extend = "none";
- }
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
- print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
-
- print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
- if ($ccmode eq 'CCUNS') { print " "; }
- print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
- if ($result eq 'clobber') {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- } elsif ($result eq $lmode) {
- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
- } else {
- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
- }
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none") {
- print " [(set (match_dup 0) (match_dup 1))\n";
- } else {
- $resultmode = $result;
- if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
- }
+ my ($lmode, $result, $mempred, $np, $mem_format);
+
+ foreach $lmode ("DI","SI", "HI", "QI")
+ {
+ foreach $result ("clobber", $lmode, "EXT${lmode}")
+ {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next if ($result =~ m/^(EXTDI|HI|QI)$/);
+
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if ($result eq "EXTQI");
+
+ # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
+ # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
+ # instructions.
+ if ($lmode ne "QI")
+ {
+ $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
+ print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
+ }
+
+ # Handle CCUNS mode (zero extended compares to 0 or 1.
+ # ld is DS-form, but lwz is not.
+ $mem_format = ($lmode eq "DI") ? "ds" : "d";
+
+ print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
+ }
}
- }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-12 16:50 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-12 16:50 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b30522325e5605266229ec36ec2acf99e64abcc3
commit b30522325e5605266229ec36ec2acf99e64abcc3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 18:17:36 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 +++++++++++++++++------------------------
1 file changed, 86 insertions(+), 126 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 84de9ac3542..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,135 +53,95 @@ sub mode_to_ldst_char
return '?';
}
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- memory format ("d" or "ds").
-
-sub print_ld_cmpi_p10
-{
- my ($lmode, $result, $ccmode, $mem_format) = @_;
-
- my $ldst = mode_to_ldst_char($lmode);
-
- # Set various things based on whether the comparisons are signed or
- # unsigned.
- my ($cmpl, $const_pred, $sign_zero, $a_or_z)
- = (($ccmode eq "CCUNS")
- ? ("l", "const_0_to_1_operand", "zero", "z")
- : ("", "const_m1_to_1_operand", "sign", "a"));
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
-
- # We always need extension if result > lmode.
- my $extend = (($result =~ m/^EXT/
- || $result eq "GPR"
- || $clobbermode eq "GPR") ? $sign_zero : "none");
-
- # DI-mode doesn't do sign/zero extension.
- my $echr = ($lmode eq "DI") ? "" : $a_or_z;
-
- # Handle DS vs. D format memory.
- my ($mempred, $np) = (($mem_format eq "ds")
- ? ("ds_form_mem_operand", "NON_PREFIXED_DS")
- : ("non_update_memory_operand", "NON_PREFIXED_D"));
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- print ";; ${info}\n";
-
- my $name = join ("",
- "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
-}
-
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mempred, $np, $mem_format);
-
- foreach $lmode ("DI","SI", "HI", "QI")
- {
- foreach $result ("clobber", $lmode, "EXT${lmode}")
- {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next if ($result =~ m/^(EXTDI|HI|QI)$/);
-
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if ($result eq "EXTQI");
-
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
- # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
- # instructions.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
- print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # ld is DS-form, but lwz is not.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-10 15:08 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-10 15:08 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:91aec80dc765fba6f4f57805c665679f95d667c6
commit 91aec80dc765fba6f4f57805c665679f95d667c6
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed May 10 11:08:54 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 +-
gcc/config/rs6000/genfusion.pl | 260 ++++++++-------------
gcc/testsuite/g++.target/powerpc/pr105325.C | 26 ---
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 +-
4 files changed, 100 insertions(+), 207 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 836dbd20948..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -45,181 +45,103 @@ print <<'EOF';
EOF
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- Integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- Sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- Memory format ("d" or "ds").
-# cmpl -- Suffix for compare ("l" or "")
-# const_pred -- Predicate for constant (i.e. -1/0/1 or 0/1).
-# extend -- "sign", "zero", or "none".
-# echr -- Suffix for load ("a", "z", or "").
-# load -- Load instruction (i.e. "ld", "lwa", "lwz", etc.)
-# np -- enum non_prefixed_form for memory type
-# constraint -- constraint to use
-# mem_pred -- predicate for the memory operation
-
-sub print_ld_cmpi_p10
+sub mode_to_ldst_char
{
- my ($lmode, $result, $ccmode, $cmpl, $const_pred,
- $extend, $load, $np, $constraint, $mem_pred) = @_;
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^[HQ]I$/) ? "GPR" : $lmode;
-
- # Break long print statements into smaller lines.
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- my $name = join ("",
- "${load}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mem_pred}\" \"${constraint}\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
- print ";; ${info}\n";
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- # Do not match prefixed loads. The machine only fuses non-prefixed loads
- # with compare immediate. Take into account whether the load is a ds-form
- # or a d-form instruction.
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"${load}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign")
- {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
+ my ($mode) = @_;
+ my %x = (DI => 'd', SI => 'w', HI => 'h', QI => 'b');
+ return $x{$mode} if exists $x{$mode};
+ return '?';
}
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mem_format, $extend);
-
- # Map mode to load instruction
- my %signed_load = ("DI" => "ld",
- "SI" => "lwa",
- "HI" => "lha");
-
- my %unsigned_load = ("DI" => "ld",
- "SI" => "lwz",
- "HI" => "lhz",
- "QI" => "lbz");
-
- # Memory predicate to use. For LWA, use the special LWA_OPERAND.
- my %signed_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "lwa_operand",
- "HI" => "non_update_memory_operand");
-
- my %unsigned_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "non_update_memory_operand",
- "HI" => "non_update_memory_operand",
- "QI" => "non_update_memory_operand");
-
- # Internal format of the memory instruction (enum non_prefixed_form) to use.
- my %np = ("ds" => "NON_PREFIXED_DS",
- "d" => "NON_PREFIXED_D");
-
- # Constraint to use.
- my %constraint = ("ds" => "YZ",
- "d" => "m");
-
- # Result modes to use. Clobber is used when you are comparing the load to
- # -1/0/1, but you are not using it otherwise. EXTDI does not exist. We
- # cannot directly use HI/QI results because we only have word and double word
- # compared. For promotion, don't allow EXTQI because that would allow HI
- # results which we can't do (use GPR instead).
- my %result_modes = ("DI" => ["clobber", "DI"],
- "SI" => ["clobber", "SI", "EXTSI" ],
- "HI" => ["clobber", "EXTHI" ],
- "QI" => ["clobber", "GPR" ]);
-
- foreach $lmode ("DI", "SI", "HI", "QI")
- {
- foreach $result (@{ $result_modes{$lmode} })
- {
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't
- # have a LBA instruction, so skip QImode. Both LD and LWA are
- # DS-form instructions for signed loads.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^[DS]I$/) ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "sign");
-
- print_ld_cmpi_p10 ($lmode, $result, "CC", "",
- "const_m1_to_1_operand", $extend,
- $signed_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $signed_memory_predicate{$lmode});
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # LD is DS-form, but LWZ is not for unsigned loads.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "zero");
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", "l",
- "const_0_to_1_operand", $extend,
- $unsigned_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $unsigned_memory_predicate{$lmode});
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index d0e66a0b897..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. The -fstack-protector option is needed to show the
- bug. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-09 20:33 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-09 20:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:32fb74a03a34d8c481ccc5713ca328862ff2840b
commit 32fb74a03a34d8c481ccc5713ca328862ff2840b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 9 16:33:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 +-
gcc/config/rs6000/genfusion.pl | 260 ++++++++-------------
gcc/testsuite/g++.target/powerpc/pr105325.C | 26 ---
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 +-
4 files changed, 100 insertions(+), 207 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 836dbd20948..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -45,181 +45,103 @@ print <<'EOF';
EOF
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- Integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- Sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- Memory format ("d" or "ds").
-# cmpl -- Suffix for compare ("l" or "")
-# const_pred -- Predicate for constant (i.e. -1/0/1 or 0/1).
-# extend -- "sign", "zero", or "none".
-# echr -- Suffix for load ("a", "z", or "").
-# load -- Load instruction (i.e. "ld", "lwa", "lwz", etc.)
-# np -- enum non_prefixed_form for memory type
-# constraint -- constraint to use
-# mem_pred -- predicate for the memory operation
-
-sub print_ld_cmpi_p10
+sub mode_to_ldst_char
{
- my ($lmode, $result, $ccmode, $cmpl, $const_pred,
- $extend, $load, $np, $constraint, $mem_pred) = @_;
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^[HQ]I$/) ? "GPR" : $lmode;
-
- # Break long print statements into smaller lines.
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- my $name = join ("",
- "${load}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mem_pred}\" \"${constraint}\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
- print ";; ${info}\n";
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- # Do not match prefixed loads. The machine only fuses non-prefixed loads
- # with compare immediate. Take into account whether the load is a ds-form
- # or a d-form instruction.
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"${load}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign")
- {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
+ my ($mode) = @_;
+ my %x = (DI => 'd', SI => 'w', HI => 'h', QI => 'b');
+ return $x{$mode} if exists $x{$mode};
+ return '?';
}
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mem_format, $extend);
-
- # Map mode to load instruction
- my %signed_load = ("DI" => "ld",
- "SI" => "lwa",
- "HI" => "lha");
-
- my %unsigned_load = ("DI" => "ld",
- "SI" => "lwz",
- "HI" => "lhz",
- "QI" => "lbz");
-
- # Memory predicate to use. For LWA, use the special LWA_OPERAND.
- my %signed_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "lwa_operand",
- "HI" => "non_update_memory_operand");
-
- my %unsigned_memory_predicate = ("DI" => "ds_form_mem_operand",
- "SI" => "non_update_memory_operand",
- "HI" => "non_update_memory_operand",
- "QI" => "non_update_memory_operand");
-
- # Internal format of the memory instruction (enum non_prefixed_form) to use.
- my %np = ("ds" => "NON_PREFIXED_DS",
- "d" => "NON_PREFIXED_D");
-
- # Constraint to use.
- my %constraint = ("ds" => "YZ",
- "d" => "m");
-
- # Result modes to use. Clobber is used when you are comparing the load to
- # -1/0/1, but you are not using it otherwise. EXTDI does not exist. We
- # cannot directly use HI/QI results because we only have word and double word
- # compared. For promotion, don't allow EXTQI because that would allow HI
- # results which we can't do (use GPR instead).
- my %result_modes = ("DI" => ["clobber", "DI"],
- "SI" => ["clobber", "SI", "EXTSI" ],
- "HI" => ["clobber", "EXTHI" ],
- "QI" => ["clobber", "GPR" ]);
-
- foreach $lmode ("DI", "SI", "HI", "QI")
- {
- foreach $result (@{ $result_modes{$lmode} })
- {
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't
- # have a LBA instruction, so skip QImode. Both LD and LWA are
- # DS-form instructions for signed loads.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^[DS]I$/) ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "sign");
-
- print_ld_cmpi_p10 ($lmode, $result, "CC", "",
- "const_m1_to_1_operand", $extend,
- $signed_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $signed_memory_predicate{$lmode});
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # LD is DS-form, but LWZ is not for unsigned loads.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
- $extend = (($lmode eq "DI"
- || $lmode eq $result
- || ($lmode eq "SI" && $result eq "clobber"))
- ? "none"
- : "zero");
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", "l",
- "const_0_to_1_operand", $extend,
- $unsigned_load{$lmode}, $np{$mem_format},
- $constraint{$mem_format},
- $unsigned_memory_predicate{$lmode});
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index d0e66a0b897..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. The -fstack-protector option is needed to show the
- bug. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-09 16:28 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-09 16:28 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:0bdac3f5cf620df86a3e9a0bfd2e2ba655921a68
commit 0bdac3f5cf620df86a3e9a0bfd2e2ba655921a68
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue May 9 12:28:18 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/fusion.md | 17 ++++++--------
gcc/config/rs6000/genfusion.pl | 17 +++++---------
gcc/testsuite/g++.target/powerpc/pr105325.C | 26 ----------------------
.../gcc.target/powerpc/fusion-p10-ldcmpi.c | 4 ++--
4 files changed, 14 insertions(+), 50 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index da9953d9ad9..d45fb138a70 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -22,7 +22,7 @@
;; load mode is DI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -43,7 +43,7 @@
;; load mode is DI result mode is clobber compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -64,7 +64,7 @@
;; load mode is DI result mode is DI compare mode is CC extend is none
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CC (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -85,7 +85,7 @@
;; load mode is DI result mode is DI compare mode is CCUNS extend is none
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
- (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "YZ")
+ (compare:CCUNS (match_operand:DI 1 "ds_form_mem_operand" "m")
(match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -106,7 +106,7 @@
;; load mode is SI result mode is clobber compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION)"
@@ -148,7 +148,7 @@
;; load mode is SI result mode is SI compare mode is CC extend is none
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION)"
@@ -190,7 +190,7 @@
;; load mode is SI result mode is EXTSI compare mode is CC extend is sign
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
- (compare:CC (match_operand:SI 1 "lwa_operand" "YZ")
+ (compare:CC (match_operand:SI 1 "ds_form_mem_operand" "m")
(match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION)"
@@ -205,7 +205,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -248,7 +247,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
@@ -291,7 +289,6 @@
""
[(set_attr "type" "fused_load_cmpi")
(set_attr "cost" "8")
- (set_attr "sign_extend" "yes")
(set_attr "length" "8")])
;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index ca16ee8576d..de55f224912 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -85,12 +85,11 @@ sub print_ld_cmpi_p10
# DI-mode doesn't do sign/zero extension.
my $echr = ($lmode eq "DI") ? "" : $a_or_z;
- # Handle DS vs. D format memory. Special case using lwa_operand for SImode.
- my $ds_load = ($lmode eq "SI") ? "lwa_operand" : "ds_form_mem_operand";
- my ($np, $constraint, $mempred)
+ # Handle DS vs. D format memory.
+ my ($np, $mempred)
= (($mem_format eq "ds")
- ? ("NON_PREFIXED_DS", "YZ", $ds_load)
- : ("NON_PREFIXED_D", "m", "non_update_memory_operand"));
+ ? ("NON_PREFIXED_DS", "ds_form_mem_operand")
+ : ("NON_PREFIXED_D", "non_update_memory_operand"));
# Break long print statements into smaller lines.
my $info = join (" ",
@@ -101,7 +100,7 @@ sub print_ld_cmpi_p10
"l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
"_${result}_${ccmode}_${extend}");
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"${constraint}\")";
+ my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
my $spaces = " " x (length ($ccmode) + 18);
@@ -149,12 +148,6 @@ sub print_ld_cmpi_p10
print " \"\"\n";
print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
print " (set_attr \"cost\" \"8\")\n";
-
- if ($extend eq "sign")
- {
- print " (set_attr \"sign_extend\" \"yes\")\n";
- }
-
print " (set_attr \"length\" \"8\")])\n";
print "\n";
}
diff --git a/gcc/testsuite/g++.target/powerpc/pr105325.C b/gcc/testsuite/g++.target/powerpc/pr105325.C
deleted file mode 100644
index d0e66a0b897..00000000000
--- a/gcc/testsuite/g++.target/powerpc/pr105325.C
+++ /dev/null
@@ -1,26 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10 -fstack-protector" } */
-
-/* Test that power10 fusion does not generate an LWA/CMPDI instruction pair
- instead of PLWZ/CMPWI. Ultimately the code was dying because the fusion
- load + compare -1/0/1 patterns did not handle the possibility that the load
- might be prefixed. The -fstack-protector option is needed to show the
- bug. */
-
-struct Ath__array1D {
- int _current;
- int getCnt() { return _current; }
-};
-struct extMeasure {
- int _mapTable[10000];
- Ath__array1D _metRCTable;
-};
-void measureRC() {
- extMeasure m;
- for (; m._metRCTable.getCnt();)
- for (;;)
- ;
-}
diff --git a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
index ca7297375a4..526a026d874 100644
--- a/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
+++ b/gcc/testsuite/gcc.target/powerpc/fusion-p10-ldcmpi.c
@@ -61,7 +61,7 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 16 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target lp64 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 8 { target lp64 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 4 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target lp64 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 2 { target lp64 } } } */
@@ -73,6 +73,6 @@ TEST(int8_t)
/* { dg-final { scan-assembler-times "lha_cmpdi_cr0_HI_clobber_CC_sign" 8 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 2 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 0 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 16 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times "lwa_cmpdi_cr0_SI_clobber_CC_none" 9 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 0 { target ilp32 } } } */
/* { dg-final { scan-assembler-times "lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 6 { target ilp32 } } } */
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-08 23:26 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-08 23:26 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:801ac8df911c5a2d2b1f44cc672c5d1e302e92b6
commit 801ac8df911c5a2d2b1f44cc672c5d1e302e92b6
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 19:26:08 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 +++++++++++++++++------------------------
1 file changed, 86 insertions(+), 126 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index b053005fa92..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,135 +53,95 @@ sub mode_to_ldst_char
return '?';
}
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- memory format ("d" or "ds").
-
-sub print_ld_cmpi_p10
-{
- my ($lmode, $result, $ccmode, $mem_format) = @_;
-
- my $ldst = mode_to_ldst_char($lmode);
-
- # Set various things based on whether the comparisons are signed or
- # unsigned.
- my ($cmpl, $const_pred, $sign_zero, $a_or_z)
- = (($ccmode eq "CCUNS")
- ? ("l", "const_0_to_1_operand", "zero", "z")
- : ("", "const_m1_to_1_operand", "sign", "a"));
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
-
- # We always need extension if result > lmode.
- my $extend = (($result =~ m/^EXT/
- || $result eq "GPR"
- || $clobbermode eq "GPR") ? $sign_zero : "none");
-
- # DI-mode doesn't do sign/zero extension.
- my $echr = ($lmode eq "DI") ? "" : $a_or_z;
-
- # Handle DS vs. D format memory.
- my ($np, $mempred) = (($mem_format eq "ds")
- ? ("NON_PREFIXED_DS", "ds_form_mem_operand")
- : ("NON_PREFIXED_D", "non_update_memory_operand"));
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- print ";; ${info}\n";
-
- my $name = join ("",
- "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
-}
-
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mempred, $np, $mem_format);
-
- foreach $lmode ("DI","SI", "HI", "QI")
- {
- foreach $result ("clobber", $lmode, "EXT${lmode}")
- {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next if ($result =~ m/^(EXTDI|HI|QI)$/);
-
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if ($result eq "EXTQI");
-
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
- # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
- # instructions.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
- print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # ld is DS-form, but lwz is not.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-08 23:21 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-08 23:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5a647e424d24e3764fa3a16ece59b1982604e03a
commit 5a647e424d24e3764fa3a16ece59b1982604e03a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 19:21:26 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 +++++++++++++++++------------------------
1 file changed, 86 insertions(+), 126 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 84de9ac3542..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,135 +53,95 @@ sub mode_to_ldst_char
return '?';
}
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- memory format ("d" or "ds").
-
-sub print_ld_cmpi_p10
-{
- my ($lmode, $result, $ccmode, $mem_format) = @_;
-
- my $ldst = mode_to_ldst_char($lmode);
-
- # Set various things based on whether the comparisons are signed or
- # unsigned.
- my ($cmpl, $const_pred, $sign_zero, $a_or_z)
- = (($ccmode eq "CCUNS")
- ? ("l", "const_0_to_1_operand", "zero", "z")
- : ("", "const_m1_to_1_operand", "sign", "a"));
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
-
- # We always need extension if result > lmode.
- my $extend = (($result =~ m/^EXT/
- || $result eq "GPR"
- || $clobbermode eq "GPR") ? $sign_zero : "none");
-
- # DI-mode doesn't do sign/zero extension.
- my $echr = ($lmode eq "DI") ? "" : $a_or_z;
-
- # Handle DS vs. D format memory.
- my ($mempred, $np) = (($mem_format eq "ds")
- ? ("ds_form_mem_operand", "NON_PREFIXED_DS")
- : ("non_update_memory_operand", "NON_PREFIXED_D"));
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- print ";; ${info}\n";
-
- my $name = join ("",
- "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
-}
-
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mempred, $np, $mem_format);
-
- foreach $lmode ("DI","SI", "HI", "QI")
- {
- foreach $result ("clobber", $lmode, "EXT${lmode}")
- {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next if ($result =~ m/^(EXTDI|HI|QI)$/);
-
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if ($result eq "EXTQI");
-
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
- # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
- # instructions.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
- print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # ld is DS-form, but lwz is not.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-08 23:20 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-08 23:20 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:3d4bfa4137bc3d1daa7e3c308f8b6ec7c23f5943
commit 3d4bfa4137bc3d1daa7e3c308f8b6ec7c23f5943
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 19:20:33 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 ++++++++++++++++++++++++-----------------
1 file changed, 126 insertions(+), 86 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index e4db352e0ce..84de9ac3542 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,95 +53,135 @@ sub mode_to_ldst_char
return '?';
}
+# Print the insns for load and compare with -1/0/1.
+# Arguments:
+# lmode -- integer mode ("DI", "SI", "HI", or "QI").
+# result -- "clobber", "GPR", or $lmode
+# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
+# mem_format -- memory format ("d" or "ds").
+
+sub print_ld_cmpi_p10
+{
+ my ($lmode, $result, $ccmode, $mem_format) = @_;
+
+ my $ldst = mode_to_ldst_char($lmode);
+
+ # Set various things based on whether the comparisons are signed or
+ # unsigned.
+ my ($cmpl, $const_pred, $sign_zero, $a_or_z)
+ = (($ccmode eq "CCUNS")
+ ? ("l", "const_0_to_1_operand", "zero", "z")
+ : ("", "const_m1_to_1_operand", "sign", "a"));
+
+ # For clobber, we need a SI/DI reg in case we split because we have to
+ # sign/zero extend.
+ my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
+
+ # We always need extension if result > lmode.
+ my $extend = (($result =~ m/^EXT/
+ || $result eq "GPR"
+ || $clobbermode eq "GPR") ? $sign_zero : "none");
+
+ # DI-mode doesn't do sign/zero extension.
+ my $echr = ($lmode eq "DI") ? "" : $a_or_z;
+
+ # Handle DS vs. D format memory.
+ my ($mempred, $np) = (($mem_format eq "ds")
+ ? ("ds_form_mem_operand", "NON_PREFIXED_DS")
+ : ("non_update_memory_operand", "NON_PREFIXED_D"));
+
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+
+ my $info = join (" ",
+ "load mode is ${lmode} result mode is ${result}",
+ "compare mode is ${ccmode} extend is ${extend}");
+
+ print ";; ${info}\n";
+
+ my $name = join ("",
+ "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
+ "_${result}_${ccmode}_${extend}");
+
+ my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
+
+ my $spaces = " " x (length ($ccmode) + 18);
+
+ print "(define_insn_and_split \"*${name}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} ${cmp_op1}\n";
+ print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
+
+ if ($result eq "clobber")
+ {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ }
+
+ else
+ {
+ my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
+ my $load_op1 = (($result eq $lmode)
+ ? "(match_dup 1)"
+ : "(${extend}_extend:${result} (match_dup 1))");
+ print " (set ${load_op0} ${load_op1})]\n";
+ }
+
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none")
+ {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ }
+
+ else
+ {
+ my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+}
+
sub gen_ld_cmpi_p10
{
- my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
- $mempred, $ccmode, $np, $extend, $resultmode);
- LMODE: foreach $lmode ('DI','SI','HI','QI') {
- $ldst = mode_to_ldst_char($lmode);
- $clobbermode = $lmode;
- # For clobber, we need a SI/DI reg in case we
- # split because we have to sign/zero extend.
- if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
- RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if $result eq "EXTQI";
- CCMODE: foreach $ccmode ('CC','CCUNS') {
- $np = "NON_PREFIXED_D";
- $mempred = "non_update_memory_operand";
- if ( $ccmode eq 'CC' ) {
- next CCMODE if $lmode eq 'QI';
- if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
- # ld and lwa are both DS-FORM.
- $np = "NON_PREFIXED_DS";
- $mempred = "ds_form_mem_operand";
- }
- $cmpl = "";
- $echr = "a";
- $constpred = "const_m1_to_1_operand";
- } else {
- if ( $lmode eq 'DI' ) {
- # ld is DS-form, but lwz is not.
- $np = "NON_PREFIXED_DS";
- $mempred = "ds_form_mem_operand";
- }
- $cmpl = "l";
- $echr = "z";
- $constpred = "const_0_to_1_operand";
- }
- if ($lmode eq 'DI') { $echr = ""; }
- if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
- # We always need extension if result > lmode.
- if ( $ccmode eq 'CC' ) {
- $extend = "sign";
- } else {
- $extend = "zero";
- }
- } else {
- # Result of SI/DI does not need sign extension.
- $extend = "none";
- }
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
- print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
-
- print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
- if ($ccmode eq 'CCUNS') { print " "; }
- print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
- if ($result eq 'clobber') {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- } elsif ($result eq $lmode) {
- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
- } else {
- print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
- }
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none") {
- print " [(set (match_dup 0) (match_dup 1))\n";
- } else {
- $resultmode = $result;
- if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
- }
+ my ($lmode, $result, $mempred, $np, $mem_format);
+
+ foreach $lmode ("DI","SI", "HI", "QI")
+ {
+ foreach $result ("clobber", $lmode, "EXT${lmode}")
+ {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next if ($result =~ m/^(EXTDI|HI|QI)$/);
+
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if ($result eq "EXTQI");
+
+ # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
+ # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
+ # instructions.
+ if ($lmode ne "QI")
+ {
+ $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
+ print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
+ }
+
+ # Handle CCUNS mode (zero extended compares to 0 or 1.
+ # ld is DS-form, but lwz is not.
+ $mem_format = ($lmode eq "DI") ? "ds" : "d";
+
+ print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
+ }
}
- }
}
sub gen_logical_addsubf
^ permalink raw reply [flat|nested] 22+ messages in thread
* [gcc(refs/users/meissner/heads/work121)] Revert patches
@ 2023-05-08 22:17 Michael Meissner
0 siblings, 0 replies; 22+ messages in thread
From: Michael Meissner @ 2023-05-08 22:17 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1c9ca427b3d63f47bb7eb370a3aec8add4e9c66f
commit 1c9ca427b3d63f47bb7eb370a3aec8add4e9c66f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon May 8 18:17:36 2023 -0400
Revert patches
Diff:
---
gcc/config/rs6000/genfusion.pl | 212 +++++++++++++++++------------------------
1 file changed, 86 insertions(+), 126 deletions(-)
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index 84de9ac3542..e4db352e0ce 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -53,135 +53,95 @@ sub mode_to_ldst_char
return '?';
}
-# Print the insns for load and compare with -1/0/1.
-# Arguments:
-# lmode -- integer mode ("DI", "SI", "HI", or "QI").
-# result -- "clobber", "GPR", or $lmode
-# ccmode -- sign vs. unsigned ("CC" or "CCUNS").
-# mem_format -- memory format ("d" or "ds").
-
-sub print_ld_cmpi_p10
-{
- my ($lmode, $result, $ccmode, $mem_format) = @_;
-
- my $ldst = mode_to_ldst_char($lmode);
-
- # Set various things based on whether the comparisons are signed or
- # unsigned.
- my ($cmpl, $const_pred, $sign_zero, $a_or_z)
- = (($ccmode eq "CCUNS")
- ? ("l", "const_0_to_1_operand", "zero", "z")
- : ("", "const_m1_to_1_operand", "sign", "a"));
-
- # For clobber, we need a SI/DI reg in case we split because we have to
- # sign/zero extend.
- my $clobbermode = ($lmode =~ m/^(QI|HI)$/) ? "GPR" : $lmode;
-
- # We always need extension if result > lmode.
- my $extend = (($result =~ m/^EXT/
- || $result eq "GPR"
- || $clobbermode eq "GPR") ? $sign_zero : "none");
-
- # DI-mode doesn't do sign/zero extension.
- my $echr = ($lmode eq "DI") ? "" : $a_or_z;
-
- # Handle DS vs. D format memory.
- my ($mempred, $np) = (($mem_format eq "ds")
- ? ("ds_form_mem_operand", "NON_PREFIXED_DS")
- : ("non_update_memory_operand", "NON_PREFIXED_D"));
-
- print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
-
- my $info = join (" ",
- "load mode is ${lmode} result mode is ${result}",
- "compare mode is ${ccmode} extend is ${extend}");
-
- print ";; ${info}\n";
-
- my $name = join ("",
- "l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}",
- "_${result}_${ccmode}_${extend}");
-
- my $cmp_op1 = "(match_operand:${lmode} 1 \"${mempred}\" \"m\")";
-
- my $spaces = " " x (length ($ccmode) + 18);
-
- print "(define_insn_and_split \"*${name}\"\n";
- print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
- print " (compare:${ccmode} ${cmp_op1}\n";
- print "${spaces}(match_operand:${lmode} 3 \"${const_pred}\" \"n\")))\n";
-
- if ($result eq "clobber")
- {
- print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
- }
-
- else
- {
- my $load_op0 = "(match_operand:${result} 0 \"gpc_reg_operand\" \"=r\")";
- my $load_op1 = (($result eq $lmode)
- ? "(match_dup 1)"
- : "(${extend}_extend:${result} (match_dup 1))");
- print " (set ${load_op0} ${load_op1})]\n";
- }
-
- print " \"(TARGET_P10_FUSION)\"\n";
- print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
- print " \"&& reload_completed\n";
- print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
- print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
- print " ${lmode}mode, ${np}))\"\n";
-
- if ($extend eq "none")
- {
- print " [(set (match_dup 0) (match_dup 1))\n";
- }
-
- else
- {
- my $resultmode = ($result eq "clobber") ? $clobbermode : $result;
- print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
- }
-
- print " (set (match_dup 2)\n";
- print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
- print " \"\"\n";
- print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
- print " (set_attr \"cost\" \"8\")\n";
- print " (set_attr \"length\" \"8\")])\n";
- print "\n";
-}
-
sub gen_ld_cmpi_p10
{
- my ($lmode, $result, $mempred, $np, $mem_format);
-
- foreach $lmode ("DI","SI", "HI", "QI")
- {
- foreach $result ("clobber", $lmode, "EXT${lmode}")
- {
- # EXTDI does not exist, and we cannot directly produce HI/QI results.
- next if ($result =~ m/^(EXTDI|HI|QI)$/);
-
- # Don't allow EXTQI because that would allow HI result which we can't do.
- $result = "GPR" if ($result eq "EXTQI");
-
- # Handle CCmode (sign extended compares to -1, 0, or 1). We don't have
- # a LBA instruction, so skip QImode. Both LD and LWA are DS-form
- # instructions.
- if ($lmode ne "QI")
- {
- $mem_format = ($lmode =~ m/^(DI|SI)$/) ? "ds" : "d";
- print_ld_cmpi_p10 ($lmode, $result, "CC", $mem_format);
- }
-
- # Handle CCUNS mode (zero extended compares to 0 or 1.
- # ld is DS-form, but lwz is not.
- $mem_format = ($lmode eq "DI") ? "ds" : "d";
-
- print_ld_cmpi_p10 ($lmode, $result, "CCUNS", $mem_format);
- }
+ my ($lmode, $ldst, $clobbermode, $result, $cmpl, $echr, $constpred,
+ $mempred, $ccmode, $np, $extend, $resultmode);
+ LMODE: foreach $lmode ('DI','SI','HI','QI') {
+ $ldst = mode_to_ldst_char($lmode);
+ $clobbermode = $lmode;
+ # For clobber, we need a SI/DI reg in case we
+ # split because we have to sign/zero extend.
+ if ($lmode eq 'HI' || $lmode eq 'QI') { $clobbermode = "GPR"; }
+ RESULT: foreach $result ('clobber', $lmode, "EXT".$lmode) {
+ # EXTDI does not exist, and we cannot directly produce HI/QI results.
+ next RESULT if $result eq "EXTDI" || $result eq "HI" || $result eq "QI";
+ # Don't allow EXTQI because that would allow HI result which we can't do.
+ $result = "GPR" if $result eq "EXTQI";
+ CCMODE: foreach $ccmode ('CC','CCUNS') {
+ $np = "NON_PREFIXED_D";
+ $mempred = "non_update_memory_operand";
+ if ( $ccmode eq 'CC' ) {
+ next CCMODE if $lmode eq 'QI';
+ if ( $lmode eq 'DI' || $lmode eq 'SI' ) {
+ # ld and lwa are both DS-FORM.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "";
+ $echr = "a";
+ $constpred = "const_m1_to_1_operand";
+ } else {
+ if ( $lmode eq 'DI' ) {
+ # ld is DS-form, but lwz is not.
+ $np = "NON_PREFIXED_DS";
+ $mempred = "ds_form_mem_operand";
+ }
+ $cmpl = "l";
+ $echr = "z";
+ $constpred = "const_0_to_1_operand";
+ }
+ if ($lmode eq 'DI') { $echr = ""; }
+ if ($result =~ m/^EXT/ || $result eq 'GPR' || $clobbermode eq 'GPR') {
+ # We always need extension if result > lmode.
+ if ( $ccmode eq 'CC' ) {
+ $extend = "sign";
+ } else {
+ $extend = "zero";
+ }
+ } else {
+ # Result of SI/DI does not need sign extension.
+ $extend = "none";
+ }
+ print ";; load-cmpi fusion pattern generated by gen_ld_cmpi_p10\n";
+ print ";; load mode is $lmode result mode is $result compare mode is $ccmode extend is $extend\n";
+
+ print "(define_insn_and_split \"*l${ldst}${echr}_cmp${cmpl}di_cr0_${lmode}_${result}_${ccmode}_${extend}\"\n";
+ print " [(set (match_operand:${ccmode} 2 \"cc_reg_operand\" \"=x\")\n";
+ print " (compare:${ccmode} (match_operand:${lmode} 1 \"${mempred}\" \"m\")\n";
+ if ($ccmode eq 'CCUNS') { print " "; }
+ print " (match_operand:${lmode} 3 \"${constpred}\" \"n\")))\n";
+ if ($result eq 'clobber') {
+ print " (clobber (match_scratch:${clobbermode} 0 \"=r\"))]\n";
+ } elsif ($result eq $lmode) {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (match_dup 1))]\n";
+ } else {
+ print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
+ }
+ print " \"(TARGET_P10_FUSION)\"\n";
+ print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
+ print " \"&& reload_completed\n";
+ print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
+ print " || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),\n";
+ print " ${lmode}mode, ${np}))\"\n";
+
+ if ($extend eq "none") {
+ print " [(set (match_dup 0) (match_dup 1))\n";
+ } else {
+ $resultmode = $result;
+ if ( $result eq 'clobber' ) { $resultmode = $clobbermode }
+ print " [(set (match_dup 0) (${extend}_extend:${resultmode} (match_dup 1)))\n";
+ }
+ print " (set (match_dup 2)\n";
+ print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
+ print " \"\"\n";
+ print " [(set_attr \"type\" \"fused_load_cmpi\")\n";
+ print " (set_attr \"cost\" \"8\")\n";
+ print " (set_attr \"length\" \"8\")])\n";
+ print "\n";
+ }
}
+ }
}
sub gen_logical_addsubf
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