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From: "" <>
To: jiawei <>,  gcc-patches <>
Cc: Kito.cheng <>,  palmer <>,
	 jeffreyalaw <>,
	 christoph.muellner <>,
	 philipp.tomsich <>,
	 wuwei2016 <>,  jiawei <>
Subject: Re: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.
Date: Tue, 15 Nov 2022 16:39:37 +0800	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

[-- Attachment #1: Type: text/plain, Size: 1322 bytes --]

LGTM. Thanks for fixing my mistake. 
Let's see whether other RISC-V folks are happy with this patch.
From: jiawei
Date: 2022-11-15 16:33
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; jeffreyalaw; christoph.muellner; philipp.tomsich; wuwei2016; jiawei
Subject: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.
Current epilogue will generate "addi sp,sp,0" redundant instruction.
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        addi    sp,sp,0
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
Optimize it by check if adjust equal to zero, remove redundant insn gen.
        csrr    t0,vlenb
        slli    t1,t0,1
        add     sp,sp,t1
        ld      s0,24(sp)
        addi    sp,sp,32
        jr      ra
Thanks for Kito and Jeff's suggestion, add testcase and fix code format.
jiawei (2):
  RISC-V: Add spill sp adjust check testcase.
  RISC-V: Optimize RVV epilogue logic.
gcc/config/riscv/                     | 35 ++++++++++---------
.../riscv/rvv/base/spill-sp-adjust.c          | 13 +++++++
2 files changed, 32 insertions(+), 16 deletions(-)
create mode 100644 gcc/testsuite/

      parent reply	other threads:[~2022-11-15  8:39 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-15  8:33 jiawei
2022-11-15  8:33 ` [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase jiawei
2022-11-17  4:02   ` Jeff Law
2022-11-15  8:33 ` [PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic jiawei
2022-11-15  8:39 ` juzhe.zhong [this message]

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