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From: Jeff Law <>
To: jiawei <>,
Subject: Re: [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.
Date: Wed, 16 Nov 2022 21:02:44 -0700	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 11/15/22 01:33, jiawei wrote:
> This testcase mix exist spill-1.c and adding new fun to check if
> there have redundant addi intructions. Idea provided by Jeff Law.
> gcc/testsuite/ChangeLog:
>          * New test.

I made several whitespace/formatting fixes to the part of this 
series, improved the Changelog and and committed it for you.



  reply	other threads:[~2022-11-17  4:02 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-15  8:33 [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic jiawei
2022-11-15  8:33 ` [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase jiawei
2022-11-17  4:02   ` Jeff Law [this message]
2022-11-15  8:33 ` [PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic jiawei
2022-11-15  8:39 ` [PATCH v2 0/2] " juzhe.zhong

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