From: jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai,
jeffreyalaw@gmail.com, christoph.muellner@vrull.eu,
philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn,
jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic.
Date: Tue, 15 Nov 2022 16:33:56 +0800 [thread overview]
Message-ID: <20221115083358.4130952-1-jiawei@iscas.ac.cn> (raw)
Current epilogue will generate "addi sp,sp,0" redundant instruction.
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
addi sp,sp,0
ld s0,24(sp)
addi sp,sp,32
jr ra
```
Optimize it by check if adjust equal to zero, remove redundant insn gen.
```
csrr t0,vlenb
slli t1,t0,1
add sp,sp,t1
ld s0,24(sp)
addi sp,sp,32
jr ra
```
Thanks for Kito and Jeff's suggestion, add testcase and fix code format.
jiawei (2):
RISC-V: Add spill sp adjust check testcase.
RISC-V: Optimize RVV epilogue logic.
gcc/config/riscv/riscv.cc | 35 ++++++++++---------
.../riscv/rvv/base/spill-sp-adjust.c | 13 +++++++
2 files changed, 32 insertions(+), 16 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
--
2.25.1
next reply other threads:[~2022-11-15 8:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 8:33 jiawei [this message]
2022-11-15 8:33 ` [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase jiawei
2022-11-17 4:02 ` Jeff Law
2022-11-15 8:33 ` [PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic jiawei
2022-11-15 8:39 ` [PATCH v2 0/2] " juzhe.zhong
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