From: jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai,
jeffreyalaw@gmail.com, christoph.muellner@vrull.eu,
philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn,
jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase.
Date: Tue, 15 Nov 2022 16:33:57 +0800 [thread overview]
Message-ID: <20221115083358.4130952-2-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20221115083358.4130952-1-jiawei@iscas.ac.cn>
This testcase mix exist spill-1.c and adding new fun to check if
there have redundant addi intructions. Idea provided by Jeff Law.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test.
---
.../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
new file mode 100644
index 00000000000..0226554abf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv" } */
+
+#include "spill-1.c"
+
+void
+spill_sp_adjust (int8_t *v)
+{
+ vint8mf8_t v1 = *(vint8mf8_t*)v;
+}
+
+/* Make sure we do not have a useless SP adjustment. */
+/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */
--
2.25.1
next prev parent reply other threads:[~2022-11-15 8:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 8:33 [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic jiawei
2022-11-15 8:33 ` jiawei [this message]
2022-11-17 4:02 ` [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase Jeff Law
2022-11-15 8:33 ` [PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic jiawei
2022-11-15 8:39 ` [PATCH v2 0/2] " juzhe.zhong
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