From: jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai,
jeffreyalaw@gmail.com, christoph.muellner@vrull.eu,
philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn,
jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic.
Date: Tue, 15 Nov 2022 16:33:58 +0800 [thread overview]
Message-ID: <20221115083358.4130952-3-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20221115083358.4130952-1-jiawei@iscas.ac.cn>
Sometimes "step1 -= scalable_frame" will cause adjust equal to
zero. And it will generate additional redundant instruction
"addi sp,sp,0". Add checking segement to skip that case.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_expand_epilogue):
New check segement.
---
gcc/config/riscv/riscv.cc | 35 +++++++++++++++++++----------------
1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 02a01ca0b7c..433b9b13eb6 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5185,25 +5185,28 @@ riscv_expand_epilogue (int style)
step1 -= scalable_frame;
}
- /* Get an rtx for STEP1 that we can add to BASE. */
- rtx adjust = GEN_INT (step1.to_constant ());
- if (!SMALL_OPERAND (step1.to_constant ()))
- {
- riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
- adjust = RISCV_PROLOGUE_TEMP (Pmode);
- }
-
- insn = emit_insn (
- gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
-
- rtx dwarf = NULL_RTX;
- rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+ /* Get an rtx for STEP1 that we can add to BASE.
+ Skip if adjust equal to zero. */
+ if (step1.to_constant () != 0)
+ {
+ rtx adjust = GEN_INT (step1.to_constant ());
+ if (!SMALL_OPERAND (step1.to_constant ()))
+ {
+ riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust);
+ adjust = RISCV_PROLOGUE_TEMP (Pmode);
+ }
+
+ insn = emit_insn (
+ gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust));
+ rtx dwarf = NULL_RTX;
+ rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
GEN_INT (step2));
- dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
- RTX_FRAME_RELATED_P (insn) = 1;
+ dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf);
+ RTX_FRAME_RELATED_P (insn) = 1;
- REG_NOTES (insn) = dwarf;
+ REG_NOTES (insn) = dwarf;
+ }
}
else if (frame_pointer_needed)
{
--
2.25.1
next prev parent reply other threads:[~2022-11-15 8:34 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-15 8:33 [PATCH v2 0/2] " jiawei
2022-11-15 8:33 ` [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase jiawei
2022-11-17 4:02 ` Jeff Law
2022-11-15 8:33 ` jiawei [this message]
2022-11-15 8:39 ` [PATCH v2 0/2] RISC-V: Optimize RVV epilogue logic juzhe.zhong
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