From: <apinski@marvell.com>
To: <gcc-patches@gcc.gnu.org>
Cc: Andrew Pinski <apinski@marvell.com>
Subject: [PATCH 03/10] [RISCV] Move iterators from sync.md to iterators.md
Date: Thu, 18 Aug 2022 15:03:46 -0700 [thread overview]
Message-ID: <1660860233-11175-4-git-send-email-apinski@marvell.com> (raw)
In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com>
From: Andrew Pinski <apinski@marvell.com>
Like the previous two patches this moves the iterators
that are in sync.md to iterators.md.
OK? build and tested for riscv64-linux-gnu.
gcc/ChangeLog:
* config/riscv/sync.md (any_atomic, atomic_optab): Move to ...
* config/riscv/iterators.md: Here.
---
gcc/config/riscv/iterators.md | 7 +++++++
gcc/config/riscv/sync.md | 4 ----
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 54590f43193..6c8a6d2dd59 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -151,6 +151,9 @@ (define_code_iterator any_ge [ge geu])
(define_code_iterator any_lt [lt ltu])
(define_code_iterator any_le [le leu])
+; atomics code iterator
+(define_code_iterator any_atomic [plus ior xor and])
+
; bitmanip code iterators
(define_code_iterator bitmanip_bitwise [and ior])
@@ -205,6 +208,10 @@ (define_code_attr insn [(ashift "sll")
(plus "add")
(minus "sub")])
+; atomics code attribute
+(define_code_attr atomic_optab
+ [(plus "add") (ior "or") (xor "xor") (and "and")])
+
; bitmanip code attributes
(define_code_attr bitmanip_optab [(smin "smin")
(smax "smax")
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 86b41e6b00a..7deb290d9dc 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -27,10 +27,6 @@ (define_c_enum "unspec" [
UNSPEC_MEMORY_BARRIER
])
-(define_code_iterator any_atomic [plus ior xor and])
-(define_code_attr atomic_optab
- [(plus "add") (ior "or") (xor "xor") (and "and")])
-
;; Memory barriers.
(define_expand "mem_thread_fence"
--
2.27.0
next prev parent reply other threads:[~2022-08-18 22:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
2022-08-18 22:03 ` apinski [this message]
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
2022-08-22 8:47 ` Kito Cheng
2022-08-18 22:03 ` [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask apinski
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
2022-08-18 22:03 ` [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand apinski
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
2022-08-22 9:09 ` Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
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