From: <apinski@marvell.com>
To: <gcc-patches@gcc.gnu.org>
Cc: Andrew Pinski <apinski@marvell.com>
Subject: [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask
Date: Thu, 18 Aug 2022 15:03:50 -0700 [thread overview]
Message-ID: <1660860233-11175-8-git-send-email-apinski@marvell.com> (raw)
In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com>
From: Andrew Pinski <apinski@marvell.com>
A constraint here just makes it easier to understand what the
operands are.
OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
--with-arch=rvNimafdc_zba_zbb_zbc_zbs (where N is 32 and 64).
Thanks,
Andrew Pinski
gcc/ChangeLog:
* config/riscv/constraints.md (DsS): New constraint.
(DsD): New constraint.
* config/riscv/iterators.md (shiftm1c): New iterator.
* config/riscv/bitmanip.md (*bset<mode>_mask):
Use shiftm1c.
(*bset<mode>_1_mask): Likewise.
---
gcc/config/riscv/bitmanip.md | 4 ++--
gcc/config/riscv/constraints.md | 12 ++++++++++++
gcc/config/riscv/iterators.md | 1 +
3 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 73a36f7751b..d362f526e79 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -273,7 +273,7 @@ (define_insn "*bset<mode>_mask"
(ior:X (ashift:X (const_int 1)
(subreg:QI
(and:X (match_operand:X 2 "register_operand" "r")
- (match_operand 3 "<X:shiftm1>" "i")) 0))
+ (match_operand 3 "<X:shiftm1>" "<X:shiftm1p>")) 0))
(match_operand:X 1 "register_operand" "r")))]
"TARGET_ZBS"
"bset\t%0,%1,%2"
@@ -292,7 +292,7 @@ (define_insn "*bset<mode>_1_mask"
(ashift:X (const_int 1)
(subreg:QI
(and:X (match_operand:X 1 "register_operand" "r")
- (match_operand 2 "<X:shiftm1>" "i")) 0)))]
+ (match_operand 2 "<X:shiftm1>" "<X:shiftm1p>")) 0)))]
"TARGET_ZBS"
"bset\t%0,x0,%1"
[(set_attr "type" "bitmanip")])
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 61b84875fd9..444870ad060 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -60,6 +60,18 @@ (define_constraint "Ds3"
(and (match_code "const_int")
(match_test "IN_RANGE (ival, 1, 3)")))
+(define_constraint "DsS"
+ "@internal
+ 31 immediate"
+ (and (match_code "const_int")
+ (match_test "ival == 31")))
+
+(define_constraint "DsD"
+ "@internal
+ 63 immediate"
+ (and (match_code "const_int")
+ (match_test "ival == 63")))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 6c8a6d2dd59..be0d5390307 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -115,6 +115,7 @@ (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
; bitmanip mode attribute
(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
+(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
;; -------------------------------------------------------------------
;; Code Iterators
--
2.27.0
next prev parent reply other threads:[~2022-08-18 22:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
2022-08-18 22:03 ` [PATCH 03/10] [RISCV] Move iterators from sync.md " apinski
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
2022-08-22 8:47 ` Kito Cheng
2022-08-18 22:03 ` apinski [this message]
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
2022-08-18 22:03 ` [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand apinski
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
2022-08-22 9:09 ` Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
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