From: Kito Cheng <kito.cheng@gmail.com>
To: apinski@marvell.com
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns
Date: Mon, 22 Aug 2022 16:47:34 +0800 [thread overview]
Message-ID: <CA+yXCZC_MmKcsQ9rojOwpgkFewh08XhR_3fnVKgSrmEwCgLm1Q@mail.gmail.com> (raw)
In-Reply-To: <1660860233-11175-7-git-send-email-apinski@marvell.com>
I know using more precise constraints might result in better code gen
in some situations, but I am Curious what's the difference between the
using pattern condition and constraints/predicates in this case? Is
there any performance or code gen difference?
On Fri, Aug 19, 2022 at 6:07 AM apinski--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Andrew Pinski <apinski@marvell.com>
>
> This simplifies the code by adding a predicate and a constraint for 1/2/3.
> The aarch64 backend has a similar predicate called aarch64_shift_imm_<mode>
> which they use there.
>
> OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with no regressions.
>
> Thanks,
> Andrew Pinski
>
> gcc/ChangeLog:
>
> * config/riscv/constraints.md (Ds3): New constraint.
> * config/riscv/predicates.md (imm123_operand): New predicate.
> * config/riscv/bitmanip.md (*shNadd): Use Ds3 and imm123_operand.
> (*shNadduw): Likewise.
> ---
> gcc/config/riscv/bitmanip.md | 8 +++-----
> gcc/config/riscv/constraints.md | 6 ++++++
> gcc/config/riscv/predicates.md | 5 +++++
> 3 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index ebd6eee1a22..73a36f7751b 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -32,10 +32,9 @@ (define_insn "*zero_extendsidi2_bitmanip"
> (define_insn "*shNadd"
> [(set (match_operand:X 0 "register_operand" "=r")
> (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
> - (match_operand:QI 2 "immediate_operand" "I"))
> + (match_operand:QI 2 "imm123_operand" "Ds3"))
> (match_operand:X 3 "register_operand" "r")))]
> - "TARGET_ZBA
> - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)"
> + "TARGET_ZBA"
> "sh%2add\t%0,%1,%3"
> [(set_attr "type" "bitmanip")
> (set_attr "mode" "<X:MODE>")])
> @@ -44,11 +43,10 @@ (define_insn "*shNadduw"
> [(set (match_operand:DI 0 "register_operand" "=r")
> (plus:DI
> (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
> - (match_operand:QI 2 "immediate_operand" "I"))
> + (match_operand:QI 2 "imm123_operand" "Ds3"))
> (match_operand 3 "immediate_operand" ""))
> (match_operand:DI 4 "register_operand" "r")))]
> "TARGET_64BIT && TARGET_ZBA
> - && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
> && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
> "sh%2add.uw\t%0,%1,%4"
> [(set_attr "type" "bitmanip")
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index bafa4188ccb..61b84875fd9 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -54,6 +54,12 @@ (define_constraint "L"
> (and (match_code "const_int")
> (match_test "LUI_OPERAND (ival)")))
>
> +(define_constraint "Ds3"
> + "@internal
> + 1, 2 or 3 immediate"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (ival, 1, 3)")))
> +
> ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
> ;; not available in RV32.
> (define_constraint "G"
> diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
> index 79e0c1d5589..2af7f661d6f 100644
> --- a/gcc/config/riscv/predicates.md
> +++ b/gcc/config/riscv/predicates.md
> @@ -244,6 +244,11 @@ (define_predicate "imm5_operand"
> (and (match_code "const_int")
> (match_test "INTVAL (op) < 5")))
>
> +;; A const_int for sh1add/sh2add/sh3add
> +(define_predicate "imm123_operand"
> + (and (match_code "const_int")
> + (match_test "IN_RANGE (INTVAL (op), 1, 3)")))
> +
> ;; A CONST_INT operand that consists of a single run of consecutive set bits.
> (define_predicate "consecutive_bits_operand"
> (match_code "const_int")
> --
> 2.27.0
>
next prev parent reply other threads:[~2022-08-22 8:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 22:03 [PATCH 00/10] [RISCV] Fix/improve the RISCV backend apinski
2022-08-18 22:03 ` [PATCH 01/10] [RISCV] Move iterators from riscv.md to iterators.md apinski
2022-08-18 22:03 ` [PATCH 02/10] [RISCV] Move iterators from bitmanip.md " apinski
2022-08-18 22:03 ` [PATCH 03/10] [RISCV] Move iterators from sync.md " apinski
2022-08-18 22:03 ` [PATCH 04/10] [RISCV] Add the list of operand modifiers to riscv.md too apinski
2022-08-18 22:03 ` [PATCH 05/10] [RISCV] Add %~ to print w if TARGET_64BIT and use it apinski
2022-08-18 22:03 ` [PATCH 06/10] [RISCV] Use constraints/predicates instead of checking const_int directly for shNadd patterns apinski
2022-08-22 8:47 ` Kito Cheng [this message]
2022-08-18 22:03 ` [PATCH 07/10] [RISCV] Use a constraint for bset<mode>_mask and bset<mode>_1_mask apinski
2022-08-18 22:03 ` [PATCH 08/10] [RISCV] Fix PR 106586: riscv32 vs ZBS apinski
2022-08-18 22:03 ` [PATCH 09/10] [RISCV] Add constraints for not_single_bit_mask_operand/single_bit_mask_operand apinski
2022-08-18 22:03 ` [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md apinski
2022-08-22 9:09 ` Kito Cheng
2022-08-22 20:44 ` Palmer Dabbelt
2022-08-22 20:44 ` [PATCH 00/10] [RISCV] Fix/improve the RISCV backend Palmer Dabbelt
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