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From: Christoph Muellner <cmuellner@gcc.gnu.org>
To: gcc-patches@gcc.gnu.org
Cc: Jim Wilson <jimw@sifive.com>, Kito Cheng <kito.cheng@sifive.com>,
	Christoph Muellner <cmuellner@gcc.gnu.org>
Subject: [PATCH 01/10] RISC-V: Simplify memory model code [PR 100265]
Date: Mon, 26 Apr 2021 14:45:43 +0200	[thread overview]
Message-ID: <20210426124552.3316789-2-cmuellner@gcc.gnu.org> (raw)
In-Reply-To: <20210426124552.3316789-1-cmuellner@gcc.gnu.org>

We don't have any special treatment of MEMMODEL_SYNC_* values,
so let's hide them behind the memmodel_base() function.

    gcc/
	PR 100265
        * config/riscv/riscv.c (riscv_memmodel_needs_amo_acquire):
	  Ignore MEMMODEL_SYNC_* values.
        * config/riscv/riscv.c (riscv_memmodel_needs_release_fence):
	  Likewise.
        * config/riscv/riscv.c (riscv_print_operand): Eliminate
	  MEMMODEL_SYNC_* values by calling memmodel_base().
---
 gcc/config/riscv/riscv.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 17cdf705c328..9b5aedc77131 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3345,20 +3345,17 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc)
    acquire portion of memory model MODEL.  */
 
 static bool
-riscv_memmodel_needs_amo_acquire (enum memmodel model)
+riscv_memmodel_needs_amo_acquire (const enum memmodel model)
 {
   switch (model)
     {
       case MEMMODEL_ACQ_REL:
       case MEMMODEL_SEQ_CST:
-      case MEMMODEL_SYNC_SEQ_CST:
       case MEMMODEL_ACQUIRE:
       case MEMMODEL_CONSUME:
-      case MEMMODEL_SYNC_ACQUIRE:
 	return true;
 
       case MEMMODEL_RELEASE:
-      case MEMMODEL_SYNC_RELEASE:
       case MEMMODEL_RELAXED:
 	return false;
 
@@ -3371,20 +3368,17 @@ riscv_memmodel_needs_amo_acquire (enum memmodel model)
    implement the release portion of memory model MODEL.  */
 
 static bool
-riscv_memmodel_needs_release_fence (enum memmodel model)
+riscv_memmodel_needs_release_fence (const enum memmodel model)
 {
   switch (model)
     {
       case MEMMODEL_ACQ_REL:
       case MEMMODEL_SEQ_CST:
-      case MEMMODEL_SYNC_SEQ_CST:
       case MEMMODEL_RELEASE:
-      case MEMMODEL_SYNC_RELEASE:
 	return true;
 
       case MEMMODEL_ACQUIRE:
       case MEMMODEL_CONSUME:
-      case MEMMODEL_SYNC_ACQUIRE:
       case MEMMODEL_RELAXED:
 	return false;
 
@@ -3409,6 +3403,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 {
   machine_mode mode = GET_MODE (op);
   enum rtx_code code = GET_CODE (op);
+  const enum memmodel model = memmodel_base (INTVAL (op));
 
   switch (letter)
     {
@@ -3428,12 +3423,12 @@ riscv_print_operand (FILE *file, rtx op, int letter)
       break;
 
     case 'A':
-      if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op)))
+      if (riscv_memmodel_needs_amo_acquire (model))
 	fputs (".aq", file);
       break;
 
     case 'F':
-      if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op)))
+      if (riscv_memmodel_needs_release_fence (model))
 	fputs ("fence iorw,ow; ", file);
       break;
 
-- 
2.31.1


  reply	other threads:[~2021-04-26 12:45 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-26 12:45 [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Christoph Muellner
2021-04-26 12:45 ` Christoph Muellner [this message]
2021-04-26 12:45 ` [PATCH 02/10] RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265] Christoph Muellner
2021-04-26 12:45 ` [PATCH 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() " Christoph Muellner
2021-04-26 12:45 ` [PATCH 04/10] RISC-V: Don't use amoswap for atomic stores " Christoph Muellner
2021-04-26 12:45 ` [PATCH 05/10] RISC-V: Emit fences according to chosen memory model " Christoph Muellner
2021-04-26 12:45 ` [PATCH 06/10] RISC-V: Implement atomic_{load,store} " Christoph Muellner
2021-04-26 12:45 ` [PATCH 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 08/10] RISC-V: Add s.ext-consuming " Christoph Muellner
2021-04-26 12:45 ` [PATCH 09/10] RISC-V: Generate helpers for cbranch4 " Christoph Muellner
2021-04-26 14:39   ` Kito Cheng
2021-05-05 19:26     ` Christoph Müllner
2021-04-26 12:45 ` [PATCH 10/10] RISC-V: Provide programmatic implementation of CAS " Christoph Muellner
2021-04-27 15:17   ` Jim Wilson
2021-04-28 22:40 ` [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Jim Wilson

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