From: Kito Cheng <kito.cheng@sifive.com>
To: Christoph Muellner <cmuellner@gcc.gnu.org>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>, Jim Wilson <jimw@sifive.com>
Subject: Re: [PATCH 09/10] RISC-V: Generate helpers for cbranch4 [PR 100266]
Date: Mon, 26 Apr 2021 22:39:33 +0800 [thread overview]
Message-ID: <CALLt3TiZmdFZHCD5Dd=pPx-8KjgXCiW0EYpdyq3DRQSrTLLSbA@mail.gmail.com> (raw)
In-Reply-To: <20210426124552.3316789-10-cmuellner@gcc.gnu.org>
This patch is a good and simple improvement which could be an independent patch.
There is only 1 comment from me for this patch, could you also add @
to cbranch pattern for floating mode, I would prefer make the
gen_cbranch4 could handle floating mode for consistency.
So feel free to commit this patch once you have addressed my comment.
On Mon, Apr 26, 2021 at 8:46 PM Christoph Muellner
<cmuellner@gcc.gnu.org> wrote:
>
> On RISC-V we are facing the fact, that our conditional branches
> require Pmode conditions. Currently, we generate them explicitly
> with a check for Pmode and then calling the proper generator
> (i.e. gen_cbranchdi4 on RV64 and gen_cbranchsi4 on RV32).
> Let's make simplify this code by using gen_cbranch4 (Pmode).
>
> gcc/
> PR 100266
> * config/rsicv/riscv.c (riscv_block_move_loop): Simplify.
> * config/rsicv/riscv.md (cbranch<mode>4): Generate helpers.
> ---
> gcc/config/riscv/riscv.c | 5 +----
> gcc/config/riscv/riscv.md | 2 +-
> 2 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 87cdde73ae21..6e97b38db6db 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -3250,10 +3250,7 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
>
> /* Emit the loop condition. */
> test = gen_rtx_NE (VOIDmode, src_reg, final_src);
> - if (Pmode == DImode)
> - emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
> - else
> - emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
> + emit_jump_insn (gen_cbranch4 (Pmode, test, src_reg, final_src, label));
>
> /* Mop up any left-over bytes. */
> if (leftover)
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index c3687d57047b..52f8a321ac23 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1908,7 +1908,7 @@
> (label_ref (match_operand 1))
> (pc)))])
>
> -(define_expand "cbranch<mode>4"
> +(define_expand "@cbranch<mode>4"
> [(set (pc)
> (if_then_else (match_operator 0 "comparison_operator"
> [(match_operand:BR 1 "register_operand")
> --
> 2.31.1
>
next prev parent reply other threads:[~2021-04-26 14:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-26 12:45 [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 01/10] RISC-V: Simplify memory model code [PR 100265] Christoph Muellner
2021-04-26 12:45 ` [PATCH 02/10] RISC-V: Emit proper memory ordering suffixes for AMOs " Christoph Muellner
2021-04-26 12:45 ` [PATCH 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() " Christoph Muellner
2021-04-26 12:45 ` [PATCH 04/10] RISC-V: Don't use amoswap for atomic stores " Christoph Muellner
2021-04-26 12:45 ` [PATCH 05/10] RISC-V: Emit fences according to chosen memory model " Christoph Muellner
2021-04-26 12:45 ` [PATCH 06/10] RISC-V: Implement atomic_{load,store} " Christoph Muellner
2021-04-26 12:45 ` [PATCH 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 08/10] RISC-V: Add s.ext-consuming " Christoph Muellner
2021-04-26 12:45 ` [PATCH 09/10] RISC-V: Generate helpers for cbranch4 " Christoph Muellner
2021-04-26 14:39 ` Kito Cheng [this message]
2021-05-05 19:26 ` Christoph Müllner
2021-04-26 12:45 ` [PATCH 10/10] RISC-V: Provide programmatic implementation of CAS " Christoph Muellner
2021-04-27 15:17 ` Jim Wilson
2021-04-28 22:40 ` [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Jim Wilson
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