From: Christoph Muellner <cmuellner@gcc.gnu.org>
To: gcc-patches@gcc.gnu.org
Cc: Jim Wilson <jimw@sifive.com>, Kito Cheng <kito.cheng@sifive.com>,
Christoph Muellner <cmuellner@gcc.gnu.org>
Subject: [PATCH 03/10] RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265]
Date: Mon, 26 Apr 2021 14:45:45 +0200 [thread overview]
Message-ID: <20210426124552.3316789-4-cmuellner@gcc.gnu.org> (raw)
In-Reply-To: <20210426124552.3316789-1-cmuellner@gcc.gnu.org>
A previous patch took care, that the proper memory ordering suffixes
for AMOs are emitted. Therefore there is no reason to keep the fence
generation mechanism for release operations.
gcc/
PR 100265
* config/riscv/riscv.c (riscv_memmodel_needs_release_fence):
Remove function.
* config/riscv/riscv.c (riscv_print_operand): Remove
%F format specifier.
* config/riscv/sync.md: Remove %F format specifier uses.
---
gcc/config/riscv/riscv.c | 29 -----------------------------
gcc/config/riscv/sync.md | 16 ++++++++--------
2 files changed, 8 insertions(+), 37 deletions(-)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 881eab66a481..87cdde73ae21 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3366,29 +3366,6 @@ riscv_print_amo_memory_ordering_suffix (FILE *file, const enum memmodel model)
}
}
-/* Return true if a FENCE should be emitted to before a memory access to
- implement the release portion of memory model MODEL. */
-
-static bool
-riscv_memmodel_needs_release_fence (const enum memmodel model)
-{
- switch (model)
- {
- case MEMMODEL_ACQ_REL:
- case MEMMODEL_SEQ_CST:
- case MEMMODEL_RELEASE:
- return true;
-
- case MEMMODEL_ACQUIRE:
- case MEMMODEL_CONSUME:
- case MEMMODEL_RELAXED:
- return false;
-
- default:
- gcc_unreachable ();
- }
-}
-
/* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
'h' Print the high-part relocation associated with OP, after stripping
@@ -3396,7 +3373,6 @@ riscv_memmodel_needs_release_fence (const enum memmodel model)
'R' Print the low-part relocation associated with OP.
'C' Print the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
- 'F' Print a FENCE if the memory model requires a release.
'z' Print x0 if OP is zero, otherwise print OP normally.
'i' Print i if the operand is not a register. */
@@ -3428,11 +3404,6 @@ riscv_print_operand (FILE *file, rtx op, int letter)
riscv_print_amo_memory_ordering_suffix (file, model);
break;
- case 'F':
- if (riscv_memmodel_needs_release_fence (model))
- fputs ("fence iorw,ow; ", file);
- break;
-
case 'i':
if (code != REG)
fputs ("i", file);
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 747a799e2377..aeeb2e854b68 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -65,7 +65,7 @@
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_ATOMIC_STORE))]
"TARGET_ATOMIC"
- "%F2amoswap.<amo>%A2 zero,%z1,%0"
+ "amoswap.<amo>%A2 zero,%z1,%0"
[(set (attr "length") (const_int 8))])
(define_insn "atomic_<atomic_optab><mode>"
@@ -76,8 +76,8 @@
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F2amo<insn>.<amo>%A2 zero,%z1,%0"
- [(set (attr "length") (const_int 8))])
+ "amo<insn>.<amo>%A2 zero,%z1,%0"
+)
(define_insn "atomic_fetch_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -89,8 +89,8 @@
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
"TARGET_ATOMIC"
- "%F3amo<insn>.<amo>%A3 %0,%z2,%1"
- [(set (attr "length") (const_int 8))])
+ "amo<insn>.<amo>%A3 %0,%z2,%1"
+)
(define_insn "atomic_exchange<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -101,8 +101,8 @@
(set (match_dup 1)
(match_operand:GPR 2 "register_operand" "0"))]
"TARGET_ATOMIC"
- "%F3amoswap.<amo>%A3 %0,%z2,%1"
- [(set (attr "length") (const_int 8))])
+ "amoswap.<amo>%A3 %0,%z2,%1"
+)
(define_insn "atomic_cas_value_strong<mode>"
[(set (match_operand:GPR 0 "register_operand" "=&r")
@@ -115,7 +115,7 @@
UNSPEC_COMPARE_AND_SWAP))
(clobber (match_scratch:GPR 6 "=&r"))]
"TARGET_ATOMIC"
- "%F5 1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
+ "1: lr.<amo>%A5 %0,%1; bne %0,%z2,1f; sc.<amo>%A4 %6,%z3,%1; bnez %6,1b; 1:"
[(set (attr "length") (const_int 20))])
(define_expand "atomic_compare_and_swap<mode>"
--
2.31.1
next prev parent reply other threads:[~2021-04-26 12:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-26 12:45 [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 01/10] RISC-V: Simplify memory model code [PR 100265] Christoph Muellner
2021-04-26 12:45 ` [PATCH 02/10] RISC-V: Emit proper memory ordering suffixes for AMOs " Christoph Muellner
2021-04-26 12:45 ` Christoph Muellner [this message]
2021-04-26 12:45 ` [PATCH 04/10] RISC-V: Don't use amoswap for atomic stores " Christoph Muellner
2021-04-26 12:45 ` [PATCH 05/10] RISC-V: Emit fences according to chosen memory model " Christoph Muellner
2021-04-26 12:45 ` [PATCH 06/10] RISC-V: Implement atomic_{load,store} " Christoph Muellner
2021-04-26 12:45 ` [PATCH 07/10] RISC-V: Model INSNs for LR and SC [PR 100266] Christoph Muellner
2021-04-26 12:45 ` [PATCH 08/10] RISC-V: Add s.ext-consuming " Christoph Muellner
2021-04-26 12:45 ` [PATCH 09/10] RISC-V: Generate helpers for cbranch4 " Christoph Muellner
2021-04-26 14:39 ` Kito Cheng
2021-05-05 19:26 ` Christoph Müllner
2021-04-26 12:45 ` [PATCH 10/10] RISC-V: Provide programmatic implementation of CAS " Christoph Muellner
2021-04-27 15:17 ` Jim Wilson
2021-04-28 22:40 ` [PATCH 00/10] [RISC-V] Atomics improvements [PR100265/PR100266] Jim Wilson
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