[PATCH] MIPS: use 8bit for IPL in Cause register

[PATCH] MIPS: use 8bit for IPL in Cause register

[YunQiang Su]

Since MIPS r2, the IPL section in Cause register has been expand
to 8bit instead of 6bit.

Since __attribute__((interrupt)) is only supported for r2+,
we don't need to detect the target.

gcc/ChangeLog:

	* config/mips/mips.cc (mips_expand_prologue):
	  IPL is 8bit for r2+.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..bde88fb8e5a 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@ mips_expand_prologue (void)
 	      if (!cfun->machine->keep_interrupts_masked_p
 		  && cfun->machine->int_mask == INT_MASK_EIC)
 		emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-				       GEN_INT (6),
+				       GEN_INT (8),
 				       GEN_INT (SR_IPL),
 				       gen_rtx_REG (SImode, K0_REG_NUM)));
 
-- 
2.30.2

Re: [PATCH] MIPS: use 8bit for IPL in Cause register

[Maciej W. Rozycki]

On Wed, 26 Jan 2022, YunQiang Su wrote:

> Since MIPS r2, the IPL section in Cause register has been expand
> to 8bit instead of 6bit.

 Hmm, I cannot see it in my copy of the architecture manual I'm afraid.  
The interpretation may have changed, but the field is still 6-bit (not 
counting the software interrupts).  Now the MCU ASE does expand the IPL 
field, but we can't rely on that here, not at least unconditionally, and 
then MCU is MIPSr3+.

 What problem are you trying to solve anyway?

  Maciej

[PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[YunQiang Su]

If MIPS MCU extension is enable, the IPL section in Cause register
has been expand to 8bit instead of 6bit.

gcc/ChangeLog:

	* config/mips/mips.cc (mips_expand_prologue):
	  IPL is 8bit for MCU ASE.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..d823c459b75 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@ mips_expand_prologue (void)
 	      if (!cfun->machine->keep_interrupts_masked_p
 		  && cfun->machine->int_mask == INT_MASK_EIC)
 		emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-				       GEN_INT (6),
+				       TARGET_MCU ? GEN_INT (8) : GEN_INT (6),
 				       GEN_INT (SR_IPL),
 				       gen_rtx_REG (SImode, K0_REG_NUM)));
 
-- 
2.30.2

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[Jeff Law]

On 2/8/2022 8:18 PM, YunQiang Su wrote:
> If MIPS MCU extension is enable, the IPL section in Cause register
> has been expand to 8bit instead of 6bit.
>
> gcc/ChangeLog:
>
> 	* config/mips/mips.cc (mips_expand_prologue):
> 	  IPL is 8bit for MCU ASE.
OK
jeff

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[Maciej W. Rozycki]

On Fri, 11 Feb 2022, Jeff Law wrote:

> > If MIPS MCU extension is enable, the IPL section in Cause register
> > has been expand to 8bit instead of 6bit.
> > 
> > gcc/ChangeLog:
> > 
> > 	* config/mips/mips.cc (mips_expand_prologue):
> > 	  IPL is 8bit for MCU ASE.
> OK

 But this is still wrong AFAICT.

 The mask is applied to the CP0 Status register according to the comment, 
but the layout of the interrupt bit-field is different between the CP0 
Status and the CP0 Cause registers, so you can't just extract it from one 
of the two registers and directly apply to the other.

 I would like to know how this code has been verified.

  Maciej

[PATCH v3] MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU

[YunQiang Su]

If MIPS MCU extension is enable, the IPL section in Cause and Status
registers has been expand to 8bit instead of 6bit.

In Cause: the bits are 10-17.
In Status: the bits are 10-16 and 18.

MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.

gcc/ChangeLog:

	* config/mips/mips.cc (mips_expand_prologue):
	  IPL is 8bit for MCU ASE.
---
 gcc/config/mips/mips.cc | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index a1c4b437cd4..91e1e964f94 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12254,10 +12254,22 @@ mips_expand_prologue (void)
 	      /* Insert the RIPL into our copy of SR (k1) as the new IPL.  */
 	      if (!cfun->machine->keep_interrupts_masked_p
 		  && cfun->machine->int_mask == INT_MASK_EIC)
-		emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-				       GEN_INT (6),
+		{
+		  emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
+				       TARGET_MCU ? GEN_INT (7) : GEN_INT (6),
 				       GEN_INT (SR_IPL),
 				       gen_rtx_REG (SImode, K0_REG_NUM)));
+		  if (TARGET_MCU)
+		    {
+		      emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
+					gen_rtx_REG (SImode, K0_REG_NUM),
+					GEN_INT (7)));
+		      emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
+				       GEN_INT (1),
+				       GEN_INT (SR_IPL+8),
+				       gen_rtx_REG (SImode, K0_REG_NUM)));
+		    }
+		}
 
 	      /* Clear all interrupt mask bits up to and including the
 		 handler's interrupt line.  */
-- 
2.30.2

Re: [PATCH v2] MIPS: IPL is 8bit in Cause register if TARGET_MCU

[YunQiang Su]

在 2022/2/12 16:47, Maciej W. Rozycki 写道:
> On Fri, 11 Feb 2022, Jeff Law wrote:
> 
>>> If MIPS MCU extension is enable, the IPL section in Cause register
>>> has been expand to 8bit instead of 6bit.
>>>
>>> gcc/ChangeLog:
>>>
>>> 	* config/mips/mips.cc (mips_expand_prologue):
>>> 	  IPL is 8bit for MCU ASE.
>> OK
> 
>   But this is still wrong AFAICT.
> 

Yes. you are right.

>   The mask is applied to the CP0 Status register according to the comment,
> but the layout of the interrupt bit-field is different between the CP0
> Status and the CP0 Cause registers, so you can't just extract it from one
> of the two registers and directly apply to the other.
> 

Since our case has 128 interrupts, so I didn't find this problem.

>   I would like to know how this code has been verified.

And now new version sent with the test with 256 interrupts.

See v3 please.

> 
>    Maciej
> .

Re: [PATCH v3] MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU

[Maciej W. Rozycki]

On Tue, 15 Mar 2022, YunQiang Su wrote:

> If MIPS MCU extension is enable, the IPL section in Cause and Status
> registers has been expand to 8bit instead of 6bit.
> 
> In Cause: the bits are 10-17.
> In Status: the bits are 10-16 and 18.
> 
> MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.

 I can see you have committed this change, but I cannot see an approval 
posted to the mailing list.  Who has approved your change?

> diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
> index a1c4b437cd4..91e1e964f94 100644
> --- a/gcc/config/mips/mips.cc
> +++ b/gcc/config/mips/mips.cc
> @@ -12254,10 +12254,22 @@ mips_expand_prologue (void)
>  	      /* Insert the RIPL into our copy of SR (k1) as the new IPL.  */
>  	      if (!cfun->machine->keep_interrupts_masked_p
>  		  && cfun->machine->int_mask == INT_MASK_EIC)
> -		emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
> -				       GEN_INT (6),
> +		{
> +		  emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
> +				       TARGET_MCU ? GEN_INT (7) : GEN_INT (6),
>  				       GEN_INT (SR_IPL),
>  				       gen_rtx_REG (SImode, K0_REG_NUM)));
> +		  if (TARGET_MCU)
> +		    {
> +		      emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
> +					gen_rtx_REG (SImode, K0_REG_NUM),
> +					GEN_INT (7)));
> +		      emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
> +				       GEN_INT (1),
> +				       GEN_INT (SR_IPL+8),
> +				       gen_rtx_REG (SImode, K0_REG_NUM)));
> +		    }
> +		}

 While code generation has been corrected your change has code formatting 
issues which should have been addressed before committing.  A test case 
should have been made too.

  Maciej