* [PATCH] RISC-V: Fix RVV machine mode attribute configuration
@ 2022-12-14 7:01 juzhe.zhong
2022-12-17 1:48 ` Jeff Law
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2022-12-14 7:01 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
The attribute configuration of each machine mode are support in the previous patch.
I noticed some of them are not correct during VSETVL PASS testsing.
Correct them in the single patch now.
gcc/ChangeLog:
* config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes.
---
gcc/config/riscv/riscv-vector-switch.def | 38 ++++++++++++------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def
index a51f45be487..ec12be84661 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -95,16 +95,16 @@ TODO: FP16 vector needs support of 'zvfh', we don't support it yet. */
#endif
/* Mask modes. Disable VNx64BImode when TARGET_MIN_VLEN == 32. */
-ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_F8, 64, LMUL_RESERVED, 0)
-ENTRY (VNx32BI, true, LMUL_F4, 32, LMUL_RESERVED, 0)
-ENTRY (VNx16BI, true, LMUL_F2, 16, LMUL_RESERVED, 0)
-ENTRY (VNx8BI, true, LMUL_1, 8, LMUL_RESERVED, 0)
-ENTRY (VNx4BI, true, LMUL_2, 4, LMUL_RESERVED, 0)
-ENTRY (VNx2BI, true, LMUL_4, 2, LMUL_RESERVED, 0)
-ENTRY (VNx1BI, true, LMUL_8, 1, LMUL_RESERVED, 0)
+ENTRY (VNx64BI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1)
+ENTRY (VNx32BI, true, LMUL_8, 1, LMUL_4, 2)
+ENTRY (VNx16BI, true, LMUL_4, 2, LMUL_2, 4)
+ENTRY (VNx8BI, true, LMUL_2, 4, LMUL_1, 8)
+ENTRY (VNx4BI, true, LMUL_1, 8, LMUL_F2, 16)
+ENTRY (VNx2BI, true, LMUL_F2, 16, LMUL_F4, 32)
+ENTRY (VNx1BI, true, LMUL_F4, 32, LMUL_F8, 64)
/* SEW = 8. Disable VNx64QImode when TARGET_MIN_VLEN == 32. */
-ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_8, 1, LMUL_RESERVED, 0)
+ENTRY (VNx64QI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 1)
ENTRY (VNx32QI, true, LMUL_8, 1, LMUL_4, 2)
ENTRY (VNx16QI, true, LMUL_4, 2, LMUL_2, 4)
ENTRY (VNx8QI, true, LMUL_2, 4, LMUL_1, 8)
@@ -113,7 +113,7 @@ ENTRY (VNx2QI, true, LMUL_F2, 16, LMUL_F4, 32)
ENTRY (VNx1QI, true, LMUL_F4, 32, LMUL_F8, 64)
/* SEW = 16. Disable VNx32HImode when TARGET_MIN_VLEN == 32. */
-ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_8, 2, LMUL_RESERVED, 0)
+ENTRY (VNx32HI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 2)
ENTRY (VNx16HI, true, LMUL_8, 2, LMUL_4, 4)
ENTRY (VNx8HI, true, LMUL_4, 4, LMUL_2, 8)
ENTRY (VNx4HI, true, LMUL_2, 8, LMUL_1, 16)
@@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32)
ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64)
/* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */
-ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0)
+ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2)
ENTRY (VNx16HF, false, LMUL_8, 2, LMUL_4, 4)
ENTRY (VNx8HF, false, LMUL_4, 4, LMUL_2, 8)
ENTRY (VNx4HF, false, LMUL_2, 8, LMUL_1, 16)
@@ -131,18 +131,18 @@ ENTRY (VNx1HF, false, LMUL_F2, 32, LMUL_F4, 64)
/* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32.
For single-precision floating-point, we need TARGET_VECTOR_FP32 ==
RVV_ENABLE. */
-ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_8, 4, LMUL_RESERVED, 0)
+ENTRY (VNx16SI, TARGET_MIN_VLEN > 32, LMUL_RESERVED, 0, LMUL_8, 4)
ENTRY (VNx8SI, true, LMUL_8, 4, LMUL_4, 8)
-ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 4)
-ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 2)
-ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 1)
+ENTRY (VNx4SI, true, LMUL_4, 8, LMUL_2, 16)
+ENTRY (VNx2SI, true, LMUL_2, 16, LMUL_1, 32)
+ENTRY (VNx1SI, true, LMUL_1, 32, LMUL_F2, 64)
-ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_8, 4,
- LMUL_RESERVED, 0)
+ENTRY (VNx16SF, TARGET_VECTOR_FP32 && (TARGET_MIN_VLEN > 32), LMUL_RESERVED, 0,
+ LMUL_8, 4)
ENTRY (VNx8SF, TARGET_VECTOR_FP32, LMUL_8, 4, LMUL_4, 8)
-ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 4)
-ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 2)
-ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 1)
+ENTRY (VNx4SF, TARGET_VECTOR_FP32, LMUL_4, 8, LMUL_2, 16)
+ENTRY (VNx2SF, TARGET_VECTOR_FP32, LMUL_2, 16, LMUL_1, 32)
+ENTRY (VNx1SF, TARGET_VECTOR_FP32, LMUL_1, 32, LMUL_F2, 64)
/* SEW = 64. Enable when TARGET_MIN_VLEN > 32.
For double-precision floating-point, we need TARGET_VECTOR_FP64 ==
--
2.36.3
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration
2022-12-14 7:01 [PATCH] RISC-V: Fix RVV machine mode attribute configuration juzhe.zhong
@ 2022-12-17 1:48 ` Jeff Law
2022-12-17 1:51 ` 钟居哲
0 siblings, 1 reply; 4+ messages in thread
From: Jeff Law @ 2022-12-17 1:48 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, palmer
On 12/14/22 00:01, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> The attribute configuration of each machine mode are support in the previous patch.
> I noticed some of them are not correct during VSETVL PASS testsing.
> Correct them in the single patch now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes.
>
> @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32)
> ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64)
>
> /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */
> -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0)
> +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2)
Is there any value in making VNx32HF dependent on TARGET_MIN_VLEN > 32
like we're doing for VNx32HI? In the past I've found it useful to have
HI, HF, BF behave identically as much as possible.
You call. The patch is OK either way.
jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration
2022-12-17 1:48 ` Jeff Law
@ 2022-12-17 1:51 ` 钟居哲
2022-12-19 15:05 ` Kito Cheng
0 siblings, 1 reply; 4+ messages in thread
From: 钟居哲 @ 2022-12-17 1:51 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: kito.cheng, palmer
[-- Attachment #1: Type: text/plain, Size: 1493 bytes --]
Actually, I don't check and test HF carefully since I disable them.
Kito ask me to disable all HF modes since zvfhmin is no ratified and GCC
doesn't allow any un-ratified ISA. You can see vector-iterator.md that all
RVV modes supported including QI HI SI DI SF DF excluding HF and BF.
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2022-12-17 09:48
To: juzhe.zhong; gcc-patches
CC: kito.cheng; palmer
Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration
On 12/14/22 00:01, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> The attribute configuration of each machine mode are support in the previous patch.
> I noticed some of them are not correct during VSETVL PASS testsing.
> Correct them in the single patch now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-switch.def (ENTRY): Correct attributes.
>
> @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32)
> ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64)
>
> /* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported. */
> -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0)
> +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2)
Is there any value in making VNx32HF dependent on TARGET_MIN_VLEN > 32
like we're doing for VNx32HI? In the past I've found it useful to have
HI, HF, BF behave identically as much as possible.
You call. The patch is OK either way.
jeff
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration
2022-12-17 1:51 ` 钟居哲
@ 2022-12-19 15:05 ` Kito Cheng
0 siblings, 0 replies; 4+ messages in thread
From: Kito Cheng @ 2022-12-19 15:05 UTC (permalink / raw)
To: 钟居哲; +Cc: Jeff Law, gcc-patches, palmer
[-- Attachment #1: Type: text/plain, Size: 1666 bytes --]
Commited to trunk.
钟居哲 <juzhe.zhong@rivai.ai> 於 2022年12月17日 週六 09:52 寫道：
> Actually, I don't check and test HF carefully since I disable them.
> Kito ask me to disable all HF modes since zvfhmin is no ratified and GCC
> doesn't allow any un-ratified ISA. You can see vector-iterator.md that all
> RVV modes supported including QI HI SI DI SF DF excluding HF and BF.
>
>
>
> juzhe.zhong@rivai.ai
>
> From: Jeff Law
> Date: 2022-12-17 09:48
> To: juzhe.zhong; gcc-patches
> CC: kito.cheng; palmer
> Subject: Re: [PATCH] RISC-V: Fix RVV machine mode attribute configuration
>
>
> On 12/14/22 00:01, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > The attribute configuration of each machine mode are support in the
> previous patch.
> > I noticed some of them are not correct during VSETVL PASS testsing.
> > Correct them in the single patch now.
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv-vector-switch.def (ENTRY): Correct
> attributes.
> >
>
>
>
> > @@ -121,7 +121,7 @@ ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32)
> > ENTRY (VNx1HI, true, LMUL_F2, 32, LMUL_F4, 64)
> >
> > /* TODO:Disable all FP16 vector, enable them when 'zvfh' is
> supported. */
> > -ENTRY (VNx32HF, false, LMUL_8, 2, LMUL_RESERVED, 0)
> > +ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2)
> Is there any value in making VNx32HF dependent on TARGET_MIN_VLEN > 32
> like we're doing for VNx32HI? In the past I've found it useful to have
> HI, HF, BF behave identically as much as possible.
>
> You call. The patch is OK either way.
>
> jeff
>
>
>
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-12-19 15:06 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-14 7:01 [PATCH] RISC-V: Fix RVV machine mode attribute configuration juzhe.zhong
2022-12-17 1:48 ` Jeff Law
2022-12-17 1:51 ` 钟居哲
2022-12-19 15:05 ` Kito Cheng
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).