From: Jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@dabbelt.com,
christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com,
mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com,
charlie.keaney@embecosm.com, simon.cook@embecosm.com,
tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com,
sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn,
shihua@iscas.ac.cn, shiyulong@iscas.ac.cn,
chenyixuan@iscas.ac.cn, Jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH 1/5] RISC-V: Minimal support for ZC extensions.
Date: Thu, 6 Apr 2023 14:21:14 +0800 [thread overview]
Message-ID: <20230406062118.47431-2-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20230406062118.47431-1-jiawei@iscas.ac.cn>
This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New extensions.
* config/riscv/riscv-opts.h (MASK_ZCA): New mask.
(MASK_ZCB): Ditto.
(MASK_ZCE): Ditto.
(MASK_ZCF): Ditto.
(MASK_ZCD): Ditto.
(MASK_ZCMP): Ditto.
(MASK_ZCMT): Ditto.
(TARGET_ZCA): New target.
(TARGET_ZCB): Ditto.
(TARGET_ZCE): Ditto.
(TARGET_ZCF): Ditto.
(TARGET_ZCD): Ditto.
(TARGET_ZCMP): Ditto.
(TARGET_ZCMT): Ditto.
* config/riscv/riscv.opt: New target variable.
---
gcc/common/config/riscv/riscv-common.cc | 39 +++++++++++++++++++++++++
gcc/config/riscv/riscv-opts.h | 16 ++++++++++
gcc/config/riscv/riscv.opt | 3 ++
3 files changed, 58 insertions(+)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 2fc0f8bffc1..933c54edded 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -108,6 +108,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
+ {"zce", "zca"},
+ {"zce", "zcb"},
+ {"zce", "zcmp"},
+ {"zce", "zcmt"},
+ {"zcf", "zca"},
+ {"zcd", "zca"},
+ {"zcb", "zca"},
+ {"zcmp", "zca"},
+ {"zcmt", "zca"},
+
{NULL, NULL}
};
@@ -219,6 +229,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zca", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcb", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zce", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcf", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcd", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+ {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+
{"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
{"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1151,14 +1169,26 @@ riscv_subset_list::parse (const char *arch, location_t loc)
subset_list->handle_implied_ext (itr);
}
+ /* Zce only imply zcf when 'f' extension exist. */
+ if (subset_list->lookup ("zce") != NULL
+ && subset_list->lookup ("f") != NULL
+ && subset_list->lookup ("zcf") == NULL)
+ subset_list->add ("zcf", false);
+
subset_list->handle_combine_ext ();
+ if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64)
+ error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only"
+ , arch);
+
if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
"extensions", arch);
return subset_list;
+
+
fail:
delete subset_list;
return NULL;
@@ -1262,6 +1292,15 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
+ /* Code-size reduction extensions. */
+ {"zca", &gcc_options::x_riscv_zc_subext, MASK_ZCA},
+ {"zcb", &gcc_options::x_riscv_zc_subext, MASK_ZCB},
+ {"zce", &gcc_options::x_riscv_zc_subext, MASK_ZCE},
+ {"zcf", &gcc_options::x_riscv_zc_subext, MASK_ZCF},
+ {"zcd", &gcc_options::x_riscv_zc_subext, MASK_ZCD},
+ {"zcmp", &gcc_options::x_riscv_zc_subext, MASK_ZCMP},
+ {"zcmt", &gcc_options::x_riscv_zc_subext, MASK_ZCMT},
+
{"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
{"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index cf0cd669be4..101d87d38b1 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -175,6 +175,22 @@ enum stack_protector_guard {
#define MASK_ZMMUL (1 << 0)
#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
+#define MASK_ZCA (1 << 0)
+#define MASK_ZCB (1 << 1)
+#define MASK_ZCE (1 << 2)
+#define MASK_ZCF (1 << 3)
+#define MASK_ZCD (1 << 4)
+#define MASK_ZCMP (1 << 5)
+#define MASK_ZCMT (1 << 6)
+
+#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
+#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
+#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
+#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
+#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
+#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
+#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
+
#define MASK_SVINVAL (1 << 0)
#define MASK_SVNAPOT (1 << 1)
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index ff1dd4ddd4f..60c07b3b614 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -232,6 +232,9 @@ int riscv_zf_subext
TargetVariable
int riscv_zm_subext
+TargetVariable
+int riscv_zc_subext
+
TargetVariable
int riscv_sv_subext
--
2.25.1
next prev parent reply other threads:[~2023-04-06 6:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 6:21 [PATCH 0/5] RISC-V: Support ZC* extensions Jiawei
2023-04-06 6:21 ` Jiawei [this message]
2023-05-04 8:33 ` [PATCH 1/5] RISC-V: Minimal support for ZC extensions Kito Cheng
2023-04-06 6:21 ` [PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions Jiawei
2023-04-06 6:21 ` [PATCH 3/5] RISC-V: Add ZC* test for march args being passed Jiawei
2023-05-04 8:37 ` Kito Cheng
2023-04-06 6:21 ` [PATCH 4/5] RISC-V: Add Zcmp extension supports Jiawei
2023-05-04 9:03 ` Kito Cheng
[not found] ` <07720619-dd69-4816-987e-ff0e14d9a348.>
2023-05-12 8:53 ` Sinan
2023-04-06 6:21 ` [PATCH 5/5] RISC-V: Add ZCMP push/pop testcases Jiawei
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