From: Jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@dabbelt.com,
christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com,
mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com,
charlie.keaney@embecosm.com, simon.cook@embecosm.com,
tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com,
sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn,
shihua@iscas.ac.cn, shiyulong@iscas.ac.cn,
chenyixuan@iscas.ac.cn, Jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions.
Date: Thu, 6 Apr 2023 14:21:15 +0800 [thread overview]
Message-ID: <20230406062118.47431-3-jiawei@iscas.ac.cn> (raw)
In-Reply-To: <20230406062118.47431-1-jiawei@iscas.ac.cn>
This patch enables the compressible features with ZC* extensions.
Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
gcc/ChangeLog:
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
Enable compressed builtins when ZC* extensions enabled.
* config/riscv/riscv-shorten-memrefs.cc:
Enable shorten_memrefs pass when ZC* extensions enabled.
* config/riscv/riscv.cc (riscv_compressed_reg_p):
Enable compressible registers when ZC* extensions enabled.
(riscv_rtx_costs):
Allow adjusting rtx costs when ZC* extensions enabled.
(riscv_address_cost):
Allow adjusting address cost when ZC* extensions enabled.
(riscv_first_stack_step):
Allow compression of the register saves without
adding extra instructions.
* config/riscv/riscv.h (FUNCTION_BOUNDARY):
Adjusts function boundary to 16 bits when ZC* extensions enabled.
---
gcc/config/riscv/riscv-c.cc | 2 +-
gcc/config/riscv/riscv-shorten-memrefs.cc | 3 ++-
gcc/config/riscv/riscv.cc | 16 +++++++++-------
gcc/config/riscv/riscv.h | 2 +-
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 6ad562dcb8b..2937c160071 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
{
builtin_define ("__riscv");
- if (TARGET_RVC)
+ if (TARGET_RVC || TARGET_ZCA)
builtin_define ("__riscv_compressed");
if (TARGET_RVE)
diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 8f10d24ec39..27803e2c657 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -65,7 +65,8 @@ public:
/* opt_pass methods: */
virtual bool gate (function *)
{
- return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0;
+ return (TARGET_RVC || TARGET_ZCA)
+ && riscv_mshorten_memrefs && optimize > 0;
}
virtual unsigned int execute (function *);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..5f8cbfc15ed 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1118,8 +1118,9 @@ static bool
riscv_compressed_reg_p (int regno)
{
/* x8-x15/f8-f15 are compressible registers. */
- return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
- || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
+ return ((TARGET_RVC || TARGET_ZCA)
+ && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
+ || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
}
/* Return true if x is an unsigned 5-bit immediate scaled by 4. */
@@ -2323,8 +2324,9 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
/* When optimizing for size, make uncompressible 32-bit addresses
more expensive so that compressible 32-bit addresses are
preferred. */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
- && !riscv_compressed_lw_address_p (XEXP (x, 0)))
+ if ((TARGET_RVC || TARGET_ZCA) && !speed && riscv_mshorten_memrefs
+ && mode == SImode
+ && !riscv_compressed_lw_address_p (XEXP (x, 0)))
cost++;
*total = COSTS_N_INSNS (cost + tune_param->memory_cost);
@@ -2735,8 +2737,8 @@ riscv_address_cost (rtx addr, machine_mode mode,
{
/* When optimizing for size, make uncompressible 32-bit addresses more
* expensive so that compressible 32-bit addresses are preferred. */
- if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
- && !riscv_compressed_lw_address_p (addr))
+ if ((TARGET_RVC || TARGET_ZCA) && !speed && riscv_mshorten_memrefs
+ && mode == SImode && !riscv_compressed_lw_address_p (addr))
return riscv_address_insns (addr, mode, false) + 1;
return riscv_address_insns (addr, mode, false);
}
@@ -5202,7 +5204,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame)
&& frame_total_constant_size % IMM_REACH >= min_first_step)
return frame_total_constant_size % IMM_REACH;
- if (TARGET_RVC)
+ if (TARGET_RVC || TARGET_ZCA)
{
/* If we need two subtracts, and one is small enough to allow compressed
loads and stores, then put that one first. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 66fb07d6652..d05b1d59853 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -183,7 +183,7 @@ ASM_MISA_SPEC
#define PARM_BOUNDARY BITS_PER_WORD
/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
+#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
/* The smallest supported stack boundary the calling convention supports. */
#define STACK_BOUNDARY \
--
2.25.1
next prev parent reply other threads:[~2023-04-06 6:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 6:21 [PATCH 0/5] RISC-V: Support " Jiawei
2023-04-06 6:21 ` [PATCH 1/5] RISC-V: Minimal support for ZC extensions Jiawei
2023-05-04 8:33 ` Kito Cheng
2023-04-06 6:21 ` Jiawei [this message]
2023-04-06 6:21 ` [PATCH 3/5] RISC-V: Add ZC* test for march args being passed Jiawei
2023-05-04 8:37 ` Kito Cheng
2023-04-06 6:21 ` [PATCH 4/5] RISC-V: Add Zcmp extension supports Jiawei
2023-05-04 9:03 ` Kito Cheng
[not found] ` <07720619-dd69-4816-987e-ff0e14d9a348.>
2023-05-12 8:53 ` Sinan
2023-04-06 6:21 ` [PATCH 5/5] RISC-V: Add ZCMP push/pop testcases Jiawei
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