From: Kito Cheng <kito.cheng@gmail.com>
To: Jiawei <jiawei@iscas.ac.cn>
Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com,
palmer@dabbelt.com, christoph.muellner@vrull.eu,
jeremy.bennett@embecosm.com, mary.bennett@embecosm.com,
nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com,
simon.cook@embecosm.com, tariq.kurd@codasip.com,
ibrahim.abu.kharmeh1@huawei.com, sinan.lin@linux.alibaba.com,
wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn,
shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn
Subject: Re: [PATCH 3/5] RISC-V: Add ZC* test for march args being passed.
Date: Thu, 4 May 2023 16:37:18 +0800 [thread overview]
Message-ID: <CA+yXCZCk55MU4Ja7mD7hzRYEwAnbSQB0xzvpB0L-+J1xfsOjpg@mail.gmail.com> (raw)
In-Reply-To: <20230406062118.47431-4-jiawei@iscas.ac.cn>
Plz drop those testcase which just contain inline asm in foo, that
should belong to binutils's testsuite IMO.
On Thu, Apr 6, 2023 at 2:23 PM Jiawei <jiawei@iscas.ac.cn> wrote:
>
> From: Charlie Keaney <charlie.keaney@embecosm.com>
>
> Add all ZC* extensions march args tests.
>
> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Co-Authored by: Jiawei <jiawei@iscas.ac.cn>
> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> Co-Authored by: Simon Cook <simon.cook@embecosm.com>
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-20.c: New test.
> * gcc.target/riscv/arch-21.c: New test.
> * gcc.target/riscv/zc-zca-arch.c: New test.
> * gcc.target/riscv/zc-zcb-arch.c: New test.
> * gcc.target/riscv/zc-zcb-m-arch.c: New test.
> * gcc.target/riscv/zc-zcb-zba-arch.c: New test.
> * gcc.target/riscv/zc-zcb-zbb-arch.c: New test.
> * gcc.target/riscv/zc-zcf-arch.c: New test.
> * gcc.target/riscv/zc-zcmp-arch.c: New test.
> * gcc.target/riscv/zc-zcmpe-arch.c: New test.
> * gcc.target/riscv/zc-zcmt-arch.c: New test.
> ---
> gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++++
> gcc/testsuite/gcc.target/riscv/arch-21.c | 5 +++++
> gcc/testsuite/gcc.target/riscv/zc-zca-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c | 9 +++++++++
> gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c | 9 +++++++++
> 11 files changed, 91 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-20.c b/gcc/testsuite/gcc.target/riscv/arch-20.c
> new file mode 100644
> index 00000000000..3be4ade65a7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-20.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
> +int foo() {}
> +/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
> +/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-21.c b/gcc/testsuite/gcc.target/riscv/arch-21.c
> new file mode 100644
> index 00000000000..cecce06e474
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-21.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
> +int foo() {}
> +/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
> +/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
> new file mode 100644
> index 00000000000..bcb8321e709
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32i_zca -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("c.sw x9, 32(x10)");
> +}
> +
> +/* { dg-final { scan-assembler "c.sw x9, 32\\(x10\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
> new file mode 100644
> index 00000000000..54d4dff63ea
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32i_zcb -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("c.lbu x9,1(x8)");
> +}
> +
> +/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
> new file mode 100644
> index 00000000000..f23fe304607
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32im_zcb -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("c.lbu x9,1(x8)");
> +}
> +
> +/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
> new file mode 100644
> index 00000000000..6b4a8762078
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32i_zcb_zba -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("c.lbu x9,1(x8)");
> +}
> +
> +/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
> new file mode 100644
> index 00000000000..53f8dba80d3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32i_zcb_zbb -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("c.lbu x9,1(x8)");
> +}
> +
> +/* { dg-final { scan-assembler "c.lbu x9,1\\(x8\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
> new file mode 100644
> index 00000000000..dcdadc87b79
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32i_zcf -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("c.flw fa0, 0(a0)");
> +}
> +
> +/* { dg-final { scan-assembler "c.flw fa0, 0\\(a0\\)" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
> new file mode 100644
> index 00000000000..17c54d6b2af
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32i_zcb_zcmp -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("cm.push {ra,s0-s3},-32");
> +}
> +
> +/* { dg-final { scan-assembler "cm.push {ra,s0-s3},-32" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
> new file mode 100644
> index 00000000000..68547c9a820
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32e_zcb_zcmp -mabi=ilp32e" } */
> +
> +int foo()
> +{
> + asm("cm.push {ra,s0-s3},-32");
> +}
> +
> +/* { dg-final { scan-assembler "cm.push {ra,s0-s3},-32" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c b/gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
> new file mode 100644
> index 00000000000..133de0c250c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32im_zcmt -mabi=ilp32" } */
> +
> +int foo()
> +{
> + asm("cm.jt 0");
> +}
> +
> +/* { dg-final { scan-assembler "cm.jt 0" } } */
> --
> 2.25.1
>
next prev parent reply other threads:[~2023-05-04 8:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 6:21 [PATCH 0/5] RISC-V: Support ZC* extensions Jiawei
2023-04-06 6:21 ` [PATCH 1/5] RISC-V: Minimal support for ZC extensions Jiawei
2023-05-04 8:33 ` Kito Cheng
2023-04-06 6:21 ` [PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions Jiawei
2023-04-06 6:21 ` [PATCH 3/5] RISC-V: Add ZC* test for march args being passed Jiawei
2023-05-04 8:37 ` Kito Cheng [this message]
2023-04-06 6:21 ` [PATCH 4/5] RISC-V: Add Zcmp extension supports Jiawei
2023-05-04 9:03 ` Kito Cheng
[not found] ` <07720619-dd69-4816-987e-ff0e14d9a348.>
2023-05-12 8:53 ` Sinan
2023-04-06 6:21 ` [PATCH 5/5] RISC-V: Add ZCMP push/pop testcases Jiawei
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