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From: Jiawei <jiawei@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@sifive.com, palmer@dabbelt.com,
	christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com,
	mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com,
	charlie.keaney@embecosm.com, simon.cook@embecosm.com,
	tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com,
	sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn,
	shihua@iscas.ac.cn, shiyulong@iscas.ac.cn,
	chenyixuan@iscas.ac.cn, Jiawei <jiawei@iscas.ac.cn>
Subject: [PATCH 0/5] RISC-V: Support ZC* extensions.
Date: Thu,  6 Apr 2023 14:21:13 +0800	[thread overview]
Message-ID: <20230406062118.47431-1-jiawei@iscas.ac.cn> (raw)

RISC-V Code Size Reduction(ZC*) extensions is a group of extensions 
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]

The implementation of the RISC-V Code Size Reduction extension in GCC is
an important step towards making the RISC-V architecture more efficient.

The cooperation with OpenHW group has played a crucial role in this effort,
with facilitating the implementation, testing and validation. Currently
works can also find in OpenHW group's github repo.[2]

Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the 
specification, and Jeremy Bennett's patient guidance throughout the whole 
development process.

[1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

[2] github.com/openhwgroup/corev-gcc

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by:	Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

  RISC-V: Minimal support for ZC extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for march args being passed.
  RISC-V: Add Zcmp extension supports.
  RISC-V: Add ZCMP push/pop testcases.

 gcc/common/config/riscv/riscv-common.cc       |  39 ++
 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/predicates.md                |  16 +
 gcc/config/riscv/riscv-c.cc                   |   2 +-
 gcc/config/riscv/riscv-opts.h                 |  16 +
 gcc/config/riscv/riscv-passes.def             |   1 +
 gcc/config/riscv/riscv-protos.h               |   4 +
 gcc/config/riscv/riscv-shorten-memrefs.cc     |   3 +-
 gcc/config/riscv/riscv-zcmp-popret.cc         | 260 ++++++++++
 gcc/config/riscv/riscv.cc                     | 453 +++++++++++++++++-
 gcc/config/riscv/riscv.h                      |   6 +-
 gcc/config/riscv/riscv.md                     |   3 +
 gcc/config/riscv/riscv.opt                    |   3 +
 gcc/config/riscv/t-riscv                      |   4 +
 gcc/config/riscv/zc.md                        |  47 ++
 gcc/testsuite/gcc.target/riscv/arch-20.c      |   5 +
 gcc/testsuite/gcc.target/riscv/arch-21.c      |   5 +
 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c  |   9 +
 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c  |   9 +
 .../gcc.target/riscv/zc-zcb-m-arch.c          |   9 +
 .../gcc.target/riscv/zc-zcb-zba-arch.c        |   9 +
 .../gcc.target/riscv/zc-zcb-zbb-arch.c        |   9 +
 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c  |   9 +
 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c |   9 +
 .../gcc.target/riscv/zc-zcmp-push-pop-1.c     |  15 +
 .../gcc.target/riscv/zc-zcmp-push-pop-2.c     |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-3.c     |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-4.c     |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-5.c     |  17 +
 .../gcc.target/riscv/zc-zcmp-push-pop-6.c     |  13 +
 .../gcc.target/riscv/zc-zcmp-push-pop-7.c     |  16 +
 .../gcc.target/riscv/zc-zcmpe-arch.c          |   9 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-1.c    |  15 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-2.c    |  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-3.c    |  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-4.c    |  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-5.c    |  17 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-6.c    |  13 +
 .../gcc.target/riscv/zc-zcmpe-push-pop-7.c    |  16 +
 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c |   9 +
 40 files changed, 1153 insertions(+), 21 deletions(-)
 create mode 100644 gcc/config/riscv/riscv-zcmp-popret.cc
 create mode 100644 gcc/config/riscv/zc.md
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zca-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-m-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zba-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcb-zbb-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcf-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmp-push-pop-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-arch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmpe-push-pop-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zc-zcmt-arch.c

-- 
2.25.1


             reply	other threads:[~2023-04-06  6:22 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-06  6:21 Jiawei [this message]
2023-04-06  6:21 ` [PATCH 1/5] RISC-V: Minimal support for ZC extensions Jiawei
2023-05-04  8:33   ` Kito Cheng
2023-04-06  6:21 ` [PATCH 2/5] RISC-V: Enable compressible features when use ZC* extensions Jiawei
2023-04-06  6:21 ` [PATCH 3/5] RISC-V: Add ZC* test for march args being passed Jiawei
2023-05-04  8:37   ` Kito Cheng
2023-04-06  6:21 ` [PATCH 4/5] RISC-V: Add Zcmp extension supports Jiawei
2023-05-04  9:03   ` Kito Cheng
     [not found]   ` <07720619-dd69-4816-987e-ff0e14d9a348.>
2023-05-12  8:53     ` Sinan
2023-04-06  6:21 ` [PATCH 5/5] RISC-V: Add ZCMP push/pop testcases Jiawei

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