* [PATCH 2/2] AArch64: New RTL for ABDL @ 2023-06-26 15:34 Oluwatamilore Adebayo 2023-06-26 20:54 ` Richard Sandiford 0 siblings, 1 reply; 7+ messages in thread From: Oluwatamilore Adebayo @ 2023-06-26 15:34 UTC (permalink / raw) To: gcc-patches; +Cc: richard.sandiford, richard.guenther, oluade01 From: oluade01 <oluwatamilore.adebayo@arm.com> This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_widen_<su>abdl_lo_<mode>, vec_widen_<su>abdl_hi_<mode>): Expansions for abd vec widen optabs. (aarch64_<su>abdl<mode>_insn): VQW based abdl RTL. * config/aarch64/iterators.md (USMAX_EXT): Code attributes that give the appropriate extend RTL for the max RTL. gcc/testsuite/ChangeLog: * gcc.target/aarch64/abd_2.c: Added ABDL testcases. * gcc.target/aarch64/abd_3.c: Added ABDL testcases. * gcc.target/aarch64/abd_4.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_2.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_3.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_4.c: Added ABDL testcases. * gcc.target/aarch64/abd_run_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_2.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_none_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_none_2.c: Added ABDL testcases. --- gcc/config/aarch64/aarch64-simd.md | 70 ++++++++++++++++ gcc/config/aarch64/iterators.md | 3 + gcc/testsuite/gcc.target/aarch64/abd_2.c | 62 ++++++++++++-- gcc/testsuite/gcc.target/aarch64/abd_3.c | 63 ++++++++++++-- gcc/testsuite/gcc.target/aarch64/abd_4.c | 47 +++++++++-- gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 73 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 73 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 84 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 29 +++++++ gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 67 +++++++++++++-- gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 53 ++++++++++-- .../gcc.target/aarch64/sve/abd_none_1.c | 73 ++++++++++++++++ .../gcc.target/aarch64/sve/abd_none_2.c | 80 ++++++++++++++++++ 13 files changed, 749 insertions(+), 28 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bf90202ba2ad3f62f2020486d21256f083effb07..36fefd0a96801479fbf6469a3fbcef4a0b8cad6f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -975,6 +975,76 @@ (define_expand "aarch64_<su>abdl2<mode>" } ) +(define_insn "aarch64_<su>abdl<mode>_hi_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (USMAX:<VWIDE> + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3)))) + (<max_opp>:<VWIDE> + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> (match_dup 1) (match_dup 3))) + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> (match_dup 2) (match_dup 3))))))] + "TARGET_SIMD" + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "type" "neon_abd_long")] +) + +(define_insn "aarch64_<su>abdl<mode>_lo_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (USMAX:<VWIDE> + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3)))) + (<max_opp>:<VWIDE> + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> + (match_dup 1) + (match_dup 3))) + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> + (match_dup 2) + (match_dup 3))))))] + "TARGET_SIMD" + "<su>abdl\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" + [(set_attr "type" "neon_abd_long")] +) + +(define_expand "vec_widen_<su>abd_hi_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>abdl<mode>_hi_internal (operands[0], operands[1], + operands[2], p)); + DONE; + } +) + +(define_expand "vec_widen_<su>abd_lo_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); + emit_insn (gen_aarch64_<su>abdl<mode>_lo_internal (operands[0], operands[1], + operands[2], p)); + DONE; + } +) + (define_insn "aarch64_<su>abal<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (plus:<VWIDE> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d9c7354730ac5870c0042f1e30fb1140a117d110..1385842d0a51b3f4a0871af4d0bbbeeeee5299d4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1984,6 +1984,9 @@ (define_code_attr max_opp [(smax "smin") (umax "umin")]) ;; Same as above, but louder. (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")]) +;; Map smax and umax to sign_extend and zero_extend +(define_code_attr USMAX_EXT [(smax "sign_extend") (umax "zero_extend")]) + ;; The number of subvectors in an SVE_STRUCT. (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") (VNx8SI "2") (VNx4DI "2") diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c index c0d41fb7ef99baf95b0f6a2e68a88f6748482af3..b86a3923fa8c6c20da52098bfb8ab8e230c894e5 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_2.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c @@ -13,23 +13,75 @@ TEST1(signed, char) TEST2(signed, char, short) TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) -TEST3(signed, char, int, short) TEST3(signed, char, short, int) +TEST3(signed, char, int, short) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, int, char) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) TEST2(unsigned, char, short) TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) +TEST3(unsigned, short, char, short) + +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 35 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ /* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c index 4873c64f34885b3993010beafa01087569336dec..471602a51c4538965ce4a292f75a4ecc7e118b1b 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_3.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c @@ -13,24 +13,75 @@ TEST1(signed, char) TEST2(signed, char, short) TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) -TEST3(signed, char, int, short) TEST3(signed, char, short, int) +TEST3(signed, char, int, short) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, int, char) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) TEST2(unsigned, char, short) TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) +TEST3(unsigned, short, char, short) + +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 35 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c index 98aa730d6aad700e3a9a712e14adc08c9fb546c2..364762283e99c1375e44ab41620d571f54050ce6 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_4.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c @@ -11,20 +11,57 @@ TEST1(signed, int) TEST2(signed, char, short) TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST2(unsigned, char, short) TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 7 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0:w + } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c index 658e7426965ead945d0cad68ef721f176fb41665..d7ef2c1417b5461f8c4315d8d4911ca9f57c592c 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c @@ -7,8 +7,81 @@ #define ABD_ABS #include "abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c index 14cfdcbde6998b527989326ff8848d071a4774e8..f23dd7d06e7facff1116a9c78303993a178b1c0b 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c @@ -7,8 +7,81 @@ #define ABD_ABS #include "abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c index d612216b98bf5484783489cc48b4417ad1914b1d..f5cfc5dd73d0e4008318b7f2a9a143c98b12c88f 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c @@ -9,14 +9,98 @@ TEST1(signed, short) TEST1(signed, char) +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) TEST3(signed, char, int, short) +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) +TEST3(signed, char, long, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, long, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) +TEST2(unsigned, short, char) TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, short, char) +TEST3(unsigned, char, int, char) +TEST3(unsigned, char, long, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, char, short) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c index 7bb0a801415ffeab235bd636032112228255e836..1bfd6aca157db47b0874af7308a5fa8d61f71da2 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c @@ -11,10 +11,17 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) +TEST2(signed, char, short) +TEST2(signed, short, int) +TEST2(signed, int, long) + TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST2(unsigned, char, short) +TEST2(unsigned, short, int) + #define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } #define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 } #define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 } @@ -27,6 +34,8 @@ typedef signed short s16; typedef unsigned short u16; typedef signed int s32; typedef unsigned int u32; +typedef signed long s64; +typedef unsigned long u64; s8 sc_out[] = EMPTY; u8 uc_out[] = EMPTY; @@ -34,6 +43,8 @@ s16 ss_out[] = EMPTY; u16 us_out[] = EMPTY; s32 si_out[] = EMPTY; u32 ui_out[] = EMPTY; +s64 sl_out[] = EMPTY; +u64 ul_out[] = EMPTY; s8 sc_A[] = sA; s8 sc_B[] = B; @@ -56,6 +67,8 @@ s16 ss_gold[] = GOLD; u16 us_gold[] = GOLD; s32 si_gold[] = GOLD; u32 ui_gold[] = GOLD; +s64 sl_gold[] = GOLD; +u64 ul_gold[] = GOLD; extern void abort (void); @@ -88,6 +101,22 @@ int main () fn_unsigned_int (ui_A, ui_B, ui_out); COMPARE (ui_out, ui_gold); + + fn_signed_char_char_short (sc_B, sc_A, ss_out); + COMPARE(ss_gold, ss_out); + + fn_signed_short_short_int (ss_A, ss_B, si_out); + COMPARE(si_gold, si_out); + + fn_signed_int_int_long (si_B, si_A, sl_out); + COMPARE(sl_gold, sl_out); + + fn_unsigned_char_char_short (uc_B, uc_A, us_out); + COMPARE(us_gold, us_out); + + fn_unsigned_short_short_int (us_A, us_B, ui_out); + COMPARE(ui_gold, ui_out); + return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c index e49006f90b22040f890c279ec19c490a655abd63..364741ea1bfb981f61676128efad1e43586e8eb8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c @@ -10,26 +10,79 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, int) TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) -TEST3(signed, char, int, short) TEST3(signed, char, short, int) +TEST3(signed, char, int, short) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, int, char) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) TEST2(unsigned, char, short) TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) +TEST3(unsigned, short, char, short) + +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 16 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c index ea64fa837b1025933ab6c339b86f0db06ffbe0e4..02e0ef09b72a3802fd32c93bf43035787ed5553b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c @@ -7,23 +7,66 @@ #include "../abd.h" TEST1(signed, int) +TEST1(signed, long) -TEST2(signed, char, int) TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) + +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) -TEST2(unsigned, char, int) TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 4 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 8 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 0 } } */ /* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 0 } } */ /* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ + /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c index a4c2053c50e235e6ea6ad8bfb124889556be1657..1fb58b38474796bb6ed66fb098372ac81446d572 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c @@ -6,8 +6,81 @@ #define ABD_ABS #include "../abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c index 4862db93a81e890637ee8e02dcc9de9e0e613e91..a9465b56bab9aad5a6bea65055e7d928c7aabe39 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c @@ -9,13 +9,93 @@ TEST1(signed, short) TEST1(signed, char) +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) + TEST3(signed, char, int, short) +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) +TEST3(signed, char, long, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, long, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) +TEST2(unsigned, short, char) TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, short, char) +TEST3(unsigned, char, int, char) +TEST3(unsigned, char, long, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, char, short) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ -- 2.25.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] AArch64: New RTL for ABDL 2023-06-26 15:34 [PATCH 2/2] AArch64: New RTL for ABDL Oluwatamilore Adebayo @ 2023-06-26 20:54 ` Richard Sandiford 2023-06-28 15:14 ` Oluwatamilore Adebayo 0 siblings, 1 reply; 7+ messages in thread From: Richard Sandiford @ 2023-06-26 20:54 UTC (permalink / raw) To: Oluwatamilore Adebayo; +Cc: gcc-patches, richard.guenther Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com> writes: > From: oluade01 <oluwatamilore.adebayo@arm.com> > > This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md > (vec_widen_<su>abdl_lo_<mode>, vec_widen_<su>abdl_hi_<mode>): > Expansions for abd vec widen optabs. > (aarch64_<su>abdl<mode>_insn): VQW based abdl RTL. > * config/aarch64/iterators.md (USMAX_EXT): Code attributes > that give the appropriate extend RTL for the max RTL. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/abd_2.c: Added ABDL testcases. > * gcc.target/aarch64/abd_3.c: Added ABDL testcases. > * gcc.target/aarch64/abd_4.c: Added ABDL testcases. > * gcc.target/aarch64/abd_none_2.c: Added ABDL testcases. > * gcc.target/aarch64/abd_none_3.c: Added ABDL testcases. > * gcc.target/aarch64/abd_none_4.c: Added ABDL testcases. > * gcc.target/aarch64/abd_run_1.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_1.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_2.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_none_1.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_none_2.c: Added ABDL testcases. > --- > gcc/config/aarch64/aarch64-simd.md | 70 ++++++++++++++++ > gcc/config/aarch64/iterators.md | 3 + > gcc/testsuite/gcc.target/aarch64/abd_2.c | 62 ++++++++++++-- > gcc/testsuite/gcc.target/aarch64/abd_3.c | 63 ++++++++++++-- > gcc/testsuite/gcc.target/aarch64/abd_4.c | 47 +++++++++-- > gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 73 ++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 73 ++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 84 +++++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 29 +++++++ > gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 67 +++++++++++++-- > gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 53 ++++++++++-- > .../gcc.target/aarch64/sve/abd_none_1.c | 73 ++++++++++++++++ > .../gcc.target/aarch64/sve/abd_none_2.c | 80 ++++++++++++++++++ > 13 files changed, 749 insertions(+), 28 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index bf90202ba2ad3f62f2020486d21256f083effb07..36fefd0a96801479fbf6469a3fbcef4a0b8cad6f 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -975,6 +975,76 @@ (define_expand "aarch64_<su>abdl2<mode>" > } > ) > > +(define_insn "aarch64_<su>abdl<mode>_hi_internal" > + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > + (minus:<VWIDE> > + (USMAX:<VWIDE> > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> > + (match_operand:VQW 1 "register_operand" "w") > + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> > + (match_operand:VQW 2 "register_operand" "w") > + (match_dup 3)))) > + (<max_opp>:<VWIDE> > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> (match_dup 1) (match_dup 3))) > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> (match_dup 2) (match_dup 3))))))] > + "TARGET_SIMD" > + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" > + [(set_attr "type" "neon_abd_long")] > +) We don't need the (minus (max…) (min…)) thing when widening is involved. It should be enough to do something like: (abs:<VWIDE> (minus:<VWIDE> (ANY_EXTEND:<VWIDE> (vec_select:…)) (ANY_EXTEND:<VWIDE> (vec_select:…)))) > + > +(define_insn "aarch64_<su>abdl<mode>_lo_internal" > + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > + (minus:<VWIDE> > + (USMAX:<VWIDE> > + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> > + (match_operand:VQW 1 "register_operand" "w") > + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) > + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> > + (match_operand:VQW 2 "register_operand" "w") > + (match_dup 3)))) > + (<max_opp>:<VWIDE> > + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> > + (match_dup 1) > + (match_dup 3))) > + (<USMAX_EXT>:<VWIDE> (vec_select:<VHALF> > + (match_dup 2) > + (match_dup 3))))))] > + "TARGET_SIMD" > + "<su>abdl\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" > + [(set_attr "type" "neon_abd_long")] > +) > + > +(define_expand "vec_widen_<su>abd_hi_<mode>" > + [(match_operand:<VWIDE> 0 "register_operand") > + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) > + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] > + "TARGET_SIMD" > + { > + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); > + emit_insn (gen_aarch64_<su>abdl<mode>_hi_internal (operands[0], operands[1], > + operands[2], p)); > + DONE; > + } > +) > + > +(define_expand "vec_widen_<su>abd_lo_<mode>" > + [(match_operand:<VWIDE> 0 "register_operand") > + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) > + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] > + "TARGET_SIMD" > + { > + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); > + emit_insn (gen_aarch64_<su>abdl<mode>_lo_internal (operands[0], operands[1], > + operands[2], p)); > + DONE; > + } > +) > + > (define_insn "aarch64_<su>abal<mode>" > [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > (plus:<VWIDE> > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md > index d9c7354730ac5870c0042f1e30fb1140a117d110..1385842d0a51b3f4a0871af4d0bbbeeeee5299d4 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -1984,6 +1984,9 @@ (define_code_attr max_opp [(smax "smin") (umax "umin")]) > ;; Same as above, but louder. > (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")]) > > +;; Map smax and umax to sign_extend and zero_extend > +(define_code_attr USMAX_EXT [(smax "sign_extend") (umax "zero_extend")]) > + > ;; The number of subvectors in an SVE_STRUCT. > (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") > (VNx8SI "2") (VNx4DI "2") > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c > index c0d41fb7ef99baf95b0f6a2e68a88f6748482af3..b86a3923fa8c6c20da52098bfb8ab8e230c894e5 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c > @@ -13,23 +13,75 @@ TEST1(signed, char) > > TEST2(signed, char, short) > TEST2(signed, char, int) > +TEST2(signed, char, long) > TEST2(signed, short, int) > +TEST2(signed, short, long) > +TEST2(signed, int, long) > + > +TEST2(signed, int, short) > +TEST2(signed, int, char) > +TEST2(signed, short, char) > > -TEST3(signed, char, int, short) > TEST3(signed, char, short, int) > +TEST3(signed, char, int, short) > +TEST3(signed, char, short, long) > +TEST3(signed, char, int, long) > +TEST3(signed, char, short, char) > +TEST3(signed, char, int, char) > + > +TEST3(signed, short, char, int) > +TEST3(signed, short, int, char) > +TEST3(signed, short, char, long) > +TEST3(signed, short, int, long) > +TEST3(signed, short, char, short) > +TEST3(signed, short, int, short) > + > +TEST3(signed, int, char, short) > +TEST3(signed, int, short, char) > +TEST3(signed, int, char, long) > +TEST3(signed, int, short, long) > +TEST3(signed, int, char, int) > +TEST3(signed, int, short, int) > > TEST1(unsigned, short) > TEST1(unsigned, char) > > TEST2(unsigned, char, short) > TEST2(unsigned, char, int) > +TEST2(unsigned, char, long) > +TEST2(unsigned, short, int) > +TEST2(unsigned, short, long) > + > +TEST2(unsigned, short, char) > > TEST3(unsigned, char, short, int) > +TEST3(unsigned, char, short, long) > +TEST3(unsigned, char, short, char) > + > +TEST3(unsigned, short, char, int) > +TEST3(unsigned, short, char, long) > +TEST3(unsigned, short, char, short) > + > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 35 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ > > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > + > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > /* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ > + > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > > /* { dg-final { scan-assembler-not {\tabs\t} } } */ Sorry to be awkward, but could you put the widening cases in a separate file? It's not very easy as things stand to work out which tests are matched against widening ops and which aren't. Thanks, Richard > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c > index 4873c64f34885b3993010beafa01087569336dec..471602a51c4538965ce4a292f75a4ecc7e118b1b 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_3.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c > @@ -13,24 +13,75 @@ TEST1(signed, char) > > TEST2(signed, char, short) > TEST2(signed, char, int) > +TEST2(signed, char, long) > TEST2(signed, short, int) > +TEST2(signed, short, long) > +TEST2(signed, int, long) > + > +TEST2(signed, int, short) > +TEST2(signed, int, char) > +TEST2(signed, short, char) > > -TEST3(signed, char, int, short) > TEST3(signed, char, short, int) > +TEST3(signed, char, int, short) > +TEST3(signed, char, short, long) > +TEST3(signed, char, int, long) > +TEST3(signed, char, short, char) > +TEST3(signed, char, int, char) > + > +TEST3(signed, short, char, int) > +TEST3(signed, short, int, char) > +TEST3(signed, short, char, long) > +TEST3(signed, short, int, long) > +TEST3(signed, short, char, short) > +TEST3(signed, short, int, short) > + > +TEST3(signed, int, char, short) > +TEST3(signed, int, short, char) > +TEST3(signed, int, char, long) > +TEST3(signed, int, short, long) > +TEST3(signed, int, char, int) > +TEST3(signed, int, short, int) > > TEST1(unsigned, short) > TEST1(unsigned, char) > > TEST2(unsigned, char, short) > TEST2(unsigned, char, int) > +TEST2(unsigned, char, long) > TEST2(unsigned, short, int) > +TEST2(unsigned, short, long) > + > +TEST2(unsigned, short, char) > > TEST3(unsigned, char, short, int) > +TEST3(unsigned, char, short, long) > +TEST3(unsigned, char, short, char) > + > +TEST3(unsigned, short, char, int) > +TEST3(unsigned, short, char, long) > +TEST3(unsigned, short, char, short) > + > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 35 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ > + > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > + > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ > > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > > /* { dg-final { scan-assembler-not {\tabs\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c > index 98aa730d6aad700e3a9a712e14adc08c9fb546c2..364762283e99c1375e44ab41620d571f54050ce6 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_4.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c > @@ -11,20 +11,57 @@ TEST1(signed, int) > > TEST2(signed, char, short) > TEST2(signed, char, int) > +TEST2(signed, char, long) > TEST2(signed, short, int) > +TEST2(signed, short, long) > +TEST2(signed, int, long) > > TEST3(signed, char, short, int) > +TEST3(signed, char, short, long) > +TEST3(signed, char, int, long) > + > +TEST3(signed, short, char, int) > +TEST3(signed, short, char, long) > +TEST3(signed, short, int, long) > + > +TEST3(signed, int, char, long) > +TEST3(signed, int, short, long) > +TEST3(signed, int, char, int) > +TEST3(signed, int, short, int) > > TEST2(unsigned, char, short) > TEST2(unsigned, char, int) > +TEST2(unsigned, char, long) > TEST2(unsigned, short, int) > +TEST2(unsigned, short, long) > > TEST3(unsigned, char, short, int) > +TEST3(unsigned, char, short, long) > + > +TEST3(unsigned, short, char, int) > +TEST3(unsigned, short, char, long) > + > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 7 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ > + > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > + > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0:w > + } } */ > > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ > > /* { dg-final { scan-assembler-not {\tabs\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c > index 658e7426965ead945d0cad68ef721f176fb41665..d7ef2c1417b5461f8c4315d8d4911ca9f57c592c 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c > @@ -7,8 +7,81 @@ > #define ABD_ABS > #include "abd.h" > > +TEST1(signed, long) > + > +TEST2(signed, long, char) > +TEST2(signed, long, short) > +TEST2(signed, long, int) > + > +TEST3(signed, char, long, short) > +TEST3(signed, char, long, int) > +TEST3(signed, char, long, char) > + > +TEST3(signed, short, long, char) > +TEST3(signed, short, long, int) > +TEST3(signed, short, long, short) > + > +TEST3(signed, int, long, char) > +TEST3(signed, int, long, short) > +TEST3(signed, int, long, int) > + > +TEST3(signed, long, char, short) > +TEST3(signed, long, short, char) > +TEST3(signed, long, char, int) > +TEST3(signed, long, int, char) > +TEST3(signed, long, short, int) > +TEST3(signed, long, int, short) > +TEST3(signed, long, char, long) > +TEST3(signed, long, short, long) > +TEST3(signed, long, int, long) > + > TEST1(unsigned, int) > +TEST1(unsigned, long) > + > +TEST2(unsigned, int, long) > + > +TEST2(unsigned, long, char) > +TEST2(unsigned, long, short) > +TEST2(unsigned, long, int) > +TEST2(unsigned, int, short) > +TEST2(unsigned, int, char) > + > TEST3(unsigned, char, int, short) > +TEST3(unsigned, char, long, short) > +TEST3(unsigned, char, int, long) > +TEST3(unsigned, char, long, int) > +TEST3(unsigned, char, int, char) > + > +TEST3(unsigned, short, int, char) > +TEST3(unsigned, short, long, char) > +TEST3(unsigned, short, int, long) > +TEST3(unsigned, short, long, int) > +TEST3(unsigned, short, int, short) > +TEST3(unsigned, short, long, short) > + > +TEST3(unsigned, int, char, short) > +TEST3(unsigned, int, short, char) > +TEST3(unsigned, int, char, long) > +TEST3(unsigned, int, long, char) > +TEST3(unsigned, int, short, long) > +TEST3(unsigned, int, long, short) > +TEST3(unsigned, int, char, int) > +TEST3(unsigned, int, short, int) > +TEST3(unsigned, int, long, int) > + > +TEST3(unsigned, long, char, short) > +TEST3(unsigned, long, short, char) > +TEST3(unsigned, long, char, int) > +TEST3(unsigned, long, int, char) > +TEST3(unsigned, long, short, int) > +TEST3(unsigned, long, int, short) > +TEST3(unsigned, long, char, long) > +TEST3(unsigned, long, short, long) > +TEST3(unsigned, long, int, long) > > /* { dg-final { scan-assembler-not {\tsabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ > /* { dg-final { scan-assembler-not {\tuabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c > index 14cfdcbde6998b527989326ff8848d071a4774e8..f23dd7d06e7facff1116a9c78303993a178b1c0b 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c > @@ -7,8 +7,81 @@ > #define ABD_ABS > #include "abd.h" > > +TEST1(signed, long) > + > +TEST2(signed, long, char) > +TEST2(signed, long, short) > +TEST2(signed, long, int) > + > +TEST3(signed, char, long, short) > +TEST3(signed, char, long, int) > +TEST3(signed, char, long, char) > + > +TEST3(signed, short, long, char) > +TEST3(signed, short, long, int) > +TEST3(signed, short, long, short) > + > +TEST3(signed, int, long, char) > +TEST3(signed, int, long, short) > +TEST3(signed, int, long, int) > + > +TEST3(signed, long, char, short) > +TEST3(signed, long, short, char) > +TEST3(signed, long, char, int) > +TEST3(signed, long, int, char) > +TEST3(signed, long, short, int) > +TEST3(signed, long, int, short) > +TEST3(signed, long, char, long) > +TEST3(signed, long, short, long) > +TEST3(signed, long, int, long) > + > TEST1(unsigned, int) > +TEST1(unsigned, long) > + > +TEST2(unsigned, int, long) > + > +TEST2(unsigned, long, char) > +TEST2(unsigned, long, short) > +TEST2(unsigned, long, int) > +TEST2(unsigned, int, short) > +TEST2(unsigned, int, char) > + > TEST3(unsigned, char, int, short) > +TEST3(unsigned, char, long, short) > +TEST3(unsigned, char, int, long) > +TEST3(unsigned, char, long, int) > +TEST3(unsigned, char, int, char) > + > +TEST3(unsigned, short, int, char) > +TEST3(unsigned, short, long, char) > +TEST3(unsigned, short, int, long) > +TEST3(unsigned, short, long, int) > +TEST3(unsigned, short, int, short) > +TEST3(unsigned, short, long, short) > + > +TEST3(unsigned, int, char, short) > +TEST3(unsigned, int, short, char) > +TEST3(unsigned, int, char, long) > +TEST3(unsigned, int, long, char) > +TEST3(unsigned, int, short, long) > +TEST3(unsigned, int, long, short) > +TEST3(unsigned, int, char, int) > +TEST3(unsigned, int, short, int) > +TEST3(unsigned, int, long, int) > + > +TEST3(unsigned, long, char, short) > +TEST3(unsigned, long, short, char) > +TEST3(unsigned, long, char, int) > +TEST3(unsigned, long, int, char) > +TEST3(unsigned, long, short, int) > +TEST3(unsigned, long, int, short) > +TEST3(unsigned, long, char, long) > +TEST3(unsigned, long, short, long) > +TEST3(unsigned, long, int, long) > > /* { dg-final { scan-assembler-not {\tsabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ > /* { dg-final { scan-assembler-not {\tuabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c > index d612216b98bf5484783489cc48b4417ad1914b1d..f5cfc5dd73d0e4008318b7f2a9a143c98b12c88f 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c > @@ -9,14 +9,98 @@ > > TEST1(signed, short) > TEST1(signed, char) > +TEST1(signed, long) > + > +TEST2(signed, long, char) > +TEST2(signed, long, short) > +TEST2(signed, long, int) > +TEST2(signed, int, short) > +TEST2(signed, int, char) > +TEST2(signed, short, char) > > TEST3(signed, char, int, short) > +TEST3(signed, char, long, short) > +TEST3(signed, char, long, int) > +TEST3(signed, char, short, char) > +TEST3(signed, char, int, char) > +TEST3(signed, char, long, char) > + > +TEST3(signed, short, int, char) > +TEST3(signed, short, long, char) > +TEST3(signed, short, long, int) > +TEST3(signed, short, char, short) > +TEST3(signed, short, int, short) > +TEST3(signed, short, long, short) > + > +TEST3(signed, int, char, short) > +TEST3(signed, int, short, char) > +TEST3(signed, int, long, char) > +TEST3(signed, int, long, short) > +TEST3(signed, int, long, int) > + > +TEST3(signed, long, char, short) > +TEST3(signed, long, short, char) > +TEST3(signed, long, char, int) > +TEST3(signed, long, int, char) > +TEST3(signed, long, short, int) > +TEST3(signed, long, int, short) > +TEST3(signed, long, char, long) > +TEST3(signed, long, short, long) > +TEST3(signed, long, int, long) > > TEST1(unsigned, int) > TEST1(unsigned, short) > TEST1(unsigned, char) > +TEST1(unsigned, long) > + > +TEST2(unsigned, int, long) > + > +TEST2(unsigned, long, char) > +TEST2(unsigned, long, short) > +TEST2(unsigned, long, int) > +TEST2(unsigned, int, short) > +TEST2(unsigned, int, char) > +TEST2(unsigned, short, char) > > TEST3(unsigned, char, int, short) > +TEST3(unsigned, char, long, short) > +TEST3(unsigned, char, int, long) > +TEST3(unsigned, char, long, int) > +TEST3(unsigned, char, short, char) > +TEST3(unsigned, char, int, char) > +TEST3(unsigned, char, long, char) > + > +TEST3(unsigned, short, int, char) > +TEST3(unsigned, short, long, char) > +TEST3(unsigned, short, int, long) > +TEST3(unsigned, short, long, int) > +TEST3(unsigned, short, char, short) > +TEST3(unsigned, short, int, short) > +TEST3(unsigned, short, long, short) > + > +TEST3(unsigned, int, char, short) > +TEST3(unsigned, int, short, char) > +TEST3(unsigned, int, char, long) > +TEST3(unsigned, int, long, char) > +TEST3(unsigned, int, short, long) > +TEST3(unsigned, int, long, short) > +TEST3(unsigned, int, char, int) > +TEST3(unsigned, int, short, int) > +TEST3(unsigned, int, long, int) > + > +TEST3(unsigned, long, char, short) > +TEST3(unsigned, long, short, char) > +TEST3(unsigned, long, char, int) > +TEST3(unsigned, long, int, char) > +TEST3(unsigned, long, short, int) > +TEST3(unsigned, long, int, short) > +TEST3(unsigned, long, char, long) > +TEST3(unsigned, long, short, long) > +TEST3(unsigned, long, int, long) > > /* { dg-final { scan-assembler-not {\tsabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ > /* { dg-final { scan-assembler-not {\tuabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c > index 7bb0a801415ffeab235bd636032112228255e836..1bfd6aca157db47b0874af7308a5fa8d61f71da2 100644 > --- a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c > @@ -11,10 +11,17 @@ TEST1(signed, int) > TEST1(signed, short) > TEST1(signed, char) > > +TEST2(signed, char, short) > +TEST2(signed, short, int) > +TEST2(signed, int, long) > + > TEST1(unsigned, int) > TEST1(unsigned, short) > TEST1(unsigned, char) > > +TEST2(unsigned, char, short) > +TEST2(unsigned, short, int) > + > #define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } > #define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 } > #define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 } > @@ -27,6 +34,8 @@ typedef signed short s16; > typedef unsigned short u16; > typedef signed int s32; > typedef unsigned int u32; > +typedef signed long s64; > +typedef unsigned long u64; > > s8 sc_out[] = EMPTY; > u8 uc_out[] = EMPTY; > @@ -34,6 +43,8 @@ s16 ss_out[] = EMPTY; > u16 us_out[] = EMPTY; > s32 si_out[] = EMPTY; > u32 ui_out[] = EMPTY; > +s64 sl_out[] = EMPTY; > +u64 ul_out[] = EMPTY; > > s8 sc_A[] = sA; > s8 sc_B[] = B; > @@ -56,6 +67,8 @@ s16 ss_gold[] = GOLD; > u16 us_gold[] = GOLD; > s32 si_gold[] = GOLD; > u32 ui_gold[] = GOLD; > +s64 sl_gold[] = GOLD; > +u64 ul_gold[] = GOLD; > > extern void abort (void); > > @@ -88,6 +101,22 @@ int main () > fn_unsigned_int (ui_A, ui_B, ui_out); > COMPARE (ui_out, ui_gold); > > + > + fn_signed_char_char_short (sc_B, sc_A, ss_out); > + COMPARE(ss_gold, ss_out); > + > + fn_signed_short_short_int (ss_A, ss_B, si_out); > + COMPARE(si_gold, si_out); > + > + fn_signed_int_int_long (si_B, si_A, sl_out); > + COMPARE(sl_gold, sl_out); > + > + fn_unsigned_char_char_short (uc_B, uc_A, us_out); > + COMPARE(us_gold, us_out); > + > + fn_unsigned_short_short_int (us_A, us_B, ui_out); > + COMPARE(ui_gold, ui_out); > + > return 0; > } > > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c > index e49006f90b22040f890c279ec19c490a655abd63..364741ea1bfb981f61676128efad1e43586e8eb8 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c > @@ -10,26 +10,79 @@ TEST1(signed, int) > TEST1(signed, short) > TEST1(signed, char) > > -TEST2(signed, char, int) > TEST2(signed, char, short) > +TEST2(signed, char, int) > +TEST2(signed, char, long) > TEST2(signed, short, int) > +TEST2(signed, short, long) > +TEST2(signed, int, long) > + > +TEST2(signed, int, short) > +TEST2(signed, int, char) > +TEST2(signed, short, char) > > -TEST3(signed, char, int, short) > TEST3(signed, char, short, int) > +TEST3(signed, char, int, short) > +TEST3(signed, char, short, long) > +TEST3(signed, char, int, long) > +TEST3(signed, char, short, char) > +TEST3(signed, char, int, char) > + > +TEST3(signed, short, char, int) > +TEST3(signed, short, int, char) > +TEST3(signed, short, char, long) > +TEST3(signed, short, int, long) > +TEST3(signed, short, char, short) > +TEST3(signed, short, int, short) > + > +TEST3(signed, int, char, short) > +TEST3(signed, int, short, char) > +TEST3(signed, int, char, long) > +TEST3(signed, int, short, long) > +TEST3(signed, int, char, int) > +TEST3(signed, int, short, int) > > TEST1(unsigned, short) > TEST1(unsigned, char) > > TEST2(unsigned, char, short) > TEST2(unsigned, char, int) > +TEST2(unsigned, char, long) > TEST2(unsigned, short, int) > +TEST2(unsigned, short, long) > + > +TEST2(unsigned, short, char) > > TEST3(unsigned, char, short, int) > +TEST3(unsigned, char, short, long) > +TEST3(unsigned, char, short, char) > + > +TEST3(unsigned, short, char, int) > +TEST3(unsigned, short, char, long) > +TEST3(unsigned, short, char, short) > + > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 16 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ > + > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 0 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ > + > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ > > -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ > > /* { dg-final { scan-assembler-not {\tabs\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c > index ea64fa837b1025933ab6c339b86f0db06ffbe0e4..02e0ef09b72a3802fd32c93bf43035787ed5553b 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c > @@ -7,23 +7,66 @@ > #include "../abd.h" > > TEST1(signed, int) > +TEST1(signed, long) > > -TEST2(signed, char, int) > TEST2(signed, char, short) > +TEST2(signed, char, int) > +TEST2(signed, char, long) > TEST2(signed, short, int) > +TEST2(signed, short, long) > +TEST2(signed, int, long) > > TEST3(signed, char, short, int) > +TEST3(signed, char, short, long) > +TEST3(signed, char, int, long) > + > +TEST3(signed, short, char, int) > +TEST3(signed, short, char, long) > +TEST3(signed, short, int, long) > + > +TEST3(signed, int, char, long) > +TEST3(signed, int, short, long) > +TEST3(signed, int, char, int) > +TEST3(signed, int, short, int) > + > +TEST3(signed, long, char, long) > +TEST3(signed, long, short, long) > +TEST3(signed, long, int, long) > > -TEST2(unsigned, char, int) > TEST2(unsigned, char, short) > +TEST2(unsigned, char, int) > +TEST2(unsigned, char, long) > TEST2(unsigned, short, int) > +TEST2(unsigned, short, long) > > TEST3(unsigned, char, short, int) > +TEST3(unsigned, char, short, long) > + > +TEST3(unsigned, short, char, int) > +TEST3(unsigned, short, char, long) > > -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 1 } } */ > -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 4 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 8 } } */ > +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 0 } } */ > /* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ > -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ > + > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ > +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */ > +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ > + > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 0 } } */ > /* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ > > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ > +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */ > +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ > + > /* { dg-final { scan-assembler-not {\tabs\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c > index a4c2053c50e235e6ea6ad8bfb124889556be1657..1fb58b38474796bb6ed66fb098372ac81446d572 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c > @@ -6,8 +6,81 @@ > #define ABD_ABS > #include "../abd.h" > > +TEST1(signed, long) > + > +TEST2(signed, long, char) > +TEST2(signed, long, short) > +TEST2(signed, long, int) > + > +TEST3(signed, char, long, short) > +TEST3(signed, char, long, int) > +TEST3(signed, char, long, char) > + > +TEST3(signed, short, long, char) > +TEST3(signed, short, long, int) > +TEST3(signed, short, long, short) > + > +TEST3(signed, int, long, char) > +TEST3(signed, int, long, short) > +TEST3(signed, int, long, int) > + > +TEST3(signed, long, char, short) > +TEST3(signed, long, short, char) > +TEST3(signed, long, char, int) > +TEST3(signed, long, int, char) > +TEST3(signed, long, short, int) > +TEST3(signed, long, int, short) > +TEST3(signed, long, char, long) > +TEST3(signed, long, short, long) > +TEST3(signed, long, int, long) > + > TEST1(unsigned, int) > +TEST1(unsigned, long) > + > +TEST2(unsigned, int, long) > + > +TEST2(unsigned, long, char) > +TEST2(unsigned, long, short) > +TEST2(unsigned, long, int) > +TEST2(unsigned, int, short) > +TEST2(unsigned, int, char) > + > TEST3(unsigned, char, int, short) > +TEST3(unsigned, char, long, short) > +TEST3(unsigned, char, int, long) > +TEST3(unsigned, char, long, int) > +TEST3(unsigned, char, int, char) > + > +TEST3(unsigned, short, int, char) > +TEST3(unsigned, short, long, char) > +TEST3(unsigned, short, int, long) > +TEST3(unsigned, short, long, int) > +TEST3(unsigned, short, int, short) > +TEST3(unsigned, short, long, short) > + > +TEST3(unsigned, int, char, short) > +TEST3(unsigned, int, short, char) > +TEST3(unsigned, int, char, long) > +TEST3(unsigned, int, long, char) > +TEST3(unsigned, int, short, long) > +TEST3(unsigned, int, long, short) > +TEST3(unsigned, int, char, int) > +TEST3(unsigned, int, short, int) > +TEST3(unsigned, int, long, int) > + > +TEST3(unsigned, long, char, short) > +TEST3(unsigned, long, short, char) > +TEST3(unsigned, long, char, int) > +TEST3(unsigned, long, int, char) > +TEST3(unsigned, long, short, int) > +TEST3(unsigned, long, int, short) > +TEST3(unsigned, long, char, long) > +TEST3(unsigned, long, short, long) > +TEST3(unsigned, long, int, long) > > /* { dg-final { scan-assembler-not {\tsabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ > /* { dg-final { scan-assembler-not {\tuabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c > index 4862db93a81e890637ee8e02dcc9de9e0e613e91..a9465b56bab9aad5a6bea65055e7d928c7aabe39 100644 > --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c > +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c > @@ -9,13 +9,93 @@ > TEST1(signed, short) > TEST1(signed, char) > > +TEST2(signed, long, char) > +TEST2(signed, long, short) > +TEST2(signed, long, int) > +TEST2(signed, int, short) > +TEST2(signed, int, char) > +TEST2(signed, short, char) > + > TEST3(signed, char, int, short) > +TEST3(signed, char, long, short) > +TEST3(signed, char, long, int) > +TEST3(signed, char, short, char) > +TEST3(signed, char, int, char) > +TEST3(signed, char, long, char) > + > +TEST3(signed, short, int, char) > +TEST3(signed, short, long, char) > +TEST3(signed, short, long, int) > +TEST3(signed, short, char, short) > +TEST3(signed, short, int, short) > +TEST3(signed, short, long, short) > + > +TEST3(signed, int, char, short) > +TEST3(signed, int, short, char) > +TEST3(signed, int, long, char) > +TEST3(signed, int, long, short) > +TEST3(signed, int, long, int) > + > +TEST3(signed, long, char, short) > +TEST3(signed, long, short, char) > +TEST3(signed, long, char, int) > +TEST3(signed, long, int, char) > +TEST3(signed, long, short, int) > +TEST3(signed, long, int, short) > > TEST1(unsigned, int) > TEST1(unsigned, short) > TEST1(unsigned, char) > +TEST1(unsigned, long) > + > +TEST2(unsigned, int, long) > + > +TEST2(unsigned, long, char) > +TEST2(unsigned, long, short) > +TEST2(unsigned, long, int) > +TEST2(unsigned, int, short) > +TEST2(unsigned, int, char) > +TEST2(unsigned, short, char) > > TEST3(unsigned, char, int, short) > +TEST3(unsigned, char, long, short) > +TEST3(unsigned, char, int, long) > +TEST3(unsigned, char, long, int) > +TEST3(unsigned, char, short, char) > +TEST3(unsigned, char, int, char) > +TEST3(unsigned, char, long, char) > + > +TEST3(unsigned, short, int, char) > +TEST3(unsigned, short, long, char) > +TEST3(unsigned, short, int, long) > +TEST3(unsigned, short, long, int) > +TEST3(unsigned, short, char, short) > +TEST3(unsigned, short, int, short) > +TEST3(unsigned, short, long, short) > + > +TEST3(unsigned, int, char, short) > +TEST3(unsigned, int, short, char) > +TEST3(unsigned, int, char, long) > +TEST3(unsigned, int, long, char) > +TEST3(unsigned, int, short, long) > +TEST3(unsigned, int, long, short) > +TEST3(unsigned, int, char, int) > +TEST3(unsigned, int, short, int) > +TEST3(unsigned, int, long, int) > + > +TEST3(unsigned, long, char, short) > +TEST3(unsigned, long, short, char) > +TEST3(unsigned, long, char, int) > +TEST3(unsigned, long, int, char) > +TEST3(unsigned, long, short, int) > +TEST3(unsigned, long, int, short) > +TEST3(unsigned, long, char, long) > +TEST3(unsigned, long, short, long) > +TEST3(unsigned, long, int, long) > > /* { dg-final { scan-assembler-not {\tsabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ > /* { dg-final { scan-assembler-not {\tuabd\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ > +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] AArch64: New RTL for ABDL 2023-06-26 20:54 ` Richard Sandiford @ 2023-06-28 15:14 ` Oluwatamilore Adebayo 2023-06-28 15:15 ` Oluwatamilore Adebayo 0 siblings, 1 reply; 7+ messages in thread From: Oluwatamilore Adebayo @ 2023-06-28 15:14 UTC (permalink / raw) To: richard.sandiford; +Cc: gcc-patches, oluwatamilore.adebayo, richard.guenther > > +(define_insn "aarch64_<su>abdl<mode>_hi_internal" > > + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > > + (minus:<VWIDE> > > + (USMAX:<VWIDE> > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> > > + (match_operand:VQW 1 "register_operand" "w") > > + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> > > + (match_operand:VQW 2 "register_operand" "w") > > + (match_dup 3)))) > > + (<max_opp>:<VWIDE> > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> (match_dup 1) (match_dup 3))) > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> (match_dup 2) (match_dup 3))))))] > > + "TARGET_SIMD" > > + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" > > + [(set_attr "type" "neon_abd_long")] > > +) > > We don't need the (minus (max…) (min…)) thing when widening is > involved. It should be enough to do something like: > > (abs:<VWIDE> > (minus:<VWIDE> > (ANY_EXTEND:<VWIDE> > (vec_select:…)) > (ANY_EXTEND:<VWIDE> > (vec_select:…)))) Change made. > Sorry to be awkward, but could you put the widening cases in a separate > file? It's not very easy as things stand to work out which tests are > matched against widening ops and which aren't. Done. Patch in next email. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] AArch64: New RTL for ABDL 2023-06-28 15:14 ` Oluwatamilore Adebayo @ 2023-06-28 15:15 ` Oluwatamilore Adebayo 2023-06-29 10:25 ` Richard Sandiford 0 siblings, 1 reply; 7+ messages in thread From: Oluwatamilore Adebayo @ 2023-06-28 15:15 UTC (permalink / raw) To: oluwatamilore.adebayo; +Cc: gcc-patches, richard.guenther, richard.sandiford From: oluade01 <oluwatamilore.adebayo@arm.com> This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_widen_<su>abdl_lo_<mode>, vec_widen_<su>abdl_hi_<mode>): Expansions for abd vec widen optabs. (aarch64_<su>abdl<mode>_insn): VQW based abdl RTL. * config/aarch64/iterators.md (USMAX_EXT): Code attributes that give the appropriate extend RTL for the max RTL. gcc/testsuite/ChangeLog: * gcc.target/aarch64/abd_2.c: Added ABDL testcases. * gcc.target/aarch64/abd_3.c: Added ABDL testcases. * gcc.target/aarch64/abd_4.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_2.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_3.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_4.c: Added ABDL testcases. * gcc.target/aarch64/abd_run_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_2.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_none_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_none_2.c: Added ABDL testcases. --- gcc/config/aarch64/aarch64-simd.md | 65 ++++++++++++++ gcc/config/aarch64/iterators.md | 3 + gcc/testsuite/gcc.target/aarch64/abd_2.c | 33 +++++--- gcc/testsuite/gcc.target/aarch64/abd_3.c | 36 +++++--- gcc/testsuite/gcc.target/aarch64/abd_4.c | 34 ++++---- gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 73 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 73 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 84 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 29 +++++++ .../gcc.target/aarch64/abd_widen_2.c | 62 ++++++++++++++ .../gcc.target/aarch64/abd_widen_3.c | 62 ++++++++++++++ .../gcc.target/aarch64/abd_widen_4.c | 56 +++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 57 +++++++++++-- gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 47 +++++++++-- .../gcc.target/aarch64/sve/abd_none_1.c | 73 ++++++++++++++++ .../gcc.target/aarch64/sve/abd_none_2.c | 80 ++++++++++++++++++ 16 files changed, 811 insertions(+), 56 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_4.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bf90202ba2ad3f62f2020486d21256f083effb07..9acf0ab3067a76c0ba49d61e2857558c8482e77d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -975,6 +975,71 @@ (define_expand "aarch64_<su>abdl2<mode>" } ) +(define_insn "aarch64_<su>abdl<mode>_hi_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (abs:<VWIDE> + (minus:<VWIDE> + (ANY_EXTEND:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3))))))] + "TARGET_SIMD" + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "type" "neon_abd_long")] +) + +(define_insn "aarch64_<su>abdl<mode>_lo_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (minus:<VWIDE> + (USMAX:<VWIDE> + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3)))) + (<max_opp>:<VWIDE> + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> (match_dup 1) (match_dup 3))) + (<USMAX_EXT>:<VWIDE> + (vec_select:<VHALF> (match_dup 2) (match_dup 3))))))] + "TARGET_SIMD" + "<su>abdl\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" + [(set_attr "type" "neon_abd_long")] +) + +(define_expand "vec_widen_<su>abd_hi_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>abdl<mode>_hi_internal (operands[0], operands[1], + operands[2], p)); + DONE; + } +) + +(define_expand "vec_widen_<su>abd_lo_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); + emit_insn (gen_aarch64_<su>abdl<mode>_lo_internal (operands[0], operands[1], + operands[2], p)); + DONE; + } +) + (define_insn "aarch64_<su>abal<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (plus:<VWIDE> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d9c7354730ac5870c0042f1e30fb1140a117d110..1385842d0a51b3f4a0871af4d0bbbeeeee5299d4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1984,6 +1984,9 @@ (define_code_attr max_opp [(smax "smin") (umax "umin")]) ;; Same as above, but louder. (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")]) +;; Map smax and umax to sign_extend and zero_extend +(define_code_attr USMAX_EXT [(smax "sign_extend") (umax "zero_extend")]) + ;; The number of subvectors in an SVE_STRUCT. (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") (VNx8SI "2") (VNx4DI "2") diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c index c0d41fb7ef99baf95b0f6a2e68a88f6748482af3..9703f4906741e5cbaef14e3d11065a243603a7f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_2.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c @@ -11,25 +11,36 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, short) -TEST2(signed, char, int) -TEST2(signed, short, int) +TEST2(signed, int, short) +TEST2(signed, int, char) TEST3(signed, char, int, short) -TEST3(signed, char, short, int) +TEST3(signed, char, int, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) -TEST2(unsigned, char, short) -TEST2(unsigned, char, int) +TEST3(unsigned, short, char, short) -TEST3(unsigned, char, short, int) +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 35 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ /* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c index 4873c64f34885b3993010beafa01087569336dec..bdb4cb39fce456f05a5d18298a52677be7422731 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_3.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c @@ -11,26 +11,36 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, short) -TEST2(signed, char, int) -TEST2(signed, short, int) +TEST2(signed, int, short) +TEST2(signed, int, char) TEST3(signed, char, int, short) -TEST3(signed, char, short, int) +TEST3(signed, char, int, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) -TEST2(unsigned, char, short) -TEST2(unsigned, char, int) -TEST2(unsigned, short, int) +TEST3(unsigned, short, char, short) -TEST3(unsigned, char, short, int) +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 35 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c index 98aa730d6aad700e3a9a712e14adc08c9fb546c2..9e078f1df619ea5ab960bb2a9874f8b89b17be47 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_4.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c @@ -9,22 +9,20 @@ TEST1(signed, int) -TEST2(signed, char, short) -TEST2(signed, char, int) -TEST2(signed, short, int) - -TEST3(signed, char, short, int) - -TEST2(unsigned, char, short) -TEST2(unsigned, char, int) -TEST2(unsigned, short, int) - -TEST3(unsigned, char, short, int) - -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ - +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) + +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 7 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0:w + } } */ + +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c index 658e7426965ead945d0cad68ef721f176fb41665..d7ef2c1417b5461f8c4315d8d4911ca9f57c592c 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c @@ -7,8 +7,81 @@ #define ABD_ABS #include "abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c index 14cfdcbde6998b527989326ff8848d071a4774e8..f23dd7d06e7facff1116a9c78303993a178b1c0b 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c @@ -7,8 +7,81 @@ #define ABD_ABS #include "abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c index d612216b98bf5484783489cc48b4417ad1914b1d..f5cfc5dd73d0e4008318b7f2a9a143c98b12c88f 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c @@ -9,14 +9,98 @@ TEST1(signed, short) TEST1(signed, char) +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) TEST3(signed, char, int, short) +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) +TEST3(signed, char, long, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, long, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) +TEST2(unsigned, short, char) TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, short, char) +TEST3(unsigned, char, int, char) +TEST3(unsigned, char, long, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, char, short) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c index 7bb0a801415ffeab235bd636032112228255e836..1bfd6aca157db47b0874af7308a5fa8d61f71da2 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c @@ -11,10 +11,17 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) +TEST2(signed, char, short) +TEST2(signed, short, int) +TEST2(signed, int, long) + TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST2(unsigned, char, short) +TEST2(unsigned, short, int) + #define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } #define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 } #define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 } @@ -27,6 +34,8 @@ typedef signed short s16; typedef unsigned short u16; typedef signed int s32; typedef unsigned int u32; +typedef signed long s64; +typedef unsigned long u64; s8 sc_out[] = EMPTY; u8 uc_out[] = EMPTY; @@ -34,6 +43,8 @@ s16 ss_out[] = EMPTY; u16 us_out[] = EMPTY; s32 si_out[] = EMPTY; u32 ui_out[] = EMPTY; +s64 sl_out[] = EMPTY; +u64 ul_out[] = EMPTY; s8 sc_A[] = sA; s8 sc_B[] = B; @@ -56,6 +67,8 @@ s16 ss_gold[] = GOLD; u16 us_gold[] = GOLD; s32 si_gold[] = GOLD; u32 ui_gold[] = GOLD; +s64 sl_gold[] = GOLD; +u64 ul_gold[] = GOLD; extern void abort (void); @@ -88,6 +101,22 @@ int main () fn_unsigned_int (ui_A, ui_B, ui_out); COMPARE (ui_out, ui_gold); + + fn_signed_char_char_short (sc_B, sc_A, ss_out); + COMPARE(ss_gold, ss_out); + + fn_signed_short_short_int (ss_A, ss_B, si_out); + COMPARE(si_gold, si_out); + + fn_signed_int_int_long (si_B, si_A, sl_out); + COMPARE(sl_gold, sl_out); + + fn_unsigned_char_char_short (uc_B, uc_A, us_out); + COMPARE(us_gold, us_out); + + fn_unsigned_short_short_int (us_A, us_B, ui_out); + COMPARE(ui_gold, ui_out); + return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/abd_widen_2.c b/gcc/testsuite/gcc.target/aarch64/abd_widen_2.c new file mode 100644 index 0000000000000000000000000000000000000000..6557f0c98a24a104c0b9ec20890b85afa8ce2734 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abd_widen_2.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#pragma GCC target "+nosve" +#define N 1024 + +#define ABD_ABS +#include "abd.h" + +TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) +TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, short, char) + +TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) + +TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) + +TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_widen_3.c b/gcc/testsuite/gcc.target/aarch64/abd_widen_3.c new file mode 100644 index 0000000000000000000000000000000000000000..dfdd20e790a37dc52f838aec008332ce6d4b7a85 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abd_widen_3.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast" } */ + +#pragma GCC target "arch=armv8-a" +#define N 1024 + +#define ABD_ABS +#include "abd.h" + +TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) +TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, short, char) + +TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) + +TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) + +TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 14 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_widen_4.c b/gcc/testsuite/gcc.target/aarch64/abd_widen_4.c new file mode 100644 index 0000000000000000000000000000000000000000..298b1c614955b470669fc3987a7c4bdeb4833e5e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abd_widen_4.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#pragma GCC target "+nosve" +#define N 1024 + +#define ABD_IDIOM +#include "abd.h" + +TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) +TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) + +TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c index e49006f90b22040f890c279ec19c490a655abd63..4f4824010b14deaa2514e1a96cac6df5a1278b62 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c @@ -10,26 +10,69 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, int) TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) -TEST3(signed, char, int, short) TEST3(signed, char, short, int) +TEST3(signed, char, int, short) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, int, char) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) TEST2(unsigned, char, short) TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) +TEST3(unsigned, short, char, short) + +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 16 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 10 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 10 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c index ea64fa837b1025933ab6c339b86f0db06ffbe0e4..ffa978af9edf7248d0c262e00ffbe3546f92d3bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c @@ -7,23 +7,56 @@ #include "../abd.h" TEST1(signed, int) +TEST1(signed, long) -TEST2(signed, char, int) TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) + +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) -TEST2(unsigned, char, int) TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 4 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 8 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 6 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 6 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c index a4c2053c50e235e6ea6ad8bfb124889556be1657..1fb58b38474796bb6ed66fb098372ac81446d572 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c @@ -6,8 +6,81 @@ #define ABD_ABS #include "../abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c index 4862db93a81e890637ee8e02dcc9de9e0e613e91..a9465b56bab9aad5a6bea65055e7d928c7aabe39 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c @@ -9,13 +9,93 @@ TEST1(signed, short) TEST1(signed, char) +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) + TEST3(signed, char, int, short) +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) +TEST3(signed, char, long, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, long, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) +TEST2(unsigned, short, char) TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, short, char) +TEST3(unsigned, char, int, char) +TEST3(unsigned, char, long, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, char, short) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ -- 2.25.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] AArch64: New RTL for ABDL 2023-06-28 15:15 ` Oluwatamilore Adebayo @ 2023-06-29 10:25 ` Richard Sandiford 2023-06-30 8:25 ` Oluwatamilore Adebayo 0 siblings, 1 reply; 7+ messages in thread From: Richard Sandiford @ 2023-06-29 10:25 UTC (permalink / raw) To: Oluwatamilore Adebayo; +Cc: gcc-patches, richard.guenther Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com> writes: > From: oluade01 <oluwatamilore.adebayo@arm.com> > > This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md > (vec_widen_<su>abdl_lo_<mode>, vec_widen_<su>abdl_hi_<mode>): > Expansions for abd vec widen optabs. > (aarch64_<su>abdl<mode>_insn): VQW based abdl RTL. > * config/aarch64/iterators.md (USMAX_EXT): Code attributes > that give the appropriate extend RTL for the max RTL. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/abd_2.c: Added ABDL testcases. > * gcc.target/aarch64/abd_3.c: Added ABDL testcases. > * gcc.target/aarch64/abd_4.c: Added ABDL testcases. > * gcc.target/aarch64/abd_none_2.c: Added ABDL testcases. > * gcc.target/aarch64/abd_none_3.c: Added ABDL testcases. > * gcc.target/aarch64/abd_none_4.c: Added ABDL testcases. > * gcc.target/aarch64/abd_run_1.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_1.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_2.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_none_1.c: Added ABDL testcases. > * gcc.target/aarch64/sve/abd_none_2.c: Added ABDL testcases. > --- > gcc/config/aarch64/aarch64-simd.md | 65 ++++++++++++++ > gcc/config/aarch64/iterators.md | 3 + > gcc/testsuite/gcc.target/aarch64/abd_2.c | 33 +++++--- > gcc/testsuite/gcc.target/aarch64/abd_3.c | 36 +++++--- > gcc/testsuite/gcc.target/aarch64/abd_4.c | 34 ++++---- > gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 73 ++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 73 ++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 84 +++++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 29 +++++++ > .../gcc.target/aarch64/abd_widen_2.c | 62 ++++++++++++++ > .../gcc.target/aarch64/abd_widen_3.c | 62 ++++++++++++++ > .../gcc.target/aarch64/abd_widen_4.c | 56 +++++++++++++ > gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 57 +++++++++++-- > gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 47 +++++++++-- > .../gcc.target/aarch64/sve/abd_none_1.c | 73 ++++++++++++++++ > .../gcc.target/aarch64/sve/abd_none_2.c | 80 ++++++++++++++++++ > 16 files changed, 811 insertions(+), 56 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_2.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_3.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_4.c > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > index bf90202ba2ad3f62f2020486d21256f083effb07..9acf0ab3067a76c0ba49d61e2857558c8482e77d 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -975,6 +975,71 @@ (define_expand "aarch64_<su>abdl2<mode>" > } > ) > > +(define_insn "aarch64_<su>abdl<mode>_hi_internal" > + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > + (abs:<VWIDE> > + (minus:<VWIDE> > + (ANY_EXTEND:<VWIDE> > + (vec_select:<VHALF> > + (match_operand:VQW 1 "register_operand" "w") > + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) > + (ANY_EXTEND:<VWIDE> > + (vec_select:<VHALF> > + (match_operand:VQW 2 "register_operand" "w") > + (match_dup 3))))))] > + "TARGET_SIMD" > + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" > + [(set_attr "type" "neon_abd_long")] > +) > + > +(define_insn "aarch64_<su>abdl<mode>_lo_internal" > + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > + (minus:<VWIDE> > + (USMAX:<VWIDE> > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> > + (match_operand:VQW 1 "register_operand" "w") > + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> > + (match_operand:VQW 2 "register_operand" "w") > + (match_dup 3)))) > + (<max_opp>:<VWIDE> > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> (match_dup 1) (match_dup 3))) > + (<USMAX_EXT>:<VWIDE> > + (vec_select:<VHALF> (match_dup 2) (match_dup 3))))))] Sorry, my fault, but I meant the comment about avoiding (minus (max…) (min…)) for both patterns, not just the first. I think the review suggestions for 1/2 will change the tests. For example: TEST2(signed, short, char) shouldn't use IFN_WIDEN_ABD, since: .L2: ldr q30, [x5, x3] ldr q28, [x4, x3] ldr q31, [x0, x3] ldr q29, [x1, x3] add x3, x3, 32 sabd v30.8h, v30.8h, v28.8h sabd v31.8h, v31.8h, v29.8h uzp1 v31.16b, v31.16b, v30.16b str q31, [x2], 16 cmp x3, 2048 bne .L2 is better than: .L2: ldr q28, [x1, x3] ldr q29, [x0, x3] ldr q30, [x5, x3] ldr q27, [x4, x3] add x3, x3, 32 sabdl v31.4s, v29.4h, v28.4h sabdl2 v29.4s, v29.8h, v28.8h sabdl v28.4s, v30.4h, v27.4h sabdl2 v30.4s, v30.8h, v27.8h uzp1 v31.8h, v31.8h, v29.8h uzp1 v30.8h, v28.8h, v30.8h uzp1 v31.16b, v31.16b, v30.16b str q31, [x2], 16 cmp x3, 2048 bne .L2 LGTM with the tests updated to match. Thanks, Richard ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] AArch64: New RTL for ABDL 2023-06-29 10:25 ` Richard Sandiford @ 2023-06-30 8:25 ` Oluwatamilore Adebayo 2023-06-30 8:26 ` Oluwatamilore Adebayo 0 siblings, 1 reply; 7+ messages in thread From: Oluwatamilore Adebayo @ 2023-06-30 8:25 UTC (permalink / raw) To: richard.sandiford; +Cc: gcc-patches, oluwatamilore.adebayo, richard.guenther > Sorry, my fault, but I meant the comment about avoiding > (minus (max…) (min…)) for both patterns, not just the first. Change made. > I think the review suggestions for 1/2 will change the tests. > For example: > > TEST2(signed, short, char) This is the case and the tests have been updated to reflect it. Updated patch in next email. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] AArch64: New RTL for ABDL 2023-06-30 8:25 ` Oluwatamilore Adebayo @ 2023-06-30 8:26 ` Oluwatamilore Adebayo 0 siblings, 0 replies; 7+ messages in thread From: Oluwatamilore Adebayo @ 2023-06-30 8:26 UTC (permalink / raw) To: oluwatamilore.adebayo; +Cc: gcc-patches, richard.guenther, richard.sandiford From: oluade01 <oluwatamilore.adebayo@arm.com> This patch adds new RTL for ABDL (sabdl, sabdl2, uabdl, uabdl2). gcc/ChangeLog: * config/aarch64/aarch64-simd.md (vec_widen_<su>abdl_lo_<mode>, vec_widen_<su>abdl_hi_<mode>): Expansions for abd vec widen optabs. (aarch64_<su>abdl<mode>_insn): VQW based abdl RTL. * config/aarch64/iterators.md (USMAX_EXT): Code attributes that give the appropriate extend RTL for the max RTL. gcc/testsuite/ChangeLog: * gcc.target/aarch64/abd_2.c: Added ABDL testcases. * gcc.target/aarch64/abd_3.c: Added ABDL testcases. * gcc.target/aarch64/abd_4.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_2.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_3.c: Added ABDL testcases. * gcc.target/aarch64/abd_none_4.c: Added ABDL testcases. * gcc.target/aarch64/abd_run_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_2.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_none_1.c: Added ABDL testcases. * gcc.target/aarch64/sve/abd_none_2.c: Added ABDL testcases. --- gcc/config/aarch64/aarch64-simd.md | 60 +++++++++++++ gcc/config/aarch64/iterators.md | 3 + gcc/testsuite/gcc.target/aarch64/abd_2.c | 45 +++++++--- gcc/testsuite/gcc.target/aarch64/abd_3.c | 46 +++++++--- gcc/testsuite/gcc.target/aarch64/abd_4.c | 34 ++++---- gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 73 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 73 ++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 84 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 29 +++++++ .../gcc.target/aarch64/abd_widen_2.c | 50 +++++++++++ .../gcc.target/aarch64/abd_widen_3.c | 50 +++++++++++ .../gcc.target/aarch64/abd_widen_4.c | 56 +++++++++++++ gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 57 +++++++++++-- gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 47 +++++++++-- .../gcc.target/aarch64/sve/abd_none_1.c | 73 ++++++++++++++++ .../gcc.target/aarch64/sve/abd_none_2.c | 80 ++++++++++++++++++ 16 files changed, 803 insertions(+), 57 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_widen_4.c diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bf90202ba2ad3f62f2020486d21256f083effb07..fddf40da57693e8158b17e6045b2a064552ad273 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -975,6 +975,66 @@ (define_expand "aarch64_<su>abdl2<mode>" } ) +(define_insn "aarch64_<su>abdl<mode>_hi_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (abs:<VWIDE> + (minus:<VWIDE> + (ANY_EXTEND:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) + (ANY_EXTEND:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3))))))] + "TARGET_SIMD" + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" + [(set_attr "type" "neon_abd_long")] +) + +(define_insn "aarch64_<su>abdl<mode>_lo_internal" + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") + (abs:<VWIDE> + (minus:<VWIDE> + (ANY_EXTEND:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 1 "register_operand" "w") + (match_operand:VQW 3 "vect_par_cnst_lo_half" ""))) + (ANY_EXTEND:<VWIDE> + (vec_select:<VHALF> + (match_operand:VQW 2 "register_operand" "w") + (match_dup 3))))))] + "TARGET_SIMD" + "<su>abdl\t%0.<Vwtype>, %1.<Vhalftype>, %2.<Vhalftype>" + [(set_attr "type" "neon_abd_long")] +) + +(define_expand "vec_widen_<su>abd_hi_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true); + emit_insn (gen_aarch64_<su>abdl<mode>_hi_internal (operands[0], operands[1], + operands[2], p)); + DONE; + } +) + +(define_expand "vec_widen_<su>abd_lo_<mode>" + [(match_operand:<VWIDE> 0 "register_operand") + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand")) + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))] + "TARGET_SIMD" + { + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false); + emit_insn (gen_aarch64_<su>abdl<mode>_lo_internal (operands[0], operands[1], + operands[2], p)); + DONE; + } +) + (define_insn "aarch64_<su>abal<mode>" [(set (match_operand:<VWIDE> 0 "register_operand" "=w") (plus:<VWIDE> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index d9c7354730ac5870c0042f1e30fb1140a117d110..1385842d0a51b3f4a0871af4d0bbbeeeee5299d4 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1984,6 +1984,9 @@ (define_code_attr max_opp [(smax "smin") (umax "umin")]) ;; Same as above, but louder. (define_code_attr MAX_OPP [(smax "SMIN") (umax "UMIN")]) +;; Map smax and umax to sign_extend and zero_extend +(define_code_attr USMAX_EXT [(smax "sign_extend") (umax "zero_extend")]) + ;; The number of subvectors in an SVE_STRUCT. (define_mode_attr vector_count [(VNx32QI "2") (VNx16HI "2") (VNx8SI "2") (VNx4DI "2") diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c index c0d41fb7ef99baf95b0f6a2e68a88f6748482af3..02256c044940094de29dd6a5fc6141100a8f2963 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_2.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c @@ -11,25 +11,46 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, short) -TEST2(signed, char, int) -TEST2(signed, short, int) +TEST2(signed, short, char) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, long) TEST3(signed, char, int, short) -TEST3(signed, char, short, int) +TEST3(signed, char, int, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) TEST1(unsigned, short) TEST1(unsigned, char) -TEST2(unsigned, char, short) -TEST2(unsigned, char, int) +TEST2(unsigned, short, char) + +TEST3(unsigned, char, short, char) +TEST3(unsigned, short, char, short) -TEST3(unsigned, char, short, int) +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 48 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 7 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 7 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c index 4873c64f34885b3993010beafa01087569336dec..cc601ac446f983fcad8f6714c6b244d8cb6b669d 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_3.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c @@ -11,26 +11,46 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, short) -TEST2(signed, char, int) -TEST2(signed, short, int) +TEST2(signed, short, char) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, long) TEST3(signed, char, int, short) -TEST3(signed, char, short, int) +TEST3(signed, char, int, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) TEST1(unsigned, short) TEST1(unsigned, char) -TEST2(unsigned, char, short) -TEST2(unsigned, char, int) -TEST2(unsigned, short, int) +TEST2(unsigned, short, char) + +TEST3(unsigned, char, short, char) +TEST3(unsigned, short, char, short) -TEST3(unsigned, char, short, int) +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 48 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 7 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 7 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c index 98aa730d6aad700e3a9a712e14adc08c9fb546c2..9e078f1df619ea5ab960bb2a9874f8b89b17be47 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_4.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c @@ -9,22 +9,20 @@ TEST1(signed, int) -TEST2(signed, char, short) -TEST2(signed, char, int) -TEST2(signed, short, int) - -TEST3(signed, char, short, int) - -TEST2(unsigned, char, short) -TEST2(unsigned, char, int) -TEST2(unsigned, short, int) - -TEST3(unsigned, char, short, int) - -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */ - +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) + +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 7 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0 } } */ + +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 0:w + } } */ + +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c index 658e7426965ead945d0cad68ef721f176fb41665..d7ef2c1417b5461f8c4315d8d4911ca9f57c592c 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c @@ -7,8 +7,81 @@ #define ABD_ABS #include "abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c index 14cfdcbde6998b527989326ff8848d071a4774e8..f23dd7d06e7facff1116a9c78303993a178b1c0b 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c @@ -7,8 +7,81 @@ #define ABD_ABS #include "abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c index d612216b98bf5484783489cc48b4417ad1914b1d..f5cfc5dd73d0e4008318b7f2a9a143c98b12c88f 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c @@ -9,14 +9,98 @@ TEST1(signed, short) TEST1(signed, char) +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) TEST3(signed, char, int, short) +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) +TEST3(signed, char, long, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, long, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) +TEST2(unsigned, short, char) TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, short, char) +TEST3(unsigned, char, int, char) +TEST3(unsigned, char, long, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, char, short) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c index 7bb0a801415ffeab235bd636032112228255e836..1bfd6aca157db47b0874af7308a5fa8d61f71da2 100644 --- a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c +++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c @@ -11,10 +11,17 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) +TEST2(signed, char, short) +TEST2(signed, short, int) +TEST2(signed, int, long) + TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST2(unsigned, char, short) +TEST2(unsigned, short, int) + #define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } #define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 } #define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 } @@ -27,6 +34,8 @@ typedef signed short s16; typedef unsigned short u16; typedef signed int s32; typedef unsigned int u32; +typedef signed long s64; +typedef unsigned long u64; s8 sc_out[] = EMPTY; u8 uc_out[] = EMPTY; @@ -34,6 +43,8 @@ s16 ss_out[] = EMPTY; u16 us_out[] = EMPTY; s32 si_out[] = EMPTY; u32 ui_out[] = EMPTY; +s64 sl_out[] = EMPTY; +u64 ul_out[] = EMPTY; s8 sc_A[] = sA; s8 sc_B[] = B; @@ -56,6 +67,8 @@ s16 ss_gold[] = GOLD; u16 us_gold[] = GOLD; s32 si_gold[] = GOLD; u32 ui_gold[] = GOLD; +s64 sl_gold[] = GOLD; +u64 ul_gold[] = GOLD; extern void abort (void); @@ -88,6 +101,22 @@ int main () fn_unsigned_int (ui_A, ui_B, ui_out); COMPARE (ui_out, ui_gold); + + fn_signed_char_char_short (sc_B, sc_A, ss_out); + COMPARE(ss_gold, ss_out); + + fn_signed_short_short_int (ss_A, ss_B, si_out); + COMPARE(si_gold, si_out); + + fn_signed_int_int_long (si_B, si_A, sl_out); + COMPARE(sl_gold, sl_out); + + fn_unsigned_char_char_short (uc_B, uc_A, us_out); + COMPARE(us_gold, us_out); + + fn_unsigned_short_short_int (us_A, us_B, ui_out); + COMPARE(ui_gold, ui_out); + return 0; } diff --git a/gcc/testsuite/gcc.target/aarch64/abd_widen_2.c b/gcc/testsuite/gcc.target/aarch64/abd_widen_2.c new file mode 100644 index 0000000000000000000000000000000000000000..1be1e40dabe3ff17ab391f6ececace6473791fe5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abd_widen_2.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#pragma GCC target "+nosve" +#define N 1024 + +#define ABD_ABS +#include "abd.h" + +TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) +TEST2(signed, short, int) +TEST2(signed, short, long) + +TEST3(signed, char, short, int) +TEST3(signed, char, short, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) + +TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_widen_3.c b/gcc/testsuite/gcc.target/aarch64/abd_widen_3.c new file mode 100644 index 0000000000000000000000000000000000000000..ff6ee8f0538ca7596c43e17c60837ba25f2ae738 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abd_widen_3.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast" } */ + +#pragma GCC target "arch=armv8-a" +#define N 1024 + +#define ABD_ABS +#include "abd.h" + +TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) +TEST2(signed, short, int) +TEST2(signed, short, long) + +TEST3(signed, char, short, int) +TEST3(signed, char, short, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) + +TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/abd_widen_4.c b/gcc/testsuite/gcc.target/aarch64/abd_widen_4.c new file mode 100644 index 0000000000000000000000000000000000000000..298b1c614955b470669fc3987a7c4bdeb4833e5e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/abd_widen_4.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#pragma GCC target "+nosve" +#define N 1024 + +#define ABD_IDIOM +#include "abd.h" + +TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) +TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) + +TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) +TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 13 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "sabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "sabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.2d, v\[0-9\]+\.2s, v\[0-9\]+\.2s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 0 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.4s, v\[0-9\]+\.4h, v\[0-9\]+\.4h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 10 } } */ +/* { dg-final { scan-assembler-times "uabdl\\tv\[0-9\]+\.8h, v\[0-9\]+\.8b, v\[0-9\]+\.8b" 3 } } */ +/* { dg-final { scan-assembler-times "uabdl2\\tv\[0-9\]+\.8h, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */ + +/* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c index e49006f90b22040f890c279ec19c490a655abd63..4f4824010b14deaa2514e1a96cac6df5a1278b62 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c @@ -10,26 +10,69 @@ TEST1(signed, int) TEST1(signed, short) TEST1(signed, char) -TEST2(signed, char, int) TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) + +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) -TEST3(signed, char, int, short) TEST3(signed, char, short, int) +TEST3(signed, char, int, short) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) + +TEST3(signed, short, char, int) +TEST3(signed, short, int, char) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) TEST1(unsigned, short) TEST1(unsigned, char) TEST2(unsigned, char, short) TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) + +TEST2(unsigned, short, char) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) +TEST3(unsigned, char, short, char) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) +TEST3(unsigned, short, char, short) + +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 16 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 10 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 10 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c index ea64fa837b1025933ab6c339b86f0db06ffbe0e4..ffa978af9edf7248d0c262e00ffbe3546f92d3bc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c @@ -7,23 +7,56 @@ #include "../abd.h" TEST1(signed, int) +TEST1(signed, long) -TEST2(signed, char, int) TEST2(signed, char, short) +TEST2(signed, char, int) +TEST2(signed, char, long) TEST2(signed, short, int) +TEST2(signed, short, long) +TEST2(signed, int, long) TEST3(signed, char, short, int) +TEST3(signed, char, short, long) +TEST3(signed, char, int, long) + +TEST3(signed, short, char, int) +TEST3(signed, short, char, long) +TEST3(signed, short, int, long) + +TEST3(signed, int, char, long) +TEST3(signed, int, short, long) +TEST3(signed, int, char, int) +TEST3(signed, int, short, int) + +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) -TEST2(unsigned, char, int) TEST2(unsigned, char, short) +TEST2(unsigned, char, int) +TEST2(unsigned, char, long) TEST2(unsigned, short, int) +TEST2(unsigned, short, long) TEST3(unsigned, char, short, int) +TEST3(unsigned, char, short, long) + +TEST3(unsigned, short, char, int) +TEST3(unsigned, short, char, long) + +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 4 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 8 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 6 } } */ +/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 1 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ -/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */ -/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.d, p\[0-9\]/m, z\[0-9\]+\.d, z\[0-9\]+\.d" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 0 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 6 } } */ +/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tabs\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c index a4c2053c50e235e6ea6ad8bfb124889556be1657..1fb58b38474796bb6ed66fb098372ac81446d572 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c @@ -6,8 +6,81 @@ #define ABD_ABS #include "../abd.h" +TEST1(signed, long) + +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) + +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, long, char) + +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, long, short) + +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) +TEST3(signed, long, char, long) +TEST3(signed, long, short, long) +TEST3(signed, long, int, long) + TEST1(unsigned, int) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) + TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, int, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c index 4862db93a81e890637ee8e02dcc9de9e0e613e91..a9465b56bab9aad5a6bea65055e7d928c7aabe39 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c @@ -9,13 +9,93 @@ TEST1(signed, short) TEST1(signed, char) +TEST2(signed, long, char) +TEST2(signed, long, short) +TEST2(signed, long, int) +TEST2(signed, int, short) +TEST2(signed, int, char) +TEST2(signed, short, char) + TEST3(signed, char, int, short) +TEST3(signed, char, long, short) +TEST3(signed, char, long, int) +TEST3(signed, char, short, char) +TEST3(signed, char, int, char) +TEST3(signed, char, long, char) + +TEST3(signed, short, int, char) +TEST3(signed, short, long, char) +TEST3(signed, short, long, int) +TEST3(signed, short, char, short) +TEST3(signed, short, int, short) +TEST3(signed, short, long, short) + +TEST3(signed, int, char, short) +TEST3(signed, int, short, char) +TEST3(signed, int, long, char) +TEST3(signed, int, long, short) +TEST3(signed, int, long, int) + +TEST3(signed, long, char, short) +TEST3(signed, long, short, char) +TEST3(signed, long, char, int) +TEST3(signed, long, int, char) +TEST3(signed, long, short, int) +TEST3(signed, long, int, short) TEST1(unsigned, int) TEST1(unsigned, short) TEST1(unsigned, char) +TEST1(unsigned, long) + +TEST2(unsigned, int, long) + +TEST2(unsigned, long, char) +TEST2(unsigned, long, short) +TEST2(unsigned, long, int) +TEST2(unsigned, int, short) +TEST2(unsigned, int, char) +TEST2(unsigned, short, char) TEST3(unsigned, char, int, short) +TEST3(unsigned, char, long, short) +TEST3(unsigned, char, int, long) +TEST3(unsigned, char, long, int) +TEST3(unsigned, char, short, char) +TEST3(unsigned, char, int, char) +TEST3(unsigned, char, long, char) + +TEST3(unsigned, short, int, char) +TEST3(unsigned, short, long, char) +TEST3(unsigned, short, int, long) +TEST3(unsigned, short, long, int) +TEST3(unsigned, short, char, short) +TEST3(unsigned, short, int, short) +TEST3(unsigned, short, long, short) + +TEST3(unsigned, int, char, short) +TEST3(unsigned, int, short, char) +TEST3(unsigned, int, char, long) +TEST3(unsigned, int, long, char) +TEST3(unsigned, int, short, long) +TEST3(unsigned, int, long, short) +TEST3(unsigned, int, char, int) +TEST3(unsigned, int, short, int) +TEST3(unsigned, int, long, int) + +TEST3(unsigned, long, char, short) +TEST3(unsigned, long, short, char) +TEST3(unsigned, long, char, int) +TEST3(unsigned, long, int, char) +TEST3(unsigned, long, short, int) +TEST3(unsigned, long, int, short) +TEST3(unsigned, long, char, long) +TEST3(unsigned, long, short, long) +TEST3(unsigned, long, int, long) /* { dg-final { scan-assembler-not {\tsabd\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tsabdl2\t} } } */ /* { dg-final { scan-assembler-not {\tuabd\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl\t} } } */ +/* { dg-final { scan-assembler-not {\tuabdl2\t} } } */ -- 2.25.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-06-30 8:27 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-06-26 15:34 [PATCH 2/2] AArch64: New RTL for ABDL Oluwatamilore Adebayo 2023-06-26 20:54 ` Richard Sandiford 2023-06-28 15:14 ` Oluwatamilore Adebayo 2023-06-28 15:15 ` Oluwatamilore Adebayo 2023-06-29 10:25 ` Richard Sandiford 2023-06-30 8:25 ` Oluwatamilore Adebayo 2023-06-30 8:26 ` Oluwatamilore Adebayo
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