Re: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P

[Jeff Law <jeffreyalaw@gmail.com>]

On 1/22/24 6:30 AM, Mary Bennett wrote:
> 
> On 09/01/2024 18:43, Jeff Law wrote:
>>
>>
>> On 1/8/24 06:14, Mary Bennett wrote:
>>> Spec: github.com/openhwgroup/core-v-sw/blob/master/specifications/ 
>>> corev-builtin-spec.md
>>>
>>> Contributors:
>>>    Mary Bennett <mary.bennett@embecosm.com>
>>>    Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>>>    Pietra Ferreira <pietra.ferreira@embecosm.com>
>>>    Charlie Keaney
>>>    Jessica Mills
>>>    Craig Blackmore <craig.blackmore@embecosm.com>
>>>    Simon Cook <simon.cook@embecosm.com>
>>>    Jeremy Bennett <jeremy.bennett@embecosm.com>
>>>    Helene Chelin <helene.chelin@embecosm.com>
>>>
>>> gcc/ChangeLog:
>>>     * common/config/riscv/riscv-common.cc: Create XCVbi extension
>>>       support.
>>>     * config/riscv/riscv.opt: Likewise.
>>>     * config/riscv/corev.md: Implement cv_branch<mode> pattern
>>>       for cv.beqimm and cv.bneimm.
>>>     * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
>>>       branch instruction pattern.
>>>     * config/riscv/constraints.md: Implement constraints
>>>       cv_bi_s5 - signed 5-bit immediate.
>>>     * config/riscv/predicates.md: Implement predicate
>>>       const_int5s_operand - signed 5 bit immediate.
>>>     * doc/sourcebuild.texi: Add XCVbi documentation.
>>>
>>> gcc/testsuite/ChangeLog:
>>>     * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
>>>     * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
>>>     * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
>>>     * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
>>>     * lib/target-supports.exp: Add proc for XCVbi.
>> Assuming this has gone through a testing cycle, this is fine for the 
>> trunk.
>>
>> Thanks,
>> jeff
> 
> This patch passes regression. Are there any other changes required 
> before it can be merged?
I pushed this to the trunk.  Sorry for the delays.

jeff