From: Mary Bennett <mary.bennett@embecosm.com>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org, Mary Bennett <mary.bennett@embecosm.com>
Subject: Re: [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P
Date: Mon, 22 Jan 2024 13:30:15 +0000 [thread overview]
Message-ID: <336ed48f-0643-41eb-9fd2-29494cda7bea@embecosm.com> (raw)
In-Reply-To: <623765fe-16e6-4065-81ba-6c3426e9388c@gmail.com>
[-- Attachment #1.1.1: Type: text/plain, Size: 1914 bytes --]
On 09/01/2024 18:43, Jeff Law wrote:
>
>
> On 1/8/24 06:14, Mary Bennett wrote:
>> Spec:
>> github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>>
>> Contributors:
>> Mary Bennett <mary.bennett@embecosm.com>
>> Nandni Jamnadas <nandni.jamnadas@embecosm.com>
>> Pietra Ferreira <pietra.ferreira@embecosm.com>
>> Charlie Keaney
>> Jessica Mills
>> Craig Blackmore <craig.blackmore@embecosm.com>
>> Simon Cook <simon.cook@embecosm.com>
>> Jeremy Bennett <jeremy.bennett@embecosm.com>
>> Helene Chelin <helene.chelin@embecosm.com>
>>
>> gcc/ChangeLog:
>> * common/config/riscv/riscv-common.cc: Create XCVbi extension
>> support.
>> * config/riscv/riscv.opt: Likewise.
>> * config/riscv/corev.md: Implement cv_branch<mode> pattern
>> for cv.beqimm and cv.bneimm.
>> * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
>> branch instruction pattern.
>> * config/riscv/constraints.md: Implement constraints
>> cv_bi_s5 - signed 5-bit immediate.
>> * config/riscv/predicates.md: Implement predicate
>> const_int5s_operand - signed 5 bit immediate.
>> * doc/sourcebuild.texi: Add XCVbi documentation.
>>
>> gcc/testsuite/ChangeLog:
>> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
>> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
>> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
>> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
>> * lib/target-supports.exp: Add proc for XCVbi.
> Assuming this has gone through a testing cycle, this is fine for the
> trunk.
>
> Thanks,
> jeff
This patch passes regression. Are there any other changes required
before it can be merged?
Kind regards,
Mary
[-- Attachment #1.1.2: OpenPGP public key --]
[-- Type: application/pgp-keys, Size: 3203 bytes --]
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 840 bytes --]
next prev parent reply other threads:[~2024-01-22 13:30 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-09 17:11 ` Jeff Law
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-10 1:08 ` Jeff Law
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-10 20:24 ` Jeff Law
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-05 15:24 ` Kito Cheng
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-15 22:01 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-15 23:11 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2024-01-09 18:43 ` Jeff Law
2024-01-22 13:30 ` Mary Bennett [this message]
2024-03-19 3:34 ` Jeff Law
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=336ed48f-0643-41eb-9fd2-29494cda7bea@embecosm.com \
--to=mary.bennett@embecosm.com \
--cc=623765fe-16e6-4065-81ba-6c3426e9388c@gmail.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).