From: Kito Cheng <kito.cheng@gmail.com>
To: Mary Bennett <mary.bennett@embecosm.com>
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors
Date: Tue, 5 Dec 2023 23:11:56 +0800 [thread overview]
Message-ID: <CA+yXCZDwiP6-9VX+M7MzMKC4YPYoKdcrPpA2ue-=68m-CYKsQA@mail.gmail.com> (raw)
In-Reply-To: <20231128131615.3986922-3-mary.bennett@embecosm.com>
LGTM
On Tue, Nov 28, 2023 at 9:17 PM Mary Bennett <mary.bennett@embecosm.com> wrote:
>
> gcc/ChangeLog:
> * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
> * config/riscv/corev.md: Likewise.
> ---
> gcc/config/riscv/constraints.md | 15 ++++++++-------
> gcc/config/riscv/corev.md | 4 ++--
> 2 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 68be4515c04..2711efe68c5 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -151,13 +151,6 @@
> (define_register_constraint "zmvr" "(TARGET_ZFA || TARGET_XTHEADFMV) ? GR_REGS : NO_REGS"
> "An integer register for ZFA or XTheadFmv.")
>
> -;; CORE-V Constraints
> -(define_constraint "CVP2"
> - "Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
> - (and (match_code "const_int")
> - (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> - (match_test "exact_log2 (ival + 1) != -1"))))
> -
> ;; Vector constraints.
>
> (define_register_constraint "vr" "TARGET_VECTOR ? V_REGS : NO_REGS"
> @@ -246,3 +239,11 @@
> A MEM with a valid address for th.[l|s]*ur* instructions."
> (and (match_code "mem")
> (match_test "th_memidx_legitimate_index_p (op, true)")))
> +
> +;; CORE-V Constraints
> +(define_constraint "CV_alu_pow2"
> + "@internal
> + Checking for CORE-V ALU clip if ival plus 1 is a power of 2"
> + (and (match_code "const_int")
> + (and (match_test "IN_RANGE (ival, 0, 1073741823)")
> + (match_test "exact_log2 (ival + 1) != -1"))))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index c7a2ba07bcc..92bf0b5d6a6 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -516,7 +516,7 @@
> (define_insn "riscv_cv_alu_clip"
> [(set (match_operand:SI 0 "register_operand" "=r,r")
> (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
> - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
> + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
> UNSPEC_CV_ALU_CLIP))]
>
> "TARGET_XCVALU && !TARGET_64BIT"
> @@ -529,7 +529,7 @@
> (define_insn "riscv_cv_alu_clipu"
> [(set (match_operand:SI 0 "register_operand" "=r,r")
> (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
> - (match_operand:SI 2 "immediate_register_operand" "CVP2,r")]
> + (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
> UNSPEC_CV_ALU_CLIPU))]
>
> "TARGET_XCVALU && !TARGET_64BIT"
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-12-05 15:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-09 17:11 ` Jeff Law
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-10 1:08 ` Jeff Law
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-10 20:24 ` Jeff Law
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-05 15:11 ` Kito Cheng [this message]
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-05 15:24 ` Kito Cheng
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-15 22:01 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-15 23:11 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2024-01-09 18:43 ` Jeff Law
2024-01-22 13:30 ` Mary Bennett
2024-03-19 3:34 ` Jeff Law
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