From: Jeff Law <jeffreyalaw@gmail.com>
To: Mary Bennett <mary.bennett@embecosm.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors
Date: Thu, 9 Nov 2023 18:08:05 -0700 [thread overview]
Message-ID: <efa3c5f9-7bc4-489e-8730-a0eac6187e68@gmail.com> (raw)
In-Reply-To: <20231108110914.2710021-3-mary.bennett@embecosm.com>
On 11/8/23 04:09, Mary Bennett wrote:
> gcc/ChangeLog:
> * config/riscv/constraints.md: CVP2 -> CV_alu_pow2.
> * config/riscv/corev.md: Likewise.
Bikeshedding alert... Usually we keep constraint names pretty small. It
helps when you've got patterns that may have many constraints. I don't
see that likely happening here, so I think we're OK. But something to
keep in mind.
2^n - 1 is a pretty common constraint and normally I might suggest we
make this more generic for use elsewhere. But in this case there's a
restriction on the upper bound of 0x3fffffff, so it's not as generic as
2^n - 1 up to word size.
So OK for the trunk as-is.
jeff
next prev parent reply other threads:[~2023-11-10 1:08 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-09 17:11 ` Jeff Law
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-10 1:08 ` Jeff Law [this message]
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-10 20:24 ` Jeff Law
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-05 15:24 ` Kito Cheng
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-15 22:01 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-15 23:11 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2024-01-09 18:43 ` Jeff Law
2024-01-22 13:30 ` Mary Bennett
2024-03-19 3:34 ` Jeff Law
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