From: Jeff Law <jeffreyalaw@gmail.com>
To: Mary Bennett <mary.bennett@embecosm.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P
Date: Thu, 9 Nov 2023 10:11:43 -0700 [thread overview]
Message-ID: <5b34db93-d653-4ad4-9839-ac7fd42836e5@gmail.com> (raw)
In-Reply-To: <20231108110914.2710021-2-mary.bennett@embecosm.com>
On 11/8/23 04:09, Mary Bennett wrote:
> +;; XCVELW builtins
> +(define_insn "riscv_cv_elw_elw_si"
> + [(set (match_operand:SI 0 "register_operand" "=r")
> + (unspec_volatile [(mem:SI (match_operand:SI 1 "address_operand" "p"))]
> + UNSPECV_CV_ELW))]
> +
> + "TARGET_XCVELW && !TARGET_64BIT"
> + "cv.elw\t%0,%a1"
> +
> + [(set_attr "type" "load")
> + (set_attr "mode" "SI")])
Would it make more sense to pull the MEM into the operand? So instead
of "address_operand", you'd define a new operand predicate which
accepted (mem (...)) and that chunk of your insn looks like
(unspec_volatile [(match_operand:SI 1 "new_predicate" "")] UNSPEC_CV_ELW))]
Or something close to that.
From a quick look at the docs it looks like the addressing modes are
similar to other extensions and could be re-used.
Thoughts?
jeff
next prev parent reply other threads:[~2023-11-09 17:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-08 11:09 [PATCH 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-08 11:09 ` [PATCH 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-09 17:11 ` Jeff Law [this message]
2023-11-08 11:09 ` [PATCH 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-10 1:08 ` Jeff Law
2023-11-08 11:09 ` [PATCH 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-10 20:24 ` Jeff Law
2023-11-13 13:35 ` [PATCH v2 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-13 13:35 ` [PATCH v2 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-11-13 13:35 ` [PATCH v2 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-11-13 13:35 ` [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-11-13 14:41 ` Kito Cheng
2023-11-13 19:14 ` Patrick O'Neill
2023-11-28 13:16 ` [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-11-28 13:16 ` [PATCH v3 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-05 15:11 ` Kito Cheng
2023-11-28 13:16 ` [PATCH v3 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-05 15:24 ` Kito Cheng
2023-12-12 19:32 ` [PATCH v4 0/3] RISC-V: Support CORE-V XCVELW and XCVBI extensions Mary Bennett
2023-12-12 19:32 ` [PATCH v4 1/3] RISC-V: Add support for XCVelw extension in CV32E40P Mary Bennett
2023-12-15 22:01 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 2/3] RISC-V: Update XCValu constraints to match other vendors Mary Bennett
2023-12-15 23:11 ` Jeff Law
2023-12-12 19:32 ` [PATCH v4 3/3] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2023-12-15 23:21 ` Jeff Law
2024-01-08 13:14 ` [PATCH v5 0/1] RISC-V: Support CORE-V XCVBI extension Mary Bennett
2024-01-08 13:14 ` [PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40P Mary Bennett
2024-01-09 18:43 ` Jeff Law
2024-01-22 13:30 ` Mary Bennett
2024-03-19 3:34 ` Jeff Law
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