* [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
@ 2015-06-05 17:18 Charles Baylis
2015-06-08 9:44 ` Alan Lawrence
2015-06-08 10:08 ` Alan Lawrence
0 siblings, 2 replies; 8+ messages in thread
From: Charles Baylis @ 2015-06-05 17:18 UTC (permalink / raw)
To: GCC Patches, Alan Lawrence, Tejas Belagod, Marcus Shawcroft,
Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 11941 bytes --]
This is another attempt at fixing this PR63870 for AArch64 (ARM is
still to come).
As before, the Q register variants are handled by moving the check for
the lane bounds into builtin expansion. The handling of lane numbers
is made consistent wrt endianess with other NEON single lane
operations - lane numbers in RTL are flipped for big-endian, and
flipped back at assembly time.
The D register variants are now handled by adding new builtins for all
the 64bit operations. These behave identically to Q register variants,
except that the permitted lane bounds are different.
In the iterators used by the relevant patterns are changed from VQ and
VALLDIF so that the correct vector sizes are used in the endian-flip
at assembly time.
Finally, a set of machine-generated test cases is added. These do need
to be in separate files, because of testsuite limitations.
Regression tested on qemu for aarch64-linux-gnu with no regressions
and all new tests pass.
OK for trunk?
gcc/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
PR target/63870
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
Add qualifier_struct_load_store_lane_index.
(aarch64_types_loadstruct_lane_qualifiers): Use
qualifier_struct_load_store_lane_index for lane index argument for
last argument.
(aarch64_types_storestruct_lane_qualifiers): Ditto.
(builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_args): Add new argument describing mode of
builtin. Check lane bounds for arguments with
SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_builtin): Emit error for incorrect lane indices
if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(aarch64_simd_expand_builtin): Handle arguments with
qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
aarch64_simd_expand_args.
* config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
vst[234]_lane with BUILTIN_VALLDIF.
* config/aarch64/aarch64-simd.md:
(aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
endianness reversal on lane index.
(aarch64_vec_load_lanesci_lane<mode>): Ditto.
(aarch64_vec_load_lanesxi_lane<mode>): Ditto.
(vec_store_lanesoi_lane<mode>): Use VALLDIF iterator. Fix typo
in attribute.
(vec_store_lanesci_lane<mode>): Use VALLDIF iterator.
(vec_store_lanesxi_lane<mode>): Ditto.
(aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
reversal of lane index.
(aarch64_ld3_lane<mode>): Ditto.
(aarch64_ld4_lane<mode>): Ditto.
(aarch64_st2_lane<mode>): Ditto.
(aarch64_st3_lane<mode>): Ditto.
(aarch64_st4_lane<mode>): Ditto.
* config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
to qmode. Add new mode parameter. Update uses.
(__LD3_LANE_FUNC): Ditto.
(__LD4_LANE_FUNC): Ditto.
(__ST2_LANE_FUNC): Ditto.
(__ST3_LANE_FUNC): Ditto.
(__ST4_LANE_FUNC): Ditto.
<DATE> Charles Baylis <charles.baylis@linaro.org>
* gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c: New test.
* gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c: New test.
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
2015-06-05 17:18 [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics Charles Baylis
@ 2015-06-08 9:44 ` Alan Lawrence
2015-06-10 9:35 ` Charles Baylis
2015-06-08 10:08 ` Alan Lawrence
1 sibling, 1 reply; 8+ messages in thread
From: Alan Lawrence @ 2015-06-08 9:44 UTC (permalink / raw)
To: Charles Baylis
Cc: GCC Patches, Tejas Belagod, Marcus Shawcroft, Richard Earnshaw
Thanks for working on this!
I'd been fiddling around with a patch with some similar elements to this, but
many trials with union types, subregs, etc., all worsened the register
allocation and led to more unnecessary shuffling / moves. The only real thing I
tried which you don't do here, was to introduce a set_dreg expander to clean up
some of those macro definitions in arm_neon.h. That could easily follow in a
separate patch if desired!
So your patch looks good to me.
A couple of style nits:
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -128,7 +128,9 @@ enum aarch64_type_qualifiers
/* Polynomial types. */
qualifier_poly = 0x100,
/* Lane indices - must be in range, and flipped for bigendian. */
- qualifier_lane_index = 0x200
+ qualifier_lane_index = 0x200,
+ /* Lane indices for single lane structure loads and stores */
+ qualifier_struct_load_store_lane_index = 0x400
};
should be ...'loads and stores. */'
also the dg-error messages in the testsuite, do not need to be on the same line
as the statement generating the error, because the trailing 0 tells dg that the
position/line number doesn't matter (i.e. dg should allow the error to be
reported at any line); so these could be brought under 80 chars.
Thanks, Alan
Charles Baylis wrote:
> This is another attempt at fixing this PR63870 for AArch64 (ARM is
> still to come).
>
> As before, the Q register variants are handled by moving the check for
> the lane bounds into builtin expansion. The handling of lane numbers
> is made consistent wrt endianess with other NEON single lane
> operations - lane numbers in RTL are flipped for big-endian, and
> flipped back at assembly time.
>
> The D register variants are now handled by adding new builtins for all
> the 64bit operations. These behave identically to Q register variants,
> except that the permitted lane bounds are different.
>
> In the iterators used by the relevant patterns are changed from VQ and
> VALLDIF so that the correct vector sizes are used in the endian-flip
> at assembly time.
>
> Finally, a set of machine-generated test cases is added. These do need
> to be in separate files, because of testsuite limitations.
>
> Regression tested on qemu for aarch64-linux-gnu with no regressions
> and all new tests pass.
>
> OK for trunk?
>
>
> gcc/ChangeLog:
>
> <DATE> Charles Baylis <charles.baylis@linaro.org>
>
> PR target/63870
> * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
> Add qualifier_struct_load_store_lane_index.
> (aarch64_types_loadstruct_lane_qualifiers): Use
> qualifier_struct_load_store_lane_index for lane index argument for
> last argument.
> (aarch64_types_storestruct_lane_qualifiers): Ditto.
> (builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
> (aarch64_simd_expand_args): Add new argument describing mode of
> builtin. Check lane bounds for arguments with
> SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
> (aarch64_simd_expand_builtin): Emit error for incorrect lane indices
> if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
> (aarch64_simd_expand_builtin): Handle arguments with
> qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
> aarch64_simd_expand_args.
> * config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
> vst[234]_lane with BUILTIN_VALLDIF.
> * config/aarch64/aarch64-simd.md:
> (aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
> endianness reversal on lane index.
> (aarch64_vec_load_lanesci_lane<mode>): Ditto.
> (aarch64_vec_load_lanesxi_lane<mode>): Ditto.
> (vec_store_lanesoi_lane<mode>): Use VALLDIF iterator. Fix typo
> in attribute.
> (vec_store_lanesci_lane<mode>): Use VALLDIF iterator.
> (vec_store_lanesxi_lane<mode>): Ditto.
> (aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
> reversal of lane index.
> (aarch64_ld3_lane<mode>): Ditto.
> (aarch64_ld4_lane<mode>): Ditto.
> (aarch64_st2_lane<mode>): Ditto.
> (aarch64_st3_lane<mode>): Ditto.
> (aarch64_st4_lane<mode>): Ditto.
> * config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
> to qmode. Add new mode parameter. Update uses.
> (__LD3_LANE_FUNC): Ditto.
> (__LD4_LANE_FUNC): Ditto.
> (__ST2_LANE_FUNC): Ditto.
> (__ST3_LANE_FUNC): Ditto.
> (__ST4_LANE_FUNC): Ditto.
>
>
> <DATE> Charles Baylis <charles.baylis@linaro.org>
>
> * gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c: New test.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
2015-06-05 17:18 [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics Charles Baylis
2015-06-08 9:44 ` Alan Lawrence
@ 2015-06-08 10:08 ` Alan Lawrence
[not found] ` <CADnVucBF-Oc3mzsRxNzFkbqH5rvc8QNJBjZNvF9UD5QQ9tMPVw@mail.gmail.com>
1 sibling, 1 reply; 8+ messages in thread
From: Alan Lawrence @ 2015-06-08 10:08 UTC (permalink / raw)
To: Charles Baylis
Cc: GCC Patches, Tejas Belagod, Marcus Shawcroft, Richard Earnshaw
Oh, have you tested bigendian?
--Alan
Charles Baylis wrote:
> This is another attempt at fixing this PR63870 for AArch64 (ARM is
> still to come).
>
> As before, the Q register variants are handled by moving the check for
> the lane bounds into builtin expansion. The handling of lane numbers
> is made consistent wrt endianess with other NEON single lane
> operations - lane numbers in RTL are flipped for big-endian, and
> flipped back at assembly time.
>
> The D register variants are now handled by adding new builtins for all
> the 64bit operations. These behave identically to Q register variants,
> except that the permitted lane bounds are different.
>
> In the iterators used by the relevant patterns are changed from VQ and
> VALLDIF so that the correct vector sizes are used in the endian-flip
> at assembly time.
>
> Finally, a set of machine-generated test cases is added. These do need
> to be in separate files, because of testsuite limitations.
>
> Regression tested on qemu for aarch64-linux-gnu with no regressions
> and all new tests pass.
>
> OK for trunk?
>
>
> gcc/ChangeLog:
>
> <DATE> Charles Baylis <charles.baylis@linaro.org>
>
> PR target/63870
> * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
> Add qualifier_struct_load_store_lane_index.
> (aarch64_types_loadstruct_lane_qualifiers): Use
> qualifier_struct_load_store_lane_index for lane index argument for
> last argument.
> (aarch64_types_storestruct_lane_qualifiers): Ditto.
> (builtin_simd_arg): Add SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
> (aarch64_simd_expand_args): Add new argument describing mode of
> builtin. Check lane bounds for arguments with
> SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
> (aarch64_simd_expand_builtin): Emit error for incorrect lane indices
> if marked with SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
> (aarch64_simd_expand_builtin): Handle arguments with
> qualifier_struct_load_store_lane_index. Pass machine mode of builtin to
> aarch64_simd_expand_args.
> * config/aarch64/aarch64-simd-builtins.def: Declare ld[234]_lane and
> vst[234]_lane with BUILTIN_VALLDIF.
> * config/aarch64/aarch64-simd.md:
> (aarch64_vec_load_lanesoi_lane<mode>): Use VALLDIF iterator. Perform
> endianness reversal on lane index.
> (aarch64_vec_load_lanesci_lane<mode>): Ditto.
> (aarch64_vec_load_lanesxi_lane<mode>): Ditto.
> (vec_store_lanesoi_lane<mode>): Use VALLDIF iterator. Fix typo
> in attribute.
> (vec_store_lanesci_lane<mode>): Use VALLDIF iterator.
> (vec_store_lanesxi_lane<mode>): Ditto.
> (aarch64_ld2_lane<mode>): Use VALLDIF iterator. Remove endianness
> reversal of lane index.
> (aarch64_ld3_lane<mode>): Ditto.
> (aarch64_ld4_lane<mode>): Ditto.
> (aarch64_st2_lane<mode>): Ditto.
> (aarch64_st3_lane<mode>): Ditto.
> (aarch64_st4_lane<mode>): Ditto.
> * config/aarch64/arm_neon.h (__LD2_LANE_FUNC): Rename mode parameter
> to qmode. Add new mode parameter. Update uses.
> (__LD3_LANE_FUNC): Ditto.
> (__LD4_LANE_FUNC): Ditto.
> (__ST2_LANE_FUNC): Ditto.
> (__ST3_LANE_FUNC): Ditto.
> (__ST4_LANE_FUNC): Ditto.
>
>
> <DATE> Charles Baylis <charles.baylis@linaro.org>
>
> * gcc.target/aarch64/simd/vld2_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld2q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld3q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vld4q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst2q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst3q_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4_lane_u8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_f32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_f64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_p8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_s8_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u16_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u32_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u64_indices_1.c: New test.
> * gcc.target/aarch64/simd/vst4q_lane_u8_indices_1.c: New test.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
2015-06-08 9:44 ` Alan Lawrence
@ 2015-06-10 9:35 ` Charles Baylis
2015-06-10 13:01 ` Alan Lawrence
0 siblings, 1 reply; 8+ messages in thread
From: Charles Baylis @ 2015-06-10 9:35 UTC (permalink / raw)
To: Alan Lawrence
Cc: GCC Patches, Tejas Belagod, Marcus Shawcroft, Richard Earnshaw
On 8 June 2015 at 10:33, Alan Lawrence <alan.lawrence@arm.com> wrote:
> Thanks for working on this!
>
> I'd been fiddling around with a patch with some similar elements to this,
> but many trials with union types, subregs, etc., all worsened the register
> allocation and led to more unnecessary shuffling / moves.
Kugan has been looking into this at Linaro. We should avoid
duplicating effort here.
> The only real
> thing I tried which you don't do here, was to introduce a set_dreg expander
> to clean up some of those macro definitions in arm_neon.h. That could easily
> follow in a separate patch if desired!
I'd prefer that to be a separate step.
> So your patch looks good to me.
>
> A couple of style nits:
>
> --- a/gcc/config/aarch64/aarch64-builtins.c
> +++ b/gcc/config/aarch64/aarch64-builtins.c
> @@ -128,7 +128,9 @@ enum aarch64_type_qualifiers
> /* Polynomial types. */
> qualifier_poly = 0x100,
> /* Lane indices - must be in range, and flipped for bigendian. */
> - qualifier_lane_index = 0x200
> + qualifier_lane_index = 0x200,
> + /* Lane indices for single lane structure loads and stores */
> + qualifier_struct_load_store_lane_index = 0x400
> };
>
> should be ...'loads and stores. */'
>
> also the dg-error messages in the testsuite, do not need to be on the same
> line as the statement generating the error, because the trailing 0 tells dg
> that the position/line number doesn't matter (i.e. dg should allow the error
> to be reported at any line); so these could be brought under 80 chars.
OK, thanks. I'll re-spin once I've tested on big endian.
> Oh, have you tested bigendian?
I have started a bigendian build on our validation infrastructure here.
Thanks for the review
Charles
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
2015-06-10 9:35 ` Charles Baylis
@ 2015-06-10 13:01 ` Alan Lawrence
0 siblings, 0 replies; 8+ messages in thread
From: Alan Lawrence @ 2015-06-10 13:01 UTC (permalink / raw)
To: Charles Baylis; +Cc: GCC Patches, Kugan
Charles Baylis wrote:
> On 8 June 2015 at 10:33, Alan Lawrence <alan.lawrence@arm.com> wrote:
>> Thanks for working on this!
>>
>> I'd been fiddling around with a patch with some similar elements to this,
>> but many trials with union types, subregs, etc., all worsened the register
>> allocation and led to more unnecessary shuffling / moves.
>
> Kugan has been looking into this at Linaro. We should avoid
> duplicating effort here.
Yes. I stopped short of looking into the internals of the register allocator,
although I believe any proper solution is going to have to make changes here.
However, I am working on (/nearly finished, just some tidying!) a patch series
to add D-registers to TARGET_ARRAY_MODE_SUPPORTED_P, which may help matters.
>> The only real
>> thing I tried which you don't do here, was to introduce a set_dreg expander
>> to clean up some of those macro definitions in arm_neon.h. That could easily
>> follow in a separate patch if desired!
>
> I'd prefer that to be a separate step.
Sure. (*If* we go that route - I hope to have another look after
aarch64_array_mode_supported_p).
Cheers,
Alan
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
[not found] ` <CADnVucBF-Oc3mzsRxNzFkbqH5rvc8QNJBjZNvF9UD5QQ9tMPVw@mail.gmail.com>
@ 2015-06-11 7:20 ` Charles Baylis
2015-06-17 14:15 ` Charles Baylis
0 siblings, 1 reply; 8+ messages in thread
From: Charles Baylis @ 2015-06-11 7:20 UTC (permalink / raw)
To: GCC Patches
Cc: Tejas Belagod, Alan Lawrence, Marcus Shawcroft, Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 480 bytes --]
[resending, as previous version was rejected from the list for html]
On 11 June 2015 at 00:38, Charles Baylis <charles.baylis@linaro.org> wrote:
>
>
> On 8 June 2015 at 10:44, Alan Lawrence <alan.lawrence@arm.com> wrote:
>> Oh, have you tested bigendian?
>
> No regressions on aarch64_be-none-elf.
>
> I re-spinned the patch with the cosmetic changes Alan suggested (comment
> punctuation, fix >80 column lines in test cases)
>
> ChangeLog remains as before.
>
> Ok for trunk?
>
[-- Attachment #2: 0001-AArch64-PR63870-Improve-error-messages-for-NEON-sing.patch --]
[-- Type: application/x-download, Size: 145839 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
2015-06-11 7:20 ` Charles Baylis
@ 2015-06-17 14:15 ` Charles Baylis
2015-06-17 16:06 ` Alan Lawrence
0 siblings, 1 reply; 8+ messages in thread
From: Charles Baylis @ 2015-06-17 14:15 UTC (permalink / raw)
To: GCC Patches, James Greenhalgh
Cc: Tejas Belagod, Alan Lawrence, Marcus Shawcroft, Richard Earnshaw
Ping?
On 11 June 2015 at 00:42, Charles Baylis <charles.baylis@linaro.org> wrote:
> [resending, as previous version was rejected from the list for html]
>
> On 11 June 2015 at 00:38, Charles Baylis <charles.baylis@linaro.org> wrote:
>>
>>
>> On 8 June 2015 at 10:44, Alan Lawrence <alan.lawrence@arm.com> wrote:
>>> Oh, have you tested bigendian?
>>
>> No regressions on aarch64_be-none-elf.
>>
>> I re-spinned the patch with the cosmetic changes Alan suggested (comment
>> punctuation, fix >80 column lines in test cases)
>>
>> ChangeLog remains as before.
>>
>> Ok for trunk?
>>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics
2015-06-17 14:15 ` Charles Baylis
@ 2015-06-17 16:06 ` Alan Lawrence
0 siblings, 0 replies; 8+ messages in thread
From: Alan Lawrence @ 2015-06-17 16:06 UTC (permalink / raw)
To: Charles Baylis
Cc: GCC Patches, James Greenhalgh, Tejas Belagod, Marcus Shawcroft,
Richard Earnshaw
Looks good to me, but I can't approve.
Thanks,
Alan
Charles Baylis wrote:
> Ping?
>
> On 11 June 2015 at 00:42, Charles Baylis <charles.baylis@linaro.org> wrote:
>> [resending, as previous version was rejected from the list for html]
>>
>> On 11 June 2015 at 00:38, Charles Baylis <charles.baylis@linaro.org> wrote:
>>>
>>> On 8 June 2015 at 10:44, Alan Lawrence <alan.lawrence@arm.com> wrote:
>>>> Oh, have you tested bigendian?
>>> No regressions on aarch64_be-none-elf.
>>>
>>> I re-spinned the patch with the cosmetic changes Alan suggested (comment
>>> punctuation, fix >80 column lines in test cases)
>>>
>>> ChangeLog remains as before.
>>>
>>> Ok for trunk?
>>>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-06-17 15:41 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-05 17:18 [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics Charles Baylis
2015-06-08 9:44 ` Alan Lawrence
2015-06-10 9:35 ` Charles Baylis
2015-06-10 13:01 ` Alan Lawrence
2015-06-08 10:08 ` Alan Lawrence
[not found] ` <CADnVucBF-Oc3mzsRxNzFkbqH5rvc8QNJBjZNvF9UD5QQ9tMPVw@mail.gmail.com>
2015-06-11 7:20 ` Charles Baylis
2015-06-17 14:15 ` Charles Baylis
2015-06-17 16:06 ` Alan Lawrence
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