* [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages
@ 2015-10-07 0:00 charles.baylis
2015-10-07 0:00 ` [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier charles.baylis
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: charles.baylis @ 2015-10-07 0:00 UTC (permalink / raw)
To: kyrylo.tkachov, Ramana.Radhakrishnan, alan.lawrence; +Cc: gcc-patches
From: Charles Baylis <charles.baylis@linaro.org>
This patch series fixes up the error messages for single lane vector
load/stores, similarly to AArch64.
make check on arm-linux-gnueabihf/qemu completes with no new regressions.
Changes since the last version:
. removed the duplicate arm_neon_lane_bounds function
. resolved conflicts with other NEON work
. whitespace clean up
Charles Baylis (3):
[ARM] PR63870 Add qualifiers for NEON builtins
[ARM] PR63870 Mark lane indices of vldN/vstN with appropriate
qualifier
[ARM] PR63870 Enable test cases for ARM
gcc/config/arm/arm-builtins.c | 50 ++++++++++++++--------
gcc/config/arm/arm.c | 1 +
gcc/config/arm/arm.h | 3 ++
gcc/config/arm/neon.md | 49 +++++++++++----------
.../advsimd-intrinsics/vld2_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld2q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld3q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vld4q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst2q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst3q_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4_lane_u8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_f16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 5 +--
.../advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 5 +--
148 files changed, 350 insertions(+), 473 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins
2015-10-07 0:00 [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages charles.baylis
2015-10-07 0:00 ` [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier charles.baylis
@ 2015-10-07 0:00 ` charles.baylis
2015-10-12 10:58 ` Alan Lawrence
2015-10-07 0:01 ` [PATCH 3/3] [ARM] PR63870 Enable test cases charles.baylis
2015-10-09 14:04 ` [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages Charles Baylis
3 siblings, 1 reply; 9+ messages in thread
From: charles.baylis @ 2015-10-07 0:00 UTC (permalink / raw)
To: kyrylo.tkachov, Ramana.Radhakrishnan, alan.lawrence; +Cc: gcc-patches
From: Charles Baylis <charles.baylis@linaro.org>
gcc/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
PR target/63870
* config/arm/arm-builtins.c (enum arm_type_qualifiers): New enumerator
qualifier_struct_load_store_lane_index.
(builtin_arg): New enumerator NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX.
(arm_expand_neon_args): New parameter. Remove ellipsis. Handle NEON
argument qualifiers.
(arm_expand_neon_builtin): Handle new NEON argument qualifier.
* config/arm/arm.h (ENDIAN_LANE_N): New macro.
Change-Id: Iaa14d8736879fa53776319977eda2089f0a26647
---
gcc/config/arm/arm-builtins.c | 46 ++++++++++++++++++++++++++++---------------
gcc/config/arm/arm.c | 1 +
gcc/config/arm/arm.h | 3 +++
3 files changed, 34 insertions(+), 16 deletions(-)
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 0f5a1f1..a29f8d6 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -77,7 +77,9 @@ enum arm_type_qualifiers
/* Polynomial types. */
qualifier_poly = 0x100,
/* Lane indices - must be within range of previous argument = a vector. */
- qualifier_lane_index = 0x200
+ qualifier_lane_index = 0x200,
+ /* Lane indices for single lane structure loads and stores. */
+ qualifier_struct_load_store_lane_index = 0x400
};
/* The qualifier_internal allows generation of a unary builtin from
@@ -1973,6 +1975,7 @@ typedef enum {
NEON_ARG_COPY_TO_REG,
NEON_ARG_CONSTANT,
NEON_ARG_LANE_INDEX,
+ NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX,
NEON_ARG_MEMORY,
NEON_ARG_STOP
} builtin_arg;
@@ -2030,9 +2033,9 @@ neon_dereference_pointer (tree exp, tree type, machine_mode mem_mode,
/* Expand a Neon builtin. */
static rtx
arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
- int icode, int have_retval, tree exp, ...)
+ int icode, int have_retval, tree exp,
+ builtin_arg *args)
{
- va_list ap;
rtx pat;
tree arg[SIMD_MAX_BUILTIN_ARGS];
rtx op[SIMD_MAX_BUILTIN_ARGS];
@@ -2047,13 +2050,11 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
|| !(*insn_data[icode].operand[0].predicate) (target, tmode)))
target = gen_reg_rtx (tmode);
- va_start (ap, exp);
-
formals = TYPE_ARG_TYPES (TREE_TYPE (arm_builtin_decls[fcode]));
for (;;)
{
- builtin_arg thisarg = (builtin_arg) va_arg (ap, int);
+ builtin_arg thisarg = args[argc];
if (thisarg == NEON_ARG_STOP)
break;
@@ -2089,6 +2090,18 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
break;
+ case NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX:
+ gcc_assert (argc > 1);
+ if (CONST_INT_P (op[argc]))
+ {
+ neon_lane_bounds (op[argc], 0,
+ GET_MODE_NUNITS (map_mode), exp);
+ /* Keep to GCC-vector-extension lane indices in the RTL. */
+ op[argc] =
+ GEN_INT (ENDIAN_LANE_N (map_mode, INTVAL (op[argc])));
+ }
+ goto constant_arg;
+
case NEON_ARG_LANE_INDEX:
/* Previous argument must be a vector, which this indexes. */
gcc_assert (argc > 0);
@@ -2099,17 +2112,22 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
}
/* Fall through - if the lane index isn't a constant then
the next case will error. */
+
case NEON_ARG_CONSTANT:
+constant_arg:
if (!(*insn_data[icode].operand[opno].predicate)
(op[argc], mode[argc]))
- error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
- "expected %<const int%>", argc + 1);
+ {
+ error ("%Kargument %d must be a constant immediate",
+ exp, argc + 1);
+ return const0_rtx;
+ }
break;
+
case NEON_ARG_MEMORY:
/* Check if expand failed. */
if (op[argc] == const0_rtx)
{
- va_end (ap);
return 0;
}
gcc_assert (MEM_P (op[argc]));
@@ -2132,8 +2150,6 @@ arm_expand_neon_args (rtx target, machine_mode map_mode, int fcode,
}
}
- va_end (ap);
-
if (have_retval)
switch (argc)
{
@@ -2245,6 +2261,8 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
if (d->qualifiers[qualifiers_k] & qualifier_lane_index)
args[k] = NEON_ARG_LANE_INDEX;
+ else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
+ args[k] = NEON_ARG_STRUCT_LOAD_STORE_LANE_INDEX;
else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
args[k] = NEON_ARG_CONSTANT;
else if (d->qualifiers[qualifiers_k] & qualifier_maybe_immediate)
@@ -2270,11 +2288,7 @@ arm_expand_neon_builtin (int fcode, tree exp, rtx target)
the function is void, and a 1 if it is not. */
return arm_expand_neon_args
(target, d->mode, fcode, icode, !is_void, exp,
- args[1],
- args[2],
- args[3],
- args[4],
- NEON_ARG_STOP);
+ &args[1]);
}
/* Expand an expression EXP that calls a built-in function,
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 02f5dc3..448cde3 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -30117,4 +30117,5 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
*pri = tmp;
return;
}
+
#include "gt-arm.h"
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 87c9f90..27ac4dc 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -288,6 +288,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
#define TARGET_BPABI false
#endif
+#define ENDIAN_LANE_N(mode, n) \
+ (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
+
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-arch is ignored if -march or -mcpu are specified.
--with-cpu is ignored if -march or -mcpu are specified, and is overridden
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier
2015-10-07 0:00 [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages charles.baylis
@ 2015-10-07 0:00 ` charles.baylis
2015-10-12 10:50 ` Alan Lawrence
2015-10-07 0:00 ` [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins charles.baylis
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: charles.baylis @ 2015-10-07 0:00 UTC (permalink / raw)
To: kyrylo.tkachov, Ramana.Radhakrishnan, alan.lawrence; +Cc: gcc-patches
From: Charles Baylis <charles.baylis@linaro.org>
gcc/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
PR target/63870
* config/arm/arm-builtins.c: (arm_load1_qualifiers) Use
qualifier_struct_load_store_lane_index.
(arm_storestruct_lane_qualifiers) Likewise.
* config/arm/neon.md: (neon_vld1_lane<mode>) Reverse lane numbers for
big-endian.
(neon_vst1_lane<mode>) Likewise.
(neon_vld2_lane<mode>) Likewise.
(neon_vst2_lane<mode>) Likewise.
(neon_vld3_lane<mode>) Likewise.
(neon_vst3_lane<mode>) Likewise.
(neon_vld4_lane<mode>) Likewise.
(neon_vst4_lane<mode>) Likewise.
Change-Id: Ic39898d288701bc5b712490265be688f5620c4e2
---
gcc/config/arm/arm-builtins.c | 4 ++--
gcc/config/arm/neon.md | 49 +++++++++++++++++++++++--------------------
2 files changed, 28 insertions(+), 25 deletions(-)
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index a29f8d6..cbe96e4 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -162,7 +162,7 @@ arm_load1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum arm_type_qualifiers
arm_load1_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_const_pointer_map_mode,
- qualifier_none, qualifier_immediate };
+ qualifier_none, qualifier_struct_load_store_lane_index };
#define LOAD1LANE_QUALIFIERS (arm_load1_lane_qualifiers)
/* The first argument (return type) of a store should be void type,
@@ -181,7 +181,7 @@ arm_store1_qualifiers[SIMD_MAX_BUILTIN_ARGS]
static enum arm_type_qualifiers
arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_void, qualifier_pointer_map_mode,
- qualifier_none, qualifier_immediate };
+ qualifier_none, qualifier_struct_load_store_lane_index };
#define STORE1LANE_QUALIFIERS (arm_storestruct_lane_qualifiers)
#define v8qi_UP V8QImode
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 2667866..251afdc 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4261,8 +4261,9 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
+ operands[3] = GEN_INT (lane);
if (lane < 0 || lane >= max)
error ("lane out of range");
if (max == 1)
@@ -4281,8 +4282,9 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
+ operands[3] = GEN_INT (lane);
int regno = REGNO (operands[0]);
if (lane < 0 || lane >= max)
error ("lane out of range");
@@ -4367,8 +4369,9 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
+ operands[2] = GEN_INT (lane);
if (lane < 0 || lane >= max)
error ("lane out of range");
if (max == 1)
@@ -4387,7 +4390,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST1_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
if (lane < 0 || lane >= max)
@@ -4396,8 +4399,8 @@ if (BYTES_BIG_ENDIAN)
{
lane -= max / 2;
regno += 2;
- operands[2] = GEN_INT (lane);
}
+ operands[2] = GEN_INT (lane);
operands[1] = gen_rtx_REG (<V_HALF>mode, regno);
if (max == 2)
return "vst1.<V_sz_elem>\t{%P1}, %A0";
@@ -4457,7 +4460,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[4];
@@ -4466,7 +4469,7 @@ if (BYTES_BIG_ENDIAN)
ops[0] = gen_rtx_REG (DImode, regno);
ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = operands[1];
- ops[3] = operands[3];
+ ops[3] = GEN_INT (lane);
output_asm_insn ("vld2.<V_sz_elem>\t{%P0[%c3], %P1[%c3]}, %A2", ops);
return "";
}
@@ -4482,7 +4485,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[4];
@@ -4572,7 +4575,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[4];
@@ -4581,7 +4584,7 @@ if (BYTES_BIG_ENDIAN)
ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 2);
- ops[3] = operands[2];
+ ops[3] = GEN_INT (lane);
output_asm_insn ("vst2.<V_sz_elem>\t{%P1[%c3], %P2[%c3]}, %A0", ops);
return "";
}
@@ -4597,7 +4600,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST2_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[4];
@@ -4716,7 +4719,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[5];
@@ -4726,7 +4729,7 @@ if (BYTES_BIG_ENDIAN)
ops[1] = gen_rtx_REG (DImode, regno + 2);
ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = operands[1];
- ops[4] = operands[3];
+ ops[4] = GEN_INT (lane);
output_asm_insn ("vld3.<V_sz_elem>\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3",
ops);
return "";
@@ -4743,7 +4746,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[5];
@@ -4888,7 +4891,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[5];
@@ -4898,7 +4901,7 @@ if (BYTES_BIG_ENDIAN)
ops[1] = gen_rtx_REG (DImode, regno);
ops[2] = gen_rtx_REG (DImode, regno + 2);
ops[3] = gen_rtx_REG (DImode, regno + 4);
- ops[4] = operands[2];
+ ops[4] = GEN_INT (lane);
output_asm_insn ("vst3.<V_sz_elem>\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0",
ops);
return "";
@@ -4915,7 +4918,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST3_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[5];
@@ -5038,7 +5041,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[6];
@@ -5049,7 +5052,7 @@ if (BYTES_BIG_ENDIAN)
ops[2] = gen_rtx_REG (DImode, regno + 4);
ops[3] = gen_rtx_REG (DImode, regno + 6);
ops[4] = operands[1];
- ops[5] = operands[3];
+ ops[5] = GEN_INT (lane);
output_asm_insn ("vld4.<V_sz_elem>\t{%P0[%c5], %P1[%c5], %P2[%c5], %P3[%c5]}, %A4",
ops);
return "";
@@ -5066,7 +5069,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VLD4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[3]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[0]);
rtx ops[6];
@@ -5218,7 +5221,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[6];
@@ -5229,7 +5232,7 @@ if (BYTES_BIG_ENDIAN)
ops[2] = gen_rtx_REG (DImode, regno + 2);
ops[3] = gen_rtx_REG (DImode, regno + 4);
ops[4] = gen_rtx_REG (DImode, regno + 6);
- ops[5] = operands[2];
+ ops[5] = GEN_INT (lane);
output_asm_insn ("vst4.<V_sz_elem>\t{%P1[%c5], %P2[%c5], %P3[%c5], %P4[%c5]}, %A0",
ops);
return "";
@@ -5246,7 +5249,7 @@ if (BYTES_BIG_ENDIAN)
UNSPEC_VST4_LANE))]
"TARGET_NEON"
{
- HOST_WIDE_INT lane = INTVAL (operands[2]);
+ HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[2]));
HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
int regno = REGNO (operands[1]);
rtx ops[6];
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] [ARM] PR63870 Enable test cases
2015-10-07 0:00 [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages charles.baylis
2015-10-07 0:00 ` [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier charles.baylis
2015-10-07 0:00 ` [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins charles.baylis
@ 2015-10-07 0:01 ` charles.baylis
2015-10-09 14:04 ` [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages Charles Baylis
3 siblings, 0 replies; 9+ messages in thread
From: charles.baylis @ 2015-10-07 0:01 UTC (permalink / raw)
To: kyrylo.tkachov, Ramana.Radhakrishnan, alan.lawrence; +Cc: gcc-patches
From: Charles Baylis <charles.baylis@linaro.org>
gcc/testsuite/ChangeLog:
<DATE> Charles Baylis <charles.baylis@linaro.org>
PR target/63870
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c (f_vld2_lane_f16): Remove xfails for arm targets.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c (f_vld2_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c (f_vld2_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c (f_vld2_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c (f_vld2_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c (f_vld2_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c (f_vld2_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c (f_vld2_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c (f_vld2_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c (f_vld2_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c (f_vld2_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c (f_vld2_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c (f_vld2q_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c (f_vld2q_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c (f_vld2q_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c (f_vld2q_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c (f_vld2q_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c (f_vld2q_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c (f_vld2q_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c (f_vld2q_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c (f_vld2q_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c (f_vld2q_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c (f_vld2q_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c (f_vld2q_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c (f_vld3_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c (f_vld3_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c (f_vld3_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c (f_vld3_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c (f_vld3_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c (f_vld3_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c (f_vld3_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c (f_vld3_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c (f_vld3_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c (f_vld3_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c (f_vld3_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c (f_vld3_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c (f_vld3q_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c (f_vld3q_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c (f_vld3q_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c (f_vld3q_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c (f_vld3q_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c (f_vld3q_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c (f_vld3q_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c (f_vld3q_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c (f_vld3q_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c (f_vld3q_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c (f_vld3q_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c (f_vld3q_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c (f_vld4_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c (f_vld4_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c (f_vld4_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c (f_vld4_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c (f_vld4_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c (f_vld4_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c (f_vld4_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c (f_vld4_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c (f_vld4_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c (f_vld4_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c (f_vld4_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c (f_vld4_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c (f_vld4q_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c (f_vld4q_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c (f_vld4q_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c (f_vld4q_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c (f_vld4q_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c (f_vld4q_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c (f_vld4q_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c (f_vld4q_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c (f_vld4q_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c (f_vld4q_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c (f_vld4q_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c (f_vld4q_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c (f_vst2_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c (f_vst2_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c (f_vst2_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c (f_vst2_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c (f_vst2_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c (f_vst2_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c (f_vst2_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c (f_vst2_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c (f_vst2_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c (f_vst2_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c (f_vst2_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c (f_vst2_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c (f_vst2q_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c (f_vst2q_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c (f_vst2q_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c (f_vst2q_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c (f_vst2q_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c (f_vst2q_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c (f_vst2q_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c (f_vst2q_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c (f_vst2q_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c (f_vst2q_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c (f_vst2q_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c (f_vst2q_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c (f_vst3_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c (f_vst3_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c (f_vst3_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c (f_vst3_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c (f_vst3_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c (f_vst3_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c (f_vst3_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c (f_vst3_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c (f_vst3_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c (f_vst3_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c (f_vst3_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c (f_vst3_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c (f_vst3q_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c (f_vst3q_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c (f_vst3q_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c (f_vst3q_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c (f_vst3q_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c (f_vst3q_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c (f_vst3q_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c (f_vst3q_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c (f_vst3q_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c (f_vst3q_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c (f_vst3q_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c (f_vst3q_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c (f_vst4_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c (f_vst4_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c (f_vst4_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c (f_vst4_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c (f_vst4_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c (f_vst4_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c (f_vst4_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c (f_vst4_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c (f_vst4_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c (f_vst4_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c (f_vst4_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c (f_vst4_lane_u8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c (f_vst4q_lane_f16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c (f_vst4q_lane_f32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c (f_vst4q_lane_f64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c (f_vst4q_lane_p8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c (f_vst4q_lane_s16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c (f_vst4q_lane_s32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c (f_vst4q_lane_s64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c (f_vst4q_lane_s8): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c (f_vst4q_lane_u16): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c (f_vst4q_lane_u32): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c (f_vst4q_lane_u64): Ditto.
* gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c (f_vst4q_lane_u8): Ditto.
Change-Id: Ib630d99a9bb42dc5a46dced17cd6e79a9931c102
---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 5 ++---
.../gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 5 ++---
144 files changed, 288 insertions(+), 432 deletions(-)
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
index 2174d6e..46fa753 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float16x4x2_t
f_vld2_lane_f16 (float16_t * p, float16x4x2_t v)
{
float16x4x2_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_f16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_f16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
index 04be713..d1895f0 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x2x2_t
f_vld2_lane_f32 (float32_t * p, float32x2x2_t v)
{
float32x2x2_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2_lane_f32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2_lane_f32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
index a03d165..19dd5f4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1x2_t
f_vld2_lane_f64 (float64_t * p, float64x1x2_t v)
{
float64x1x2_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld2_lane_f64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld2_lane_f64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
index 3a7aeb3..df3ce8c 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_p8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
poly8x8x2_t
f_vld2_lane_p8 (poly8_t * p, poly8x8x2_t v)
{
poly8x8x2_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2_lane_p8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2_lane_p8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
index 0b6314c..ad56c8b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x4x2_t
f_vld2_lane_s16 (int16_t * p, int16x4x2_t v)
{
int16x4x2_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_s16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_s16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
index 3314780..8b7455d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x2x2_t
f_vld2_lane_s32 (int32_t * p, int32x2x2_t v)
{
int32x2x2_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2_lane_s32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2_lane_s32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
index 351ba40..de0a2c1 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x1x2_t
f_vld2_lane_s64 (int64_t * p, int64x1x2_t v)
{
int64x1x2_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld2_lane_s64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld2_lane_s64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
index 1db7462..ad414a5 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_s8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int8x8x2_t
f_vld2_lane_s8 (int8_t * p, int8x8x2_t v)
{
int8x8x2_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2_lane_s8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2_lane_s8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
index b65ae56..a80b54d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x4x2_t
f_vld2_lane_u16 (uint16_t * p, uint16x4x2_t v)
{
uint16x4x2_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_u16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2_lane_u16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
index 4990ed0..76db072 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x2x2_t
f_vld2_lane_u32 (uint32_t * p, uint32x2x2_t v)
{
uint32x2x2_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2_lane_u32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2_lane_u32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
index 09ff01c..3539a3f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x1x2_t
f_vld2_lane_u64 (uint64_t * p, uint64x1x2_t v)
{
uint64x1x2_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld2_lane_u64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld2_lane_u64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
index d0c40a1..20e8465 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_u8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint8x8x2_t
f_vld2_lane_u8 (uint8_t * p, uint8x8x2_t v)
{
uint8x8x2_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2_lane_u8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2_lane_u8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
index 83ae82c..f921d32 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float16x8x2_t
f_vld2q_lane_f16 (float16_t * p, float16x8x2_t v)
{
float16x8x2_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2q_lane_f16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2q_lane_f16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
index 84853f3..0c3c947 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x4x2_t
f_vld2q_lane_f32 (float32_t * p, float32x4x2_t v)
{
float32x4x2_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2q_lane_f32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2q_lane_f32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
index 4f106bc..5d2eb2d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2x2_t
f_vld2q_lane_f64 (float64_t * p, float64x2x2_t v)
{
float64x2x2_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2q_lane_f64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2q_lane_f64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
index 04eab14..b48aca4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_p8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
poly8x16x2_t
f_vld2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
{
poly8x16x2_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld2q_lane_p8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld2q_lane_p8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
index 048517d..c3062c9 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x8x2_t
f_vld2q_lane_s16 (int16_t * p, int16x8x2_t v)
{
int16x8x2_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2q_lane_s16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2q_lane_s16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
index 620bafb..bfb4f0a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x4x2_t
f_vld2q_lane_s32 (int32_t * p, int32x4x2_t v)
{
int32x4x2_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2q_lane_s32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2q_lane_s32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
index e182c6d..84d453a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x2x2_t
f_vld2q_lane_s64 (int64_t * p, int64x2x2_t v)
{
int64x2x2_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2q_lane_s64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2q_lane_s64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
index a58538e..ec37d1b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_s8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int8x16x2_t
f_vld2q_lane_s8 (int8_t * p, int8x16x2_t v)
{
int8x16x2_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld2q_lane_s8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld2q_lane_s8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
index cf6e9a1..3588131 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x8x2_t
f_vld2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
{
uint16x8x2_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2q_lane_u16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld2q_lane_u16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
index 6945cf0..7f27214 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x4x2_t
f_vld2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
{
uint32x4x2_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2q_lane_u32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld2q_lane_u32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
index 84f0959..828f7d3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x2x2_t
f_vld2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
{
uint64x2x2_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2q_lane_u64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld2q_lane_u64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
index 82ecfe2..08fe749 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_u8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint8x16x2_t
f_vld2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
{
uint8x16x2_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld2q_lane_u8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld2q_lane_u8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
index 21b7861..d068d79 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float16x4x3_t
f_vld3_lane_f16 (float16_t * p, float16x4x3_t v)
{
float16x4x3_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3_lane_f16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3_lane_f16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
index 4db8b7c..6d13e2b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x2x3_t
f_vld3_lane_f32 (float32_t * p, float32x2x3_t v)
{
float32x2x3_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3_lane_f32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3_lane_f32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
index 7465976..63d5551 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1x3_t
f_vld3_lane_f64 (float64_t * p, float64x1x3_t v)
{
float64x1x3_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld3_lane_f64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld3_lane_f64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
index 712c67c..a6a9666 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_p8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
poly8x8x3_t
f_vld3_lane_p8 (poly8_t * p, poly8x8x3_t v)
{
poly8x8x3_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3_lane_p8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3_lane_p8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
index 22e11d3..69fd90d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x4x3_t
f_vld3_lane_s16 (int16_t * p, int16x4x3_t v)
{
int16x4x3_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3_lane_s16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3_lane_s16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
index ed4f50b..01816e8 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x2x3_t
f_vld3_lane_s32 (int32_t * p, int32x2x3_t v)
{
int32x2x3_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3_lane_s32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3_lane_s32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
index ae7b35e..f2a6dbd 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x1x3_t
f_vld3_lane_s64 (int64_t * p, int64x1x3_t v)
{
int64x1x3_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld3_lane_s64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld3_lane_s64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
index 320ef37..5d5f845 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_s8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int8x8x3_t
f_vld3_lane_s8 (int8_t * p, int8x8x3_t v)
{
int8x8x3_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3_lane_s8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3_lane_s8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
index a00253a..8be04ed 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x4x3_t
f_vld3_lane_u16 (uint16_t * p, uint16x4x3_t v)
{
uint16x4x3_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3_lane_u16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3_lane_u16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
index d53ead3..bf890d3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x2x3_t
f_vld3_lane_u32 (uint32_t * p, uint32x2x3_t v)
{
uint32x2x3_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3_lane_u32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3_lane_u32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
index e9b4427..926718e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x1x3_t
f_vld3_lane_u64 (uint64_t * p, uint64x1x3_t v)
{
uint64x1x3_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld3_lane_u64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld3_lane_u64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
index 3afff9f..d129bba 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_u8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint8x8x3_t
f_vld3_lane_u8 (uint8_t * p, uint8x8x3_t v)
{
uint8x8x3_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3_lane_u8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3_lane_u8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
index 95ec391..ed4d7d5 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float16x8x3_t
f_vld3q_lane_f16 (float16_t * p, float16x8x3_t v)
{
float16x8x3_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3q_lane_f16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3q_lane_f16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
index e38799c..0c276c4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x4x3_t
f_vld3q_lane_f32 (float32_t * p, float32x4x3_t v)
{
float32x4x3_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3q_lane_f32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3q_lane_f32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
index c84c6c8..2c666c6 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2x3_t
f_vld3q_lane_f64 (float64_t * p, float64x2x3_t v)
{
float64x2x3_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3q_lane_f64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3q_lane_f64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
index 1dea0d4..2041472 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_p8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
poly8x16x3_t
f_vld3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
{
poly8x16x3_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld3q_lane_p8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld3q_lane_p8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
index 03f59f0..7b7b2b6 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x8x3_t
f_vld3q_lane_s16 (int16_t * p, int16x8x3_t v)
{
int16x8x3_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3q_lane_s16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3q_lane_s16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
index 57315ba..c8db256 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x4x3_t
f_vld3q_lane_s32 (int32_t * p, int32x4x3_t v)
{
int32x4x3_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3q_lane_s32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3q_lane_s32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
index fff4f80..e350971 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x2x3_t
f_vld3q_lane_s64 (int64_t * p, int64x2x3_t v)
{
int64x2x3_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3q_lane_s64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3q_lane_s64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
index 9c340e0..1b1c682 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_s8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int8x16x3_t
f_vld3q_lane_s8 (int8_t * p, int8x16x3_t v)
{
int8x16x3_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld3q_lane_s8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld3q_lane_s8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
index 3dfaacb..adbc42f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x8x3_t
f_vld3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
{
uint16x8x3_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3q_lane_u16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld3q_lane_u16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
index 9d4ed46..c79388a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x4x3_t
f_vld3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
{
uint32x4x3_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3q_lane_u32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld3q_lane_u32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
index ca188a8..7513140 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x2x3_t
f_vld3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
{
uint64x2x3_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3q_lane_u64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld3q_lane_u64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
index 5ca835e..5fec76e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_u8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint8x16x3_t
f_vld3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
{
uint8x16x3_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld3q_lane_u8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld3q_lane_u8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
index bd7ecf0..b5d5adf 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float16x4x4_t
f_vld4_lane_f16 (float16_t * p, float16x4x4_t v)
{
float16x4x4_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4_lane_f16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4_lane_f16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
index f956ee6..183036f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x2x4_t
f_vld4_lane_f32 (float32_t * p, float32x2x4_t v)
{
float32x2x4_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4_lane_f32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4_lane_f32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
index 52763b4..655c27f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x1x4_t
f_vld4_lane_f64 (float64_t * p, float64x1x4_t v)
{
float64x1x4_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld4_lane_f64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld4_lane_f64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
index 8f9d3ee..7bc5140 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_p8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
poly8x8x4_t
f_vld4_lane_p8 (poly8_t * p, poly8x8x4_t v)
{
poly8x8x4_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4_lane_p8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4_lane_p8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
index 53f51a0..5881a89 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x4x4_t
f_vld4_lane_s16 (int16_t * p, int16x4x4_t v)
{
int16x4x4_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4_lane_s16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4_lane_s16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
index 7b8396e..02282d9 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x2x4_t
f_vld4_lane_s32 (int32_t * p, int32x2x4_t v)
{
int32x2x4_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4_lane_s32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4_lane_s32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
index 8cc138e..162b5c4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x1x4_t
f_vld4_lane_s64 (int64_t * p, int64x1x4_t v)
{
int64x1x4_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld4_lane_s64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld4_lane_s64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
index 1c3bcf3..4949410 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_s8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int8x8x4_t
f_vld4_lane_s8 (int8_t * p, int8x8x4_t v)
{
int8x8x4_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4_lane_s8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4_lane_s8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
index 2ac73af..16d54e9 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x4x4_t
f_vld4_lane_u16 (uint16_t * p, uint16x4x4_t v)
{
uint16x4x4_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4_lane_u16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4_lane_u16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
index e37e038..c65bd30 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x2x4_t
f_vld4_lane_u32 (uint32_t * p, uint32x2x4_t v)
{
uint32x2x4_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4_lane_u32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4_lane_u32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
index 96f0bb8..e8f2884 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x1x4_t
f_vld4_lane_u64 (uint64_t * p, uint64x1x4_t v)
{
uint64x1x4_t res;
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld4_lane_u64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
res = vld4_lane_u64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
index e8de335..cb7f487 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_u8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint8x8x4_t
f_vld4_lane_u8 (uint8_t * p, uint8x8x4_t v)
{
uint8x8x4_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4_lane_u8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4_lane_u8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
index c27559f..e9947d4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float16x8x4_t
f_vld4q_lane_f16 (float16_t * p, float16x8x4_t v)
{
float16x8x4_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4q_lane_f16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4q_lane_f16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
index 93d5730..8d7d03e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
float32x4x4_t
f_vld4q_lane_f32 (float32_t * p, float32x4x4_t v)
{
float32x4x4_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4q_lane_f32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4q_lane_f32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
index 062e0eb..d0ce4e5 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
float64x2x4_t
f_vld4q_lane_f64 (float64_t * p, float64x2x4_t v)
{
float64x2x4_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4q_lane_f64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4q_lane_f64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
index 32ae95b..bb1cb31 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_p8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
poly8x16x4_t
f_vld4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
{
poly8x16x4_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld4q_lane_p8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld4q_lane_p8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
index f4a7225..d96fe0e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int16x8x4_t
f_vld4q_lane_s16 (int16_t * p, int16x8x4_t v)
{
int16x8x4_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4q_lane_s16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4q_lane_s16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
index 45dd197..446ff43 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
int32x4x4_t
f_vld4q_lane_s32 (int32_t * p, int32x4x4_t v)
{
int32x4x4_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4q_lane_s32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4q_lane_s32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
index 5a01d05..df02f39 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int64x2x4_t
f_vld4q_lane_s64 (int64_t * p, int64x2x4_t v)
{
int64x2x4_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4q_lane_s64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4q_lane_s64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
index db66917..d7573c1 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_s8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
int8x16x4_t
f_vld4q_lane_s8 (int8_t * p, int8x16x4_t v)
{
int8x16x4_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld4q_lane_s8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld4q_lane_s8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
index 5a27639..05be38b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u16_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint16x8x4_t
f_vld4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
{
uint16x8x4_t res;
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4q_lane_u16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
res = vld4q_lane_u16 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
index 5d8a570..572c6d0 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u32_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
uint32x4x4_t
f_vld4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
{
uint32x4x4_t res;
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4q_lane_u32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
res = vld4q_lane_u32 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
index 92b4c51..a6828df 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u64_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint64x2x4_t
f_vld4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
{
uint64x2x4_t res;
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4q_lane_u64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
res = vld4q_lane_u64 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
index 293416d..8b5eb43 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_u8_indices_1.c
@@ -2,16 +2,15 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
uint8x16x4_t
f_vld4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
{
uint8x16x4_t res;
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld4q_lane_u8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
res = vld4q_lane_u8 (p, v, -1);
return res;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
index dbf5241..93d6e5c 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_f16 (float16_t * p, float16x4x2_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2_lane_f16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2_lane_f16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
index 1a39625..a0ea45b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_f32 (float32_t * p, float32x2x2_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2_lane_f32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2_lane_f32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
index 3674715..2eca26f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2_lane_f64 (float64_t * p, float64x1x2_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst2_lane_f64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst2_lane_f64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
index 770fe9d..3692d7d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_p8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_p8 (poly8_t * p, poly8x8x2_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2_lane_p8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2_lane_p8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
index ac89d03..94ac769 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_s16 (int16_t * p, int16x4x2_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2_lane_s16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2_lane_s16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
index 4bbceb6..3ef5687 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_s32 (int32_t * p, int32x2x2_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2_lane_s32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2_lane_s32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
index da60b9b..1e3c202 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2_lane_s64 (int64_t * p, int64x1x2_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst2_lane_s64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst2_lane_s64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
index b5bf3d6..a96b1b4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_s8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_s8 (int8_t * p, int8x8x2_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2_lane_s8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2_lane_s8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
index bfdc5c0..970be4a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_u16 (uint16_t * p, uint16x4x2_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2_lane_u16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2_lane_u16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
index e32c6ff..4c8e2f1 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_u32 (uint32_t * p, uint32x2x2_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2_lane_u32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2_lane_u32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
index 03546bd..dfb0de2 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2_lane_u64 (uint64_t * p, uint64x1x2_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst2_lane_u64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst2_lane_u64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
index 74da14c..4877ea2 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_u8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2_lane_u8 (uint8_t * p, uint8x8x2_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2_lane_u8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2_lane_u8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
index e3c0296..729314e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_f16 (float16_t * p, float16x8x2_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2q_lane_f16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2q_lane_f16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
index 246c60c..75f7dd6 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_f32 (float32_t * p, float32x4x2_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2q_lane_f32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2q_lane_f32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
index a102921..9a23056 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_f64 (float64_t * p, float64x2x2_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2q_lane_f64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2q_lane_f64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
index 8966b53..c3f2433 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_p8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_p8 (poly8_t * p, poly8x16x2_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst2q_lane_p8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst2q_lane_p8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
index 19d22a1..82ae1e4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_s16 (int16_t * p, int16x8x2_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2q_lane_s16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2q_lane_s16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
index bbb772c..27208bd 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_s32 (int32_t * p, int32x4x2_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2q_lane_s32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2q_lane_s32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
index 6efc681..a66d55b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_s64 (int64_t * p, int64x2x2_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2q_lane_s64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2q_lane_s64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
index 7c0eb49..7a3338b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_s8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_s8 (int8_t * p, int8x16x2_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst2q_lane_s8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst2q_lane_s8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
index b079a34..999ee70 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_u16 (uint16_t * p, uint16x8x2_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2q_lane_u16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst2q_lane_u16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
index b919e2b..fd4422d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst2q_lane_u32 (uint32_t * p, uint32x4x2_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2q_lane_u32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst2q_lane_u32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
index 7d31d65..78863b5 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_u64 (uint64_t * p, uint64x2x2_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2q_lane_u64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst2q_lane_u64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
index 9c35ce9..e7463e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_u8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst2q_lane_u8 (uint8_t * p, uint8x16x2_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst2q_lane_u8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst2q_lane_u8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
index 406dfd4..1f262a1 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_f16 (float16_t * p, float16x4x3_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3_lane_f16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3_lane_f16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
index 1d7a57e..0cec880 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_f32 (float32_t * p, float32x2x3_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3_lane_f32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3_lane_f32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
index 5e9b9ea..d63aa1f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3_lane_f64 (float64_t * p, float64x1x3_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst3_lane_f64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst3_lane_f64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
index 7599a19..0122b75 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_p8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_p8 (poly8_t * p, poly8x8x3_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3_lane_p8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3_lane_p8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
index f8b856d..2c57d2b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_s16 (int16_t * p, int16x4x3_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3_lane_s16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3_lane_s16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
index 7fbf2e89..c0b3a5b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_s32 (int32_t * p, int32x2x3_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3_lane_s32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3_lane_s32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
index 801dcc0..2c2d043 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3_lane_s64 (int64_t * p, int64x1x3_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst3_lane_s64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst3_lane_s64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
index 1623326..b93d69a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_s8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_s8 (int8_t * p, int8x8x3_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3_lane_s8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3_lane_s8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
index 7304da6..ce6025d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_u16 (uint16_t * p, uint16x4x3_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3_lane_u16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3_lane_u16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
index 4c1c4b7..5696034 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_u32 (uint32_t * p, uint32x2x3_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3_lane_u32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3_lane_u32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
index adc8fb2..9a36915 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3_lane_u64 (uint64_t * p, uint64x1x3_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst3_lane_u64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst3_lane_u64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
index 8a55b55..9004f3d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_u8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3_lane_u8 (uint8_t * p, uint8x8x3_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3_lane_u8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3_lane_u8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
index 4e8b24c..6c24a5e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3q_lane_f16 (float16_t * p, float16x8x3_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3q_lane_f16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3q_lane_f16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
index 8a081fe..d1ffc04 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3q_lane_f32 (float32_t * p, float32x4x3_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3q_lane_f32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3q_lane_f32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
index 2d867f2..e165f2a 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3q_lane_f64 (float64_t * p, float64x2x3_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3q_lane_f64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3q_lane_f64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
index 295f6b6..7fb3c96 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_p8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3q_lane_p8 (poly8_t * p, poly8x16x3_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst3q_lane_p8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst3q_lane_p8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
index 160c90c..de8ae54 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3q_lane_s16 (int16_t * p, int16x8x3_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3q_lane_s16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3q_lane_s16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
index 0324f3c..6502bcf 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3q_lane_s32 (int32_t * p, int32x4x3_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3q_lane_s32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3q_lane_s32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
index b565126..c6d8236 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3q_lane_s64 (int64_t * p, int64x2x3_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3q_lane_s64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3q_lane_s64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
index 5e35bb9..2b48619 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_s8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3q_lane_s8 (int8_t * p, int8x16x3_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst3q_lane_s8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst3q_lane_s8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
index 9eaae3b..6d68051 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3q_lane_u16 (uint16_t * p, uint16x8x3_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3q_lane_u16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst3q_lane_u16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
index 62339fc..78b28a0 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst3q_lane_u32 (uint32_t * p, uint32x4x3_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3q_lane_u32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst3q_lane_u32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
index 39044cc..fe4f52e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3q_lane_u64 (uint64_t * p, uint64x2x3_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3q_lane_u64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst3q_lane_u64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
index bf48dbb..74e49db 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_u8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst3q_lane_u8 (uint8_t * p, uint8x16x3_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst3q_lane_u8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst3q_lane_u8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
index 0fe6511..6ada55e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_f16 (float16_t * p, float16x4x4_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4_lane_f16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4_lane_f16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
index 7f04512..00a8a50 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_f32 (float32_t * p, float32x2x4_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4_lane_f32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4_lane_f32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
index ddee219..7cb45ca 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4_lane_f64 (float64_t * p, float64x1x4_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst4_lane_f64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst4_lane_f64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
index 14491ac..8b7fef3 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_p8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_p8 (poly8_t * p, poly8x8x4_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4_lane_p8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4_lane_p8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
index 8434a9b..e62691c 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_s16 (int16_t * p, int16x4x4_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4_lane_s16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4_lane_s16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
index 53a4a46..ced39ca 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_s32 (int32_t * p, int32x2x4_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4_lane_s32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4_lane_s32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
index 051c8eb..fe77b4d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4_lane_s64 (int64_t * p, int64x1x4_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst4_lane_s64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst4_lane_s64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
index 33967ac..b287a59 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_s8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_s8 (int8_t * p, int8x8x4_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4_lane_s8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4_lane_s8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
index 8e358dd..2144dc4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_u16 (uint16_t * p, uint16x4x4_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4_lane_u16 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4_lane_u16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
index 4f7899f..576036c 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_u32 (uint32_t * p, uint32x2x4_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4_lane_u32 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4_lane_u32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
index 9fb06d1..b6040b7 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4_lane_u64 (uint64_t * p, uint64x1x4_t v)
{
- /* { dg-error "lane 1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst4_lane_u64 (p, v, 1);
- /* { dg-error "lane -1 out of range 0 - 0" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 0" "" { target *-*-* } 0 } */
vst4_lane_u64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
index 3a18322..4ed80cf 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_u8_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4_lane_u8 (uint8_t * p, uint8x8x4_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4_lane_u8 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4_lane_u8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
index 9a5f09a..7327c03 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4q_lane_f16 (float16_t * p, float16x8x4_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4q_lane_f16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4q_lane_f16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
index 72f7d02..ca01289 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4q_lane_f32 (float32_t * p, float32x4x4_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4q_lane_f32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4q_lane_f32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
index c5f721f..e2b7fb8 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4q_lane_f64 (float64_t * p, float64x2x4_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4q_lane_f64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4q_lane_f64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
index 3e57c95..fb8f4ca 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_p8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4q_lane_p8 (poly8_t * p, poly8x16x4_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst4q_lane_p8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst4q_lane_p8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
index 5fcbc7f..4855b73 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4q_lane_s16 (int16_t * p, int16x8x4_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4q_lane_s16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4q_lane_s16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
index c039c87..29a8a69 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4q_lane_s32 (int32_t * p, int32x4x4_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4q_lane_s32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4q_lane_s32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
index 824a7e7..297cae8 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4q_lane_s64 (int64_t * p, int64x2x4_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4q_lane_s64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4q_lane_s64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
index 0850c67..10c70cc 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_s8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4q_lane_s8 (int8_t * p, int8x16x4_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst4q_lane_s8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst4q_lane_s8 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
index 6950a22..d0063ea 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u16_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4q_lane_u16 (uint16_t * p, uint16x8x4_t v)
{
- /* { dg-error "lane 8 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4q_lane_u16 (p, v, 8);
- /* { dg-error "lane -1 out of range 0 - 7" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
vst4q_lane_u16 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
index 3c9a171..89b4c52 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u32_indices_1.c
@@ -2,14 +2,13 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
void
f_vst4q_lane_u32 (uint32_t * p, uint32x4x4_t v)
{
- /* { dg-error "lane 4 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4q_lane_u32 (p, v, 4);
- /* { dg-error "lane -1 out of range 0 - 3" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
vst4q_lane_u32 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
index 8543e58..ba697c4 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u64_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4q_lane_u64 (uint64_t * p, uint64x2x4_t v)
{
- /* { dg-error "lane 2 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4q_lane_u64 (p, v, 2);
- /* { dg-error "lane -1 out of range 0 - 1" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
vst4q_lane_u64 (p, v, -1);
return;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
index ade4801..61f8ce2 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_u8_indices_1.c
@@ -2,15 +2,14 @@
/* { dg-do compile } */
/* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */
-/* { dg-excess-errors "" { xfail arm*-*-* } } */
/* { dg-skip-if "" { arm*-*-* } } */
void
f_vst4q_lane_u8 (uint8_t * p, uint8x16x4_t v)
{
- /* { dg-error "lane 16 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane 16 out of range 0 - 15" "" { target *-*-* } 0 } */
vst4q_lane_u8 (p, v, 16);
- /* { dg-error "lane -1 out of range 0 - 15" "" { xfail arm*-*-* } 0 } */
+ /* { dg-error "lane -1 out of range 0 - 15" "" { target *-*-* } 0 } */
vst4q_lane_u8 (p, v, -1);
return;
}
--
1.9.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages
2015-10-07 0:00 [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages charles.baylis
` (2 preceding siblings ...)
2015-10-07 0:01 ` [PATCH 3/3] [ARM] PR63870 Enable test cases charles.baylis
@ 2015-10-09 14:04 ` Charles Baylis
3 siblings, 0 replies; 9+ messages in thread
From: Charles Baylis @ 2015-10-09 14:04 UTC (permalink / raw)
To: Kyrylo Tkachov, Ramana Radhakrishnan, Alan Lawrence; +Cc: GCC Patches
On 7 October 2015 at 00:59, <charles.baylis@linaro.org> wrote:
> From: Charles Baylis <charles.baylis@linaro.org>
>
> This patch series fixes up the error messages for single lane vector
> load/stores, similarly to AArch64.
>
> make check on arm-linux-gnueabihf/qemu completes with no new regressions.
>
> Changes since the last version:
> . removed the duplicate arm_neon_lane_bounds function
> . resolved conflicts with other NEON work
> . whitespace clean up
>
A bit more info is required here.
Original patch submission was at:
https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00142.html
> Charles Baylis (3):
> [ARM] PR63870 Add qualifiers for NEON builtins
This adds the qualifier_struct_load_store_lane_index qualifier, ported
from my AArch64 changes. This causes the lane bounds check to be
performed and, on big-endian targets, reverses the lane number used in
the RTL (in common with other NEON patterns). This isn't strictly
required for correctness, since the vectorizer never generates these
patterns, but the consistency seems like a good idea.
> [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate
> qualifier
This marks the builtins with qualifier_struct_load_store_lane_index.
The patterns are also updated to un-reverse the lane order at assembly
time.
> [ARM] PR63870 Enable test cases for ARM
Removes the xfails from the test cases.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier
2015-10-07 0:00 ` [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier charles.baylis
@ 2015-10-12 10:50 ` Alan Lawrence
0 siblings, 0 replies; 9+ messages in thread
From: Alan Lawrence @ 2015-10-12 10:50 UTC (permalink / raw)
To: charles.baylis, Kyrylo Tkachov, Ramana Radhakrishnan; +Cc: gcc-patches
On 07/10/15 00:59, charles.baylis@linaro.org wrote:
> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
> index 2667866..251afdc 100644
> --- a/gcc/config/arm/neon.md
> +++ b/gcc/config/arm/neon.md
> @@ -4261,8 +4261,9 @@ if (BYTES_BIG_ENDIAN)
> UNSPEC_VLD1_LANE))]
> "TARGET_NEON"
> {
> - HOST_WIDE_INT lane = INTVAL (operands[3]);
> + HOST_WIDE_INT lane = ENDIAN_LANE_N(<MODE>mode, INTVAL (operands[3]));
> HOST_WIDE_INT max = GET_MODE_NUNITS (<MODE>mode);
> + operands[3] = GEN_INT (lane);
> if (lane < 0 || lane >= max)
> error ("lane out of range");
I'm just wondering whether these 'lane out of range' error messages can ever be
triggered now we have all the other checking? Can we now remove them (perhaps in
a followup patch)?
Cheers, Alan
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins
2015-10-07 0:00 ` [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins charles.baylis
@ 2015-10-12 10:58 ` Alan Lawrence
2015-10-14 22:02 ` Charles Baylis
0 siblings, 1 reply; 9+ messages in thread
From: Alan Lawrence @ 2015-10-12 10:58 UTC (permalink / raw)
To: charles.baylis, Kyrylo Tkachov, Ramana Radhakrishnan; +Cc: gcc-patches
On 07/10/15 00:59, charles.baylis@linaro.org wrote:
> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
...
> case NEON_ARG_MEMORY:
> /* Check if expand failed. */
> if (op[argc] == const0_rtx)
> {
> - va_end (ap);
> return 0;
> }
...and drop the braces?
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 02f5dc3..448cde3 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -30117,4 +30117,5 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
> *pri = tmp;
> return;
> }
> +
> #include "gt-arm.h"
This looks unrelated (and is the only change to arm.c) - perhaps commit
separately? (Note I am not a maintainer! But this looks "obvious"...)
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index 87c9f90..27ac4dc 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -288,6 +288,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
> #define TARGET_BPABI false
> #endif
>
> +#define ENDIAN_LANE_N(mode, n) \
> + (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
> +
Given we are making changes here to how this all works on bigendian, have you
tested armeb at all?
Generally I would say this all looks sensible :)
Cheers, Alan
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins
2015-10-12 10:58 ` Alan Lawrence
@ 2015-10-14 22:02 ` Charles Baylis
2015-10-19 16:59 ` Alan Lawrence
0 siblings, 1 reply; 9+ messages in thread
From: Charles Baylis @ 2015-10-14 22:02 UTC (permalink / raw)
To: Alan Lawrence; +Cc: Kyrylo Tkachov, Ramana Radhakrishnan, gcc-patches
On 12 October 2015 at 11:58, Alan Lawrence <alan.lawrence@arm.com> wrote:
> On 07/10/15 00:59, charles.baylis@linaro.org wrote:
>>
>> diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
>
> ...
>>
>> case NEON_ARG_MEMORY:
>> /* Check if expand failed. */
>> if (op[argc] == const0_rtx)
>> {
>> - va_end (ap);
>> return 0;
>> }
>
>
> ...and drop the braces?
Will do.
>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>> index 02f5dc3..448cde3 100644
>> --- a/gcc/config/arm/arm.c
>> +++ b/gcc/config/arm/arm.c
>> @@ -30117,4 +30117,5 @@ arm_sched_fusion_priority (rtx_insn *insn, int
>> max_pri,
>> *pri = tmp;
>> return;
>> }
>> +
>> #include "gt-arm.h"
>
>
> This looks unrelated (and is the only change to arm.c) - perhaps commit
> separately? (Note I am not a maintainer! But this looks "obvious"...)
It doesn't seem very useful. I'll drop it.
>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
>> index 87c9f90..27ac4dc 100644
>> --- a/gcc/config/arm/arm.h
>> +++ b/gcc/config/arm/arm.h
>> @@ -288,6 +288,9 @@ extern void
>> (*arm_lang_output_object_attributes_hook)(void);
>> #define TARGET_BPABI false
>> #endif
>>
>> +#define ENDIAN_LANE_N(mode, n) \
>> + (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n)
>> +
>
>
> Given we are making changes here to how this all works on bigendian, have
> you tested armeb at all?
I tested on big endian, and it passes, except for a testsuite issue
with the *_f16 tests, which fail because they are built without the
fp16 options on big endian. This is because
check_effective_target_arm_neon_fp16_ok_nocache gets an ICE when it
attempts to compile the test program. I think those fp16 intrinsics
are in your area, do you want to take a look? :)
Thanks for the review
Charles
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins
2015-10-14 22:02 ` Charles Baylis
@ 2015-10-19 16:59 ` Alan Lawrence
0 siblings, 0 replies; 9+ messages in thread
From: Alan Lawrence @ 2015-10-19 16:59 UTC (permalink / raw)
To: Charles Baylis; +Cc: Kyrylo Tkachov, Ramana Radhakrishnan, gcc-patches
On 14/10/15 23:02, Charles Baylis wrote:
> On 12 October 2015 at 11:58, Alan Lawrence <alan.lawrence@arm.com> wrote:
>
>> Given we are making changes here to how this all works on bigendian, have
>> you tested armeb at all?
>
> I tested on big endian, and it passes, except....
Well, I asked because it seemed good to make sure that the changes/improvements
to how lane-swapping was done, wasn't breaking anything on armeb by the back
door, and so thank you, I'm happy with that as far as your patch is concerned ;).
> for a testsuite issue
> with the *_f16 tests, which fail because they are built without the
> fp16 options on big endian. This is because
> check_effective_target_arm_neon_fp16_ok_nocache gets an ICE when it
> attempts to compile the test program. I think those fp16 intrinsics
> are in your area, do you want to take a look? :)
Heh, yes, I see ;). So I've dug into this a bit, and the problem seems to be
that we don't define a movv4hf pattern, and hence, we fall back to
emit_multi_word_move. This uses subregs, and in simplify_subreg_regno,
REG_CANNOT_CHANGE_MODE_P is true on bigendian (but false on little-endian).
That is, I *think* the right thing to do is just to add a movv4hf (and v8hf)
pattern, I'm testing this now....
Cheers, Alan
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2015-10-19 16:56 UTC | newest]
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2015-10-07 0:00 [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages charles.baylis
2015-10-07 0:00 ` [PATCH 2/3] [ARM] PR63870 Mark lane indices of vldN/vstN with appropriate qualifier charles.baylis
2015-10-12 10:50 ` Alan Lawrence
2015-10-07 0:00 ` [PATCH 1/3] [ARM] PR63870 Add qualifiers for NEON builtins charles.baylis
2015-10-12 10:58 ` Alan Lawrence
2015-10-14 22:02 ` Charles Baylis
2015-10-19 16:59 ` Alan Lawrence
2015-10-07 0:01 ` [PATCH 3/3] [ARM] PR63870 Enable test cases charles.baylis
2015-10-09 14:04 ` [PATCH v2 0/3] [ARM] PR63870 vldN_lane/vstN_lane error messages Charles Baylis
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