* [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check
@ 2023-07-17 14:20 Juzhe-Zhong
2023-07-17 14:24 ` Jeff Law
0 siblings, 1 reply; 5+ messages in thread
From: Juzhe-Zhong @ 2023-07-17 14:20 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, palmer, rdapp.gcc, jeffreyalaw, kito.cheng, Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_option_override): Add sorry check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: New test.
* gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: New test.
---
gcc/config/riscv/riscv.cc | 8 ++++++++
.../gcc.target/riscv/rvv/base/zvl-unimplemented-1.c | 4 ++++
.../gcc.target/riscv/rvv/base/zvl-unimplemented-2.c | 4 ++++
3 files changed, 16 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6ed735d6983..82e7c27b057 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -6672,6 +6672,14 @@ riscv_option_override (void)
riscv_stack_protector_guard_offset = offs;
}
+ /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
+ both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
+
+ We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
+ if (TARGET_MIN_VLEN > 4096)
+ sorry (
+ "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
+
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits ();
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
new file mode 100644
index 00000000000..03f67035ca4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */
+
+void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
new file mode 100644
index 00000000000..075112f2f81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
@@ -0,0 +1,4 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */
+
+void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" }
--
2.36.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check
2023-07-17 14:20 [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check Juzhe-Zhong
@ 2023-07-17 14:24 ` Jeff Law
2023-07-21 21:16 ` Andreas Schwab
0 siblings, 1 reply; 5+ messages in thread
From: Jeff Law @ 2023-07-17 14:24 UTC (permalink / raw)
To: Juzhe-Zhong, gcc-patches; +Cc: kito.cheng, palmer, rdapp.gcc, kito.cheng
On 7/17/23 08:20, Juzhe-Zhong wrote:
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_option_override): Add sorry check.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: New test.
> * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: New test.
OK
jeff
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check
2023-07-17 14:24 ` Jeff Law
@ 2023-07-21 21:16 ` Andreas Schwab
2023-07-21 21:20 ` Jeff Law
2023-07-24 14:16 ` Jeff Law
0 siblings, 2 replies; 5+ messages in thread
From: Andreas Schwab @ 2023-07-21 21:16 UTC (permalink / raw)
To: Jeff Law via Gcc-patches
Cc: Juzhe-Zhong, Jeff Law, kito.cheng, palmer, rdapp.gcc, kito.cheng
../../gcc/config/riscv/riscv.cc: In function 'void riscv_option_override()':
../../gcc/config/riscv/riscv.cc:6716:7: error: misspelled term 'can not' in format; use 'cannot' instead [-Werror=format-diag]
6716 | "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../gcc/config/riscv/riscv.cc:6716:7: error: unbalanced punctuation character '>' in format [-Werror=format-diag]
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check
2023-07-21 21:16 ` Andreas Schwab
@ 2023-07-21 21:20 ` Jeff Law
2023-07-24 14:16 ` Jeff Law
1 sibling, 0 replies; 5+ messages in thread
From: Jeff Law @ 2023-07-21 21:20 UTC (permalink / raw)
To: Andreas Schwab, Jeff Law via Gcc-patches
Cc: Juzhe-Zhong, kito.cheng, palmer, rdapp.gcc, kito.cheng
On 7/21/23 15:16, Andreas Schwab wrote:
> ../../gcc/config/riscv/riscv.cc: In function 'void riscv_option_override()':
> ../../gcc/config/riscv/riscv.cc:6716:7: error: misspelled term 'can not' in format; use 'cannot' instead [-Werror=format-diag]
> 6716 | "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> ../../gcc/config/riscv/riscv.cc:6716:7: error: unbalanced punctuation character '>' in format [-Werror=format-diag]
Thanks. There's another similar warning with strong accents. I'll deal
with both.
jeff
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check
2023-07-21 21:16 ` Andreas Schwab
2023-07-21 21:20 ` Jeff Law
@ 2023-07-24 14:16 ` Jeff Law
1 sibling, 0 replies; 5+ messages in thread
From: Jeff Law @ 2023-07-24 14:16 UTC (permalink / raw)
To: Andreas Schwab, Jeff Law via Gcc-patches
Cc: Juzhe-Zhong, kito.cheng, palmer, rdapp.gcc, kito.cheng
On 7/21/23 15:16, Andreas Schwab wrote:
> ../../gcc/config/riscv/riscv.cc: In function 'void riscv_option_override()':
> ../../gcc/config/riscv/riscv.cc:6716:7: error: misspelled term 'can not' in format; use 'cannot' instead [-Werror=format-diag]
> 6716 | "Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension");
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> ../../gcc/config/riscv/riscv.cc:6716:7: error: unbalanced punctuation character '>' in format [-Werror=format-diag]
I've fixed all three diagnostic warnings that my bootstrap tests
stumbled over. 23hrs later, successful bootstrap.
jeff
^ permalink raw reply [flat|nested] 5+ messages in thread
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2023-07-17 14:20 [PATCH V3] RISC-V: Add TARGET_MIN_VLEN > 4096 check Juzhe-Zhong
2023-07-17 14:24 ` Jeff Law
2023-07-21 21:16 ` Andreas Schwab
2023-07-21 21:20 ` Jeff Law
2023-07-24 14:16 ` Jeff Law
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