[PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all

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* [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all
@ 2023-04-06 13:34 yanzhang.wang
  2023-04-06 13:47 ` juzhe.zhong
                   ` (4 more replies)
  0 siblings, 5 replies; 14+ messages in thread
From: yanzhang.wang @ 2023-04-06 13:34 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.

	PR 109104

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (default_zero_call_used_regs):
	(riscv_zero_call_used_regs):
	* config/riscv/riscv.cc (riscv_zero_call_used_regs):
	(TARGET_ZERO_CALL_USED_REGS):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
	* gcc.target/riscv/zero-scratch-regs-2.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-v.cc                   | 79 +++++++++++++++++++
 gcc/config/riscv/riscv.cc                     |  6 ++
 .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
 .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 ++++++
 4 files changed, 118 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..90c69b52bb4 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -43,6 +43,7 @@
 #include "optabs.h"
 #include "tm-constrs.h"
 #include "rtx-vector-builder.h"
+#include "diagnostic-core.h"
 
 using namespace riscv_vector;
 
@@ -724,4 +725,82 @@ gen_avl_for_scalar_move (rtx avl)
     }
 }
 
+/* Generate a sequence of instructions that zero registers specified by
+   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
+   zeroed.  */
+static HARD_REG_SET
+gpr_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; ++regno)
+    {
+      if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	continue;
+
+      rtx reg = regno_reg_rtx[regno];
+      machine_mode mode = GET_MODE (reg);
+      emit_move_insn (reg, CONST0_RTX (mode));
+
+      SET_HARD_REG_BIT (zeroed_hardregs, regno);
+    }
+
+  return zeroed_hardregs;
+}
+
+static HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  /* Find a register to hold vl.  */
+  unsigned vl_regno = GP_REG_LAST + 1;
+  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+    {
+      /* If vl and avl both are x0, the existing vl is kept.  */
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno) && regno != X0_REGNUM)
+	{
+	  vl_regno = regno;
+	  break;
+	}
+    }
+
+  if (vl_regno > GP_REG_LAST)
+    sorry ("can't allocate vl register for %qs on this target",
+	   "-fzero-call-used-regs");
+
+  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
+  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  rtx target = regno_reg_rtx[regno];
+	  machine_mode mode = GET_MODE (target);
+	  poly_uint16 nunits = GET_MODE_NUNITS (mode);
+	  machine_mode mask_mode = get_vector_mode (BImode, nunits).require ();
+
+	  emit_vlmax_vsetvl (mode, vl);
+	  emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode),
+			 vl, mask_mode);
+
+	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
+	}
+    }
+
+  return zeroed_hardregs;
+}
+
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  if (TARGET_VECTOR)
+    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
+
+  return zeroed_hardregs | gpr_zero_call_used_regs (need_zeroed_hardregs);
+}
 } // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..e176f2d9f34 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
 
+namespace riscv_vector {
+extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
+}
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_vector::riscv_zero_call_used_regs
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..2d9dfeb9dc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..a53f034b5d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
-- 
2.39.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-06 13:34 [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all yanzhang.wang
@ 2023-04-06 13:47 ` juzhe.zhong
  2023-04-06 14:59   ` Kito Cheng
  2023-04-07  6:59 ` [PATCH v2] " yanzhang.wang
                   ` (3 subsequent siblings)
  4 siblings, 1 reply; 14+ messages in thread
From: juzhe.zhong @ 2023-04-06 13:47 UTC (permalink / raw)
  To: yanzhang.wang, gcc-patches; +Cc: Kito.cheng, pan2.li, yanzhang.wang

[-- Attachment #1: Type: text/plain, Size: 7174 bytes --]

--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
 
+namespace riscv_vector {
+extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
+}

namespace riscv_vector should be put in the riscv-protos.h. Since there is already a riscv_vector namespace there.


juzhe.zhong@rivai.ai
 
From: yanzhang.wang
Date: 2023-04-06 21:34
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all
From: Yanzhang Wang <yanzhang.wang@intel.com>
 
This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.
 
PR 109104
 
gcc/ChangeLog:
 
* config/riscv/riscv-v.cc (default_zero_call_used_regs):
(riscv_zero_call_used_regs):
* config/riscv/riscv.cc (riscv_zero_call_used_regs):
(TARGET_ZERO_CALL_USED_REGS):
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/zero-scratch-regs-1.c: New test.
* gcc.target/riscv/zero-scratch-regs-2.c: New test.
 
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
gcc/config/riscv/riscv-v.cc                   | 79 +++++++++++++++++++
gcc/config/riscv/riscv.cc                     |  6 ++
.../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
.../gcc.target/riscv/zero-scratch-regs-2.c    | 24 ++++++
4 files changed, 118 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
 
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..90c69b52bb4 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -43,6 +43,7 @@
#include "optabs.h"
#include "tm-constrs.h"
#include "rtx-vector-builder.h"
+#include "diagnostic-core.h"
using namespace riscv_vector;
@@ -724,4 +725,82 @@ gen_avl_for_scalar_move (rtx avl)
     }
}
+/* Generate a sequence of instructions that zero registers specified by
+   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
+   zeroed.  */
+static HARD_REG_SET
+gpr_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; ++regno)
+    {
+      if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+ continue;
+
+      rtx reg = regno_reg_rtx[regno];
+      machine_mode mode = GET_MODE (reg);
+      emit_move_insn (reg, CONST0_RTX (mode));
+
+      SET_HARD_REG_BIT (zeroed_hardregs, regno);
+    }
+
+  return zeroed_hardregs;
+}
+
+static HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  /* Find a register to hold vl.  */
+  unsigned vl_regno = GP_REG_LAST + 1;
+  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+    {
+      /* If vl and avl both are x0, the existing vl is kept.  */
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno) && regno != X0_REGNUM)
+ {
+   vl_regno = regno;
+   break;
+ }
+    }
+
+  if (vl_regno > GP_REG_LAST)
+    sorry ("can't allocate vl register for %qs on this target",
+    "-fzero-call-used-regs");
+
+  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
+  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+ {
+   rtx target = regno_reg_rtx[regno];
+   machine_mode mode = GET_MODE (target);
+   poly_uint16 nunits = GET_MODE_NUNITS (mode);
+   machine_mode mask_mode = get_vector_mode (BImode, nunits).require ();
+
+   emit_vlmax_vsetvl (mode, vl);
+   emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode),
+ vl, mask_mode);
+
+   SET_HARD_REG_BIT (zeroed_hardregs, regno);
+ }
+    }
+
+  return zeroed_hardregs;
+}
+
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  if (TARGET_VECTOR)
+    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
+
+  return zeroed_hardregs | gpr_zero_call_used_regs (need_zeroed_hardregs);
+}
} // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..e176f2d9f34 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
#undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
#define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
+namespace riscv_vector {
+extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
+}
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_vector::riscv_zero_call_used_regs
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..2d9dfeb9dc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..a53f034b5d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
-- 
2.39.2
 
 

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-06 13:47 ` juzhe.zhong
@ 2023-04-06 14:59   ` Kito Cheng
  0 siblings, 0 replies; 14+ messages in thread
From: Kito Cheng @ 2023-04-06 14:59 UTC (permalink / raw)
  To: juzhe.zhong; +Cc: yanzhang.wang, gcc-patches, Kito.cheng, pan2.li

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..90c69b52bb4 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -43,6 +43,7 @@
> #include "optabs.h"
> #include "tm-constrs.h"
> #include "rtx-vector-builder.h"
> +#include "diagnostic-core.h"
> using namespace riscv_vector;
> @@ -724,4 +725,82 @@ gen_avl_for_scalar_move (rtx avl)
>      }
> }
> +/* Generate a sequence of instructions that zero registers specified by
> +   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
> +   zeroed.  */
> +static HARD_REG_SET
> +gpr_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

Drop this - call default_zero_call_used_regs instead of build our own one.

> +{
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; ++regno)
> +    {
> +      if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> + continue;
> +
> +      rtx reg = regno_reg_rtx[regno];
> +      machine_mode mode = GET_MODE (reg);
> +      emit_move_insn (reg, CONST0_RTX (mode));
> +
> +      SET_HARD_REG_BIT (zeroed_hardregs, regno);
> +    }
> +
> +  return zeroed_hardregs;
> +}
> +
> +static HARD_REG_SET
> +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

Plz move this into riscv.cc

> +{
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  /* Find a register to hold vl.  */
> +  unsigned vl_regno = GP_REG_LAST + 1;

Use INVALID_REGNUM as sentinel value

> +  for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)

Start from `GP_REG_FIRST + 1`

> +    {
> +      /* If vl and avl both are x0, the existing vl is kept.  */
> +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno) && regno != X0_REGNUM)

Then we don't need to check `regno != X0_REGNUM` here.

> + {
> +   vl_regno = regno;
> +   break;
> + }
> +    }
> +
> +  if (vl_regno > GP_REG_LAST)
> +    sorry ("can't allocate vl register for %qs on this target",
> +    "-fzero-call-used-regs");
> +
> +  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
> +  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
> +    {
> +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> + {
> +   rtx target = regno_reg_rtx[regno];
> +   machine_mode mode = GET_MODE (target);
> +   poly_uint16 nunits = GET_MODE_NUNITS (mode);
> +   machine_mode mask_mode = get_vector_mode (BImode, nunits).require ();
> +
> +   emit_vlmax_vsetvl (mode, vl);

You can add an variable to check vlmax_vsetvl is emitted or not, and
skip that if already emitted

e.g.

if (!emitted_vlmax_vsetvl)
  emit_vlmax_vsetvl (mode, vl);

emitted_vlmax_vsetvl = true;

Add a new function maybe named emit_hard_vlmax_vsetvl to prevent the
vsetvli instruction gone when optimization is enabled.
---
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4611447ddde..5244e8dcbf0 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -159,6 +159,7 @@ bool check_builtin_call (location_t,
vec<location_t>, unsigned int,
 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 bool legitimize_move (rtx, rtx, machine_mode);
 void emit_vlmax_vsetvl (machine_mode, rtx);
+void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 90c69b52bb4..6d34e3a2b6c 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -119,6 +119,20 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
          && IN_RANGE (INTVAL (elt), minval, maxval));
 }

+/* Emit a vlmax vsetvl instruction with side effect, this should be only used
+   when optimization is tune off or emit after vsetvl insertion pass.  */
+void
+emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
+{
+  unsigned int sew = get_sew (vmode);
+  enum vlmul_type vlmul = get_vlmul (vmode);
+  unsigned int ratio = calculate_ratio (sew, vlmul);
+
+  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+                        gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+                        const0_rtx));
+}
+
 void
 emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
 {
@@ -127,9 +141,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
   unsigned int ratio = calculate_ratio (sew, vlmul);

   if (!optimize)
-    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-                          gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
-                          const0_rtx));
+    emit_hard_vlmax_vsetvl (vmode, vl);
   else
     emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 }

---


> +   emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode),
> + vl, mask_mode);
> +
> +   SET_HARD_REG_BIT (zeroed_hardregs, regno);
> + }
> +    }
> +
> +  return zeroed_hardregs;
> +}
> +
> +HARD_REG_SET
> +riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

Plz move this into riscv.cc

> +{
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  if (TARGET_VECTOR)
> +    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
> +
> +  return zeroed_hardregs | gpr_zero_call_used_regs (need_zeroed_hardregs);

Call default_zero_call_used_regs here, e.g.

return zeroed_hardregs | default_zero_call_used_regs
(need_zeroed_hardregs & ~zeroed_hardregs);

Also one important reason is default_zero_call_used_regs also zero init all FRP.

> +}
> } // namespace riscv_vector
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5f542932d13..e176f2d9f34 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
> #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
> #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
> +namespace riscv_vector {
> +extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET);
> +}
> +#undef TARGET_ZERO_CALL_USED_REGS
> +#define TARGET_ZERO_CALL_USED_REGS riscv_vector::riscv_zero_call_used_regs
> +
> struct gcc_target targetm = TARGET_INITIALIZER;
> #include "gt-riscv.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> new file mode 100644
> index 00000000000..2d9dfeb9dc2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler-not "li\t" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> new file mode 100644
> index 00000000000..a53f034b5d5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> @@ -0,0 +1,24 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */

Add -march=rv64gc -mabi=lp64 to dg-options, otherwise it will failed
when default config is rv32e

Plz add one more test case with -march=rv64gcv -mabi=lp64 is work as well.

> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler-not "vsetvli" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
> --
> 2.39.2
>
>

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-06 13:34 [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all yanzhang.wang
  2023-04-06 13:47 ` juzhe.zhong
@ 2023-04-07  6:59 ` yanzhang.wang
  2023-04-07  7:07   ` Kito Cheng
  2023-04-07 12:32 ` [PATCH v3] " yanzhang.wang
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 14+ messages in thread
From: yanzhang.wang @ 2023-04-07  6:59 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.

	PR 109104

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (GCC_RISCV_PROTOS_H):
	(emit_hard_vlmax_vsetvl):
	(vector_zero_call_used_regs):
	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
	(emit_vlmax_vsetvl):
	(vector_zero_call_used_regs):
	* config/riscv/riscv.cc (riscv_zero_call_used_regs):
	(TARGET_ZERO_CALL_USED_REGS):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
	* gcc.target/riscv/zero-scratch-regs-3.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |  5 ++
 gcc/config/riscv/riscv-v.cc                   | 67 ++++++++++++++++++-
 gcc/config/riscv/riscv.cc                     | 21 ++++++
 .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
 .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 +++++++
 .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 ++++++++++++++++
 6 files changed, 180 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4611447ddde..7ab0ec4b8be 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -22,6 +22,8 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_RISCV_PROTOS_H
 #define GCC_RISCV_PROTOS_H
 
+#include "hard-reg-set.h"
+
 /* Symbol types we understand.  The order of this list must match that of
    the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST.  */
 enum riscv_symbol_type {
@@ -159,6 +161,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 bool legitimize_move (rtx, rtx, machine_mode);
 void emit_vlmax_vsetvl (machine_mode, rtx);
+void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
@@ -206,6 +209,8 @@ enum vlen_enum
 bool slide1_sew64_helper (int, machine_mode, machine_mode,
 			  machine_mode, rtx *);
 rtx gen_avl_for_scalar_move (rtx);
+
+HARD_REG_SET vector_zero_call_used_regs (HARD_REG_SET);
 }
 
 /* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..aad046240ee 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -43,6 +43,8 @@
 #include "optabs.h"
 #include "tm-constrs.h"
 #include "rtx-vector-builder.h"
+#include "diagnostic-core.h"
+#include "targhooks.h"
 
 using namespace riscv_vector;
 
@@ -118,6 +120,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
 	  && IN_RANGE (INTVAL (elt), minval, maxval));
 }
 
+/* Emit a vlmax vsetvl instruction with side effect, this should be only used
+   when optimization is tune off or emit after vsetvl insertion pass.  */
+void
+emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
+{
+  unsigned int sew = get_sew (vmode);
+  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+			 gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+			 const0_rtx));
+}
+
 void
 emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
 {
@@ -126,9 +139,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
   unsigned int ratio = calculate_ratio (sew, vlmul);
 
   if (!optimize)
-    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-			   gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
-			   const0_rtx));
+    emit_hard_vlmax_vsetvl (vmode, vl);
   else
     emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 }
@@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl)
     }
 }
 
+HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  /* Find a register to hold vl.  */
+  unsigned vl_regno = INVALID_REGNUM;
+  /* Skip the first GPR, otherwise the existing vl is kept due to the same
+     between vl and avl.  */
+  for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  vl_regno = regno;
+	  break;
+	}
+    }
+
+  if (vl_regno > GP_REG_LAST)
+    sorry ("can't allocate vl register for %qs on this target",
+	   "-fzero-call-used-regs");
+
+  bool emitted_vlmax_vsetvl = false;
+  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
+  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  rtx target = regno_reg_rtx[regno];
+	  machine_mode mode = GET_MODE (target);
+	  poly_uint16 nunits = GET_MODE_NUNITS (mode);
+	  machine_mode mask_mode = get_vector_mode (BImode, nunits).require ();
+
+	  if (!emitted_vlmax_vsetvl)
+	    {
+	      emit_hard_vlmax_vsetvl (mode, vl);
+	      emitted_vlmax_vsetvl = true;
+	    }
+
+	  emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode),
+			 vl, mask_mode);
+
+	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
+	}
+    }
+
+  return zeroed_hardregs;
+}
+
 } // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..c3ae9571766 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7066,6 +7066,24 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
   return shamt == ctz_hwi (mask);
 }
 
+/* Generate a sequence of instructions that zero registers specified by
+   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
+   zeroed.  */
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  if (TARGET_VECTOR)
+    zeroed_hardregs
+      |= riscv_vector::vector_zero_call_used_regs (need_zeroed_hardregs);
+
+  return zeroed_hardregs | default_zero_call_used_regs (need_zeroed_hardregs
+							& ~zeroed_hardregs);
+}
+
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -7317,6 +7335,9 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
 
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..41d94ab921a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..9161dd3d4ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
new file mode 100644
index 00000000000..824fe9e548f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O2 -fzero-call-used-regs=all" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
+/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */
-- 
2.39.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v2] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-07  6:59 ` [PATCH v2] " yanzhang.wang
@ 2023-04-07  7:07   ` Kito Cheng
  0 siblings, 0 replies; 14+ messages in thread
From: Kito Cheng @ 2023-04-07  7:07 UTC (permalink / raw)
  To: yanzhang.wang; +Cc: gcc-patches, juzhe.zhong, kito.cheng, pan2.li

Generally LGTM, just one more comment :)

> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..aad046240ee 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -724,4 +735,54 @@ gen_avl_for_scalar_move (rtx avl)
>      }
>  }
>
> +HARD_REG_SET
> +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)

I would prefer this should be moved to riscv.cc too, major concern is
we don't want to introduce `hard-reg-set.h` into riscv-protos.h.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-06 13:34 [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all yanzhang.wang
  2023-04-06 13:47 ` juzhe.zhong
  2023-04-07  6:59 ` [PATCH v2] " yanzhang.wang
@ 2023-04-07 12:32 ` yanzhang.wang
  2023-04-08 18:39   ` Jeff Law
  2023-04-10  3:00 ` [PATCH v4] " yanzhang.wang
  2023-04-11 11:37 ` [PATCH v5] " yanzhang.wang
  4 siblings, 1 reply; 14+ messages in thread
From: yanzhang.wang @ 2023-04-07 12:32 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.

	PR 109104

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
	(emit_vlmax_vsetvl):
	* config/riscv/riscv.cc (vector_zero_call_used_regs):
	(riscv_zero_call_used_regs):
	(TARGET_ZERO_CALL_USED_REGS):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
	* gcc.target/riscv/zero-scratch-regs-3.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |  1 +
 gcc/config/riscv/riscv-v.cc                   | 15 +++-
 gcc/config/riscv/riscv.cc                     | 71 +++++++++++++++++++
 .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
 .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 +++++++
 .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 +++++++++++++++
 6 files changed, 174 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4611447ddde..5244e8dcbf0 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -159,6 +159,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 bool legitimize_move (rtx, rtx, machine_mode);
 void emit_vlmax_vsetvl (machine_mode, rtx);
+void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..13dd6639c9f 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
 	  && IN_RANGE (INTVAL (elt), minval, maxval));
 }
 
+/* Emit a vlmax vsetvl instruction with side effect, this should be only used
+   when optimization is tune off or emit after vsetvl insertion pass.  */
+void
+emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
+{
+  unsigned int sew = get_sew (vmode);
+  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+			 gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+			 const0_rtx));
+}
+
 void
 emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
 {
@@ -126,9 +137,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
   unsigned int ratio = calculate_ratio (sew, vlmul);
 
   if (!optimize)
-    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-			   gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
-			   const0_rtx));
+    emit_hard_vlmax_vsetvl (vmode, vl);
   else
     emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..a6a610f5901 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7066,6 +7066,74 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
   return shamt == ctz_hwi (mask);
 }
 
+HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  /* Find a register to hold vl.  */
+  unsigned vl_regno = INVALID_REGNUM;
+  /* Skip the first GPR, otherwise the existing vl is kept due to the same
+     between vl and avl.  */
+  for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  vl_regno = regno;
+	  break;
+	}
+    }
+
+  if (vl_regno > GP_REG_LAST)
+    sorry ("cannot allocate vl register for %qs on this target",
+	   "-fzero-call-used-regs");
+
+  bool emitted_vlmax_vsetvl = false;
+  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
+  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  rtx target = regno_reg_rtx[regno];
+	  machine_mode mode = GET_MODE (target);
+	  poly_uint16 nunits = GET_MODE_NUNITS (mode);
+	  machine_mode mask_mode = riscv_vector::get_vector_mode (BImode,
+								  nunits)
+	    .require ();
+
+	  if (!emitted_vlmax_vsetvl)
+	    {
+	      riscv_vector::emit_hard_vlmax_vsetvl (mode, vl);
+	      emitted_vlmax_vsetvl = true;
+	    }
+
+	  riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,
+				       CONST0_RTX (mode), vl, mask_mode);
+
+	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
+	}
+    }
+
+  return zeroed_hardregs;
+}
+
+/* Generate a sequence of instructions that zero registers specified by
+   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
+   zeroed.  */
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  if (TARGET_VECTOR)
+    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
+
+  return zeroed_hardregs | default_zero_call_used_regs (need_zeroed_hardregs
+							& ~zeroed_hardregs);
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -7317,6 +7385,9 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
 
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..41d94ab921a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..9161dd3d4ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
new file mode 100644
index 00000000000..824fe9e548f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O2 -fzero-call-used-regs=all" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
+/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */
-- 
2.39.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-07 12:32 ` [PATCH v3] " yanzhang.wang
@ 2023-04-08 18:39   ` Jeff Law
  2023-04-10  2:21     ` Wang, Yanzhang
  0 siblings, 1 reply; 14+ messages in thread
From: Jeff Law @ 2023-04-08 18:39 UTC (permalink / raw)
  To: yanzhang.wang, gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li



On 4/7/23 06:32, yanzhang.wang--- via Gcc-patches wrote:
> From: Yanzhang Wang <yanzhang.wang@intel.com>
> 
> This patch registers a riscv specific function to
> TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
> clean gpr and vector relevant registers.
> 
> 	PR 109104
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
> 	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
> 	(emit_vlmax_vsetvl):
> 	* config/riscv/riscv.cc (vector_zero_call_used_regs):
> 	(riscv_zero_call_used_regs):
> 	(TARGET_ZERO_CALL_USED_REGS):
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
> 	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
> 	* gcc.target/riscv/zero-scratch-regs-3.c: New test.
Presumably the difficulty here is we need to find a suitable hard 
register so that we can emit the vsetvl.


> 
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Pan Li <pan2.li@intel.com>
> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>   gcc/config/riscv/riscv-protos.h               |  1 +
>   gcc/config/riscv/riscv-v.cc                   | 15 +++-
>   gcc/config/riscv/riscv.cc                     | 71 +++++++++++++++++++
>   .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
>   .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 +++++++
>   .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 +++++++++++++++
>   6 files changed, 174 insertions(+), 3 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
>   create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> 
> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
> index 2e91d019f6c..13dd6639c9f 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
>   	  && IN_RANGE (INTVAL (elt), minval, maxval));
>   }
>   
> +/* Emit a vlmax vsetvl instruction with side effect, this should be only used
> +   when optimization is tune off or emit after vsetvl insertion pass.  */
Minor grammar errors.  I'd probably write it as:

/* Emit a vlvax vsetvl instruction.  This should only be used
    when optimization is disabled or after the vsetvl insertion pass.  */


Do you need to save/restore the vector configuration before and after 
clearing the vector registers?    If so, that seems to be missing.  If 
not, it seems like a comment explaining why would be useful.




Jeff

^ permalink raw reply	[flat|nested] 14+ messages in thread

* RE: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-08 18:39   ` Jeff Law
@ 2023-04-10  2:21     ` Wang, Yanzhang
  2023-04-10  3:11       ` Kito Cheng
  0 siblings, 1 reply; 14+ messages in thread
From: Wang, Yanzhang @ 2023-04-10  2:21 UTC (permalink / raw)
  To: Jeff Law, gcc-patches; +Cc: juzhe.zhong, kito.cheng, Li, Pan2

Thanks Jeff's comment.

> Presumably the difficulty here is we need to find a suitable hard
> register so that we can emit the vsetvl.

Yes. We use the GPR which has been flagged in the need_zeroed_regs to
hold the vl. There should be one GPR we can use, otherwise, will throw
an exception.

> Do you need to save/restore the vector configuration before and after
> clearing the vector registers?    If so, that seems to be missing.  If
> not, it seems like a comment explaining why would be useful.

I'll add some comments in the code and want to explain here first.
We need not save/restore the vector configurations. Because, by design,
the RVV requires vsetvl when using vector instructions. When users want to
use the RVV insns next, they should have to issue vsetvl first.

Thanks,
Yanzhang

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v4] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-06 13:34 [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all yanzhang.wang
                   ` (2 preceding siblings ...)
  2023-04-07 12:32 ` [PATCH v3] " yanzhang.wang
@ 2023-04-10  3:00 ` yanzhang.wang
  2023-04-11 11:37 ` [PATCH v5] " yanzhang.wang
  4 siblings, 0 replies; 14+ messages in thread
From: yanzhang.wang @ 2023-04-10  3:00 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.

	PR 109104

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
	(emit_vlmax_vsetvl):
	* config/riscv/riscv.cc (vector_zero_call_used_regs):
	(riscv_zero_call_used_regs):
	(TARGET_ZERO_CALL_USED_REGS):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
	* gcc.target/riscv/zero-scratch-regs-3.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |  1 +
 gcc/config/riscv/riscv-v.cc                   | 15 +++-
 gcc/config/riscv/riscv.cc                     | 76 +++++++++++++++++++
 .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
 .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 ++++++
 .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 ++++++++++++++
 6 files changed, 179 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4611447ddde..5244e8dcbf0 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -159,6 +159,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 bool legitimize_move (rtx, rtx, machine_mode);
 void emit_vlmax_vsetvl (machine_mode, rtx);
+void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..e6c46b0a6a3 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
 	  && IN_RANGE (INTVAL (elt), minval, maxval));
 }
 
+/* Emit a vlmax vsetvl instruction. This should only be used when
+   optimization is disabled or after vsetvl insertion pass.  */
+void
+emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
+{
+  unsigned int sew = get_sew (vmode);
+  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+			 gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+			 const0_rtx));
+}
+
 void
 emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
 {
@@ -126,9 +137,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
   unsigned int ratio = calculate_ratio (sew, vlmul);
 
   if (!optimize)
-    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-			   gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
-			   const0_rtx));
+    emit_hard_vlmax_vsetvl (vmode, vl);
   else
     emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..d50ca9c02ea 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7066,6 +7066,79 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
   return shamt == ctz_hwi (mask);
 }
 
+HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  /* Find a register to hold vl.  */
+  unsigned vl_regno = INVALID_REGNUM;
+  /* Skip the first GPR, otherwise the existing vl is kept due to the same
+     between vl and avl.  */
+  for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  vl_regno = regno;
+	  break;
+	}
+    }
+
+  if (vl_regno > GP_REG_LAST)
+    sorry ("cannot allocate vl register for %qs on this target",
+	   "-fzero-call-used-regs");
+
+  /* We will not save and restore existing configurations set by
+     vsetvl. By design, most RVV instructions require the user to
+     issue vsetvl first before using. Those remaining instructions
+     will not be affected by vsetvl.  */
+
+  bool emitted_vlmax_vsetvl = false;
+  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
+  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  rtx target = regno_reg_rtx[regno];
+	  machine_mode mode = GET_MODE (target);
+	  poly_uint16 nunits = GET_MODE_NUNITS (mode);
+	  machine_mode mask_mode = riscv_vector::get_vector_mode (BImode,
+								  nunits)
+	    .require ();
+
+	  if (!emitted_vlmax_vsetvl)
+	    {
+	      riscv_vector::emit_hard_vlmax_vsetvl (mode, vl);
+	      emitted_vlmax_vsetvl = true;
+	    }
+
+	  riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,
+				       CONST0_RTX (mode), vl, mask_mode);
+
+	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
+	}
+    }
+
+  return zeroed_hardregs;
+}
+
+/* Generate a sequence of instructions that zero registers specified by
+   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
+   zeroed.  */
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  if (TARGET_VECTOR)
+    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
+
+  return zeroed_hardregs | default_zero_call_used_regs (need_zeroed_hardregs
+							& ~zeroed_hardregs);
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -7317,6 +7390,9 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
 
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..41d94ab921a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..9161dd3d4ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
new file mode 100644
index 00000000000..824fe9e548f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O2 -fzero-call-used-regs=all" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
+/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */
-- 
2.39.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-10  2:21     ` Wang, Yanzhang
@ 2023-04-10  3:11       ` Kito Cheng
  2023-04-10 20:57         ` Jeff Law
  0 siblings, 1 reply; 14+ messages in thread
From: Kito Cheng @ 2023-04-10  3:11 UTC (permalink / raw)
  To: Wang, Yanzhang; +Cc: Jeff Law, gcc-patches, juzhe.zhong, Li, Pan2

> > Do you need to save/restore the vector configuration before and after
> > clearing the vector registers?    If so, that seems to be missing.  If
> > not, it seems like a comment explaining why would be useful.
>
> I'll add some comments in the code and want to explain here first.
> We need not save/restore the vector configurations. Because, by design,
> the RVV requires vsetvl when using vector instructions. When users want to
> use the RVV insns next, they should have to issue vsetvl first.

I think one keypoint here is -fzero-call-used-regs=* emit zeroing
instruction before return,
that means there won't be any vector operations between return and
zeroing instructions,
so we don't need to restore the vcsr after zeroing.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-10  3:11       ` Kito Cheng
@ 2023-04-10 20:57         ` Jeff Law
  0 siblings, 0 replies; 14+ messages in thread
From: Jeff Law @ 2023-04-10 20:57 UTC (permalink / raw)
  To: Kito Cheng, Wang, Yanzhang; +Cc: gcc-patches, juzhe.zhong, Li, Pan2




On 4/9/23 21:11, Kito Cheng wrote:

> I think one keypoint here is -fzero-call-used-regs=* emit zeroing
> instruction before return, that means there won't be any vector
> operations between return and zeroing instructions, so we don't need
> to restore the vcsr after zeroing.
Oh yea, makes perfect sense.  Thanks.
jeff

^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v5] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-06 13:34 [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all yanzhang.wang
                   ` (3 preceding siblings ...)
  2023-04-10  3:00 ` [PATCH v4] " yanzhang.wang
@ 2023-04-11 11:37 ` yanzhang.wang
  2023-04-11 12:00   ` Wang, Yanzhang
  4 siblings, 1 reply; 14+ messages in thread
From: yanzhang.wang @ 2023-04-11 11:37 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang

From: Yanzhang Wang <yanzhang.wang@intel.com>

This patch registers a riscv specific function to
TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
clean gpr and vector relevant registers.

	PR 109104

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
	(emit_vlmax_vsetvl):
	* config/riscv/riscv.cc (vector_zero_call_used_regs):
	(riscv_zero_call_used_regs):
	(TARGET_ZERO_CALL_USED_REGS):

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
	* gcc.target/riscv/zero-scratch-regs-3.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
---
 gcc/config/riscv/riscv-protos.h               |  1 +
 gcc/config/riscv/riscv-v.cc                   | 15 +++-
 gcc/config/riscv/riscv.cc                     | 75 +++++++++++++++++++
 .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
 .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 ++++++
 .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 ++++++++++++++
 6 files changed, 178 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 4611447ddde..5244e8dcbf0 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -159,6 +159,7 @@ bool check_builtin_call (location_t, vec<location_t>, unsigned int,
 bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
 bool legitimize_move (rtx, rtx, machine_mode);
 void emit_vlmax_vsetvl (machine_mode, rtx);
+void emit_hard_vlmax_vsetvl (machine_mode, rtx);
 void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);
 void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
 void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2e91d019f6c..392f5d02e17 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval,
 	  && IN_RANGE (INTVAL (elt), minval, maxval));
 }
 
+/* Emit a vlmax vsetvl instruction.  This should only be used when
+   optimization is disabled or after vsetvl insertion pass.  */
+void
+emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl)
+{
+  unsigned int sew = get_sew (vmode);
+  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
+			 gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
+			 const0_rtx));
+}
+
 void
 emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
 {
@@ -126,9 +137,7 @@ emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
   unsigned int ratio = calculate_ratio (sew, vlmul);
 
   if (!optimize)
-    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-			   gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
-			   const0_rtx));
+    emit_hard_vlmax_vsetvl (vmode, vl);
   else
     emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio, Pmode)));
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5f542932d13..a9c9e1aa32b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7066,6 +7066,78 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
   return shamt == ctz_hwi (mask);
 }
 
+HARD_REG_SET
+vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  /* Find a register to hold vl.  */
+  unsigned vl_regno = INVALID_REGNUM;
+  /* Skip the first GPR, otherwise the existing vl is kept due to the same
+     between vl and avl.  */
+  for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  vl_regno = regno;
+	  break;
+	}
+    }
+
+  if (vl_regno > GP_REG_LAST)
+    sorry ("cannot allocate vl register for %qs on this target",
+	   "-fzero-call-used-regs");
+
+  /* Vector configurations need not be saved and restored here.  The
+     -fzero-call-used-regs=* option will zero all vector registers and
+     return.  So there's no vector operations between them.  */
+
+  bool emitted_vlmax_vsetvl = false;
+  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
+  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
+    {
+      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
+	{
+	  rtx target = regno_reg_rtx[regno];
+	  machine_mode mode = GET_MODE (target);
+	  poly_uint16 nunits = GET_MODE_NUNITS (mode);
+	  machine_mode mask_mode = riscv_vector::get_vector_mode (BImode,
+								  nunits)
+	    .require ();
+
+	  if (!emitted_vlmax_vsetvl)
+	    {
+	      riscv_vector::emit_hard_vlmax_vsetvl (mode, vl);
+	      emitted_vlmax_vsetvl = true;
+	    }
+
+	  riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,
+				       CONST0_RTX (mode), vl, mask_mode);
+
+	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
+	}
+    }
+
+  return zeroed_hardregs;
+}
+
+/* Generate a sequence of instructions that zero registers specified by
+   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
+   zeroed.  */
+HARD_REG_SET
+riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+  HARD_REG_SET zeroed_hardregs;
+  CLEAR_HARD_REG_SET (zeroed_hardregs);
+
+  if (TARGET_VECTOR)
+    zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs);
+
+  return zeroed_hardregs | default_zero_call_used_regs (need_zeroed_hardregs
+							& ~zeroed_hardregs);
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -7317,6 +7389,9 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask)
 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
 
+#undef TARGET_ZERO_CALL_USED_REGS
+#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
new file mode 100644
index 00000000000..41d94ab921a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "li\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
new file mode 100644
index 00000000000..9161dd3d4ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fzero-call-used-regs=all-gpr" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler-not "vsetvli" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
new file mode 100644
index 00000000000..824fe9e548f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O2 -fzero-call-used-regs=all" } */
+
+void
+foo (void)
+{
+}
+
+/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */
+/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
+/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
+/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */
-- 
2.39.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* RE: [PATCH v5] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-11 11:37 ` [PATCH v5] " yanzhang.wang
@ 2023-04-11 12:00   ` Wang, Yanzhang
  2023-04-11 14:11     ` Kito Cheng
  0 siblings, 1 reply; 14+ messages in thread
From: Wang, Yanzhang @ 2023-04-11 12:00 UTC (permalink / raw)
  To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, Li, Pan2, jeffreyalaw

Hi Kito, Juzhe, Jeff,

Thanks for your kindly reviews. I have modified based on the comments and ran the testsuite on my local. Could you please take another look ? If any more comments please let me know.

Thanks
Yanzhang

> -----Original Message-----
> From: Wang, Yanzhang <yanzhang.wang@intel.com>
> Sent: Tuesday, April 11, 2023 7:38 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2
> <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: [PATCH v5] RISC-V: Fix regression of -fzero-call-used-regs=all
> 
> From: Yanzhang Wang <yanzhang.wang@intel.com>
> 
> This patch registers a riscv specific function to
> TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
> clean gpr and vector relevant registers.
> 
> 	PR 109104
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
> 	* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
> 	(emit_vlmax_vsetvl):
> 	* config/riscv/riscv.cc (vector_zero_call_used_regs):
> 	(riscv_zero_call_used_regs):
> 	(TARGET_ZERO_CALL_USED_REGS):
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zero-scratch-regs-1.c: New test.
> 	* gcc.target/riscv/zero-scratch-regs-2.c: New test.
> 	* gcc.target/riscv/zero-scratch-regs-3.c: New test.
> 
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Pan Li <pan2.li@intel.com>
> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>  gcc/config/riscv/riscv-protos.h               |  1 +
>  gcc/config/riscv/riscv-v.cc                   | 15 +++-
>  gcc/config/riscv/riscv.cc                     | 75 +++++++++++++++++++
>  .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
>  .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 ++++++
>  .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 ++++++++++++++
>  6 files changed, 178 insertions(+), 3 deletions(-)  create mode 100644
> gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> 
> diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-
> protos.h index 4611447ddde..5244e8dcbf0 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -159,6 +159,7 @@ bool check_builtin_call (location_t, vec<location_t>,
> unsigned int,  bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
> HOST_WIDE_INT);  bool legitimize_move (rtx, rtx, machine_mode);  void
> emit_vlmax_vsetvl (machine_mode, rtx);
> +void emit_hard_vlmax_vsetvl (machine_mode, rtx);
>  void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);  void
> emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);  void
> emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); diff --git
> a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index
> 2e91d019f6c..392f5d02e17 100644
> --- a/gcc/config/riscv/riscv-v.cc
> +++ b/gcc/config/riscv/riscv-v.cc
> @@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> minval,
>  	  && IN_RANGE (INTVAL (elt), minval, maxval));  }
> 
> +/* Emit a vlmax vsetvl instruction.  This should only be used when
> +   optimization is disabled or after vsetvl insertion pass.  */ void
> +emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl) {
> +  unsigned int sew = get_sew (vmode);
> +  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
> +			 gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
> +			 const0_rtx));
> +}
> +
>  void
>  emit_vlmax_vsetvl (machine_mode vmode, rtx vl)  { @@ -126,9 +137,7 @@
> emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
>    unsigned int ratio = calculate_ratio (sew, vlmul);
> 
>    if (!optimize)
> -    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew,
> Pmode),
> -			   gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
> -			   const0_rtx));
> +    emit_hard_vlmax_vsetvl (vmode, vl);
>    else
>      emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio,
> Pmode)));  } diff --git a/gcc/config/riscv/riscv.cc
> b/gcc/config/riscv/riscv.cc index 5f542932d13..a9c9e1aa32b 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7066,6 +7066,78 @@ riscv_shamt_matches_mask_p (int shamt,
> HOST_WIDE_INT mask)
>    return shamt == ctz_hwi (mask);
>  }
> 
> +HARD_REG_SET
> +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) {
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  /* Find a register to hold vl.  */
> +  unsigned vl_regno = INVALID_REGNUM;
> +  /* Skip the first GPR, otherwise the existing vl is kept due to the
> same
> +     between vl and avl.  */
> +  for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++)
> +    {
> +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> +	{
> +	  vl_regno = regno;
> +	  break;
> +	}
> +    }
> +
> +  if (vl_regno > GP_REG_LAST)
> +    sorry ("cannot allocate vl register for %qs on this target",
> +	   "-fzero-call-used-regs");
> +
> +  /* Vector configurations need not be saved and restored here.  The
> +     -fzero-call-used-regs=* option will zero all vector registers and
> +     return.  So there's no vector operations between them.  */
> +
> +  bool emitted_vlmax_vsetvl = false;
> +  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
> +  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
> +    {
> +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> +	{
> +	  rtx target = regno_reg_rtx[regno];
> +	  machine_mode mode = GET_MODE (target);
> +	  poly_uint16 nunits = GET_MODE_NUNITS (mode);
> +	  machine_mode mask_mode = riscv_vector::get_vector_mode (BImode,
> +								  nunits)
> +	    .require ();
> +
> +	  if (!emitted_vlmax_vsetvl)
> +	    {
> +	      riscv_vector::emit_hard_vlmax_vsetvl (mode, vl);
> +	      emitted_vlmax_vsetvl = true;
> +	    }
> +
> +	  riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,
> +				       CONST0_RTX (mode), vl, mask_mode);
> +
> +	  SET_HARD_REG_BIT (zeroed_hardregs, regno);
> +	}
> +    }
> +
> +  return zeroed_hardregs;
> +}
> +
> +/* Generate a sequence of instructions that zero registers specified by
> +   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
> +   zeroed.  */
> +HARD_REG_SET
> +riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) {
> +  HARD_REG_SET zeroed_hardregs;
> +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> +
> +  if (TARGET_VECTOR)
> +    zeroed_hardregs |= vector_zero_call_used_regs
> + (need_zeroed_hardregs);
> +
> +  return zeroed_hardregs | default_zero_call_used_regs
> (need_zeroed_hardregs
> +							& ~zeroed_hardregs);
> +}
> +
>  /* Initialize the GCC target structure.  */  #undef
> TARGET_ASM_ALIGNED_HI_OP  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -7317,6 +7389,9 @@ riscv_shamt_matches_mask_p (int shamt,
> HOST_WIDE_INT mask)  #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
>  #define TARGET_DWARF_POLY_INDETERMINATE_VALUE
> riscv_dwarf_poly_indeterminate_value
> 
> +#undef TARGET_ZERO_CALL_USED_REGS
> +#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
> +
>  struct gcc_target targetm = TARGET_INITIALIZER;
> 
>  #include "gt-riscv.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> new file mode 100644
> index 00000000000..41d94ab921a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2
> +-fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler-not "li\t" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> new file mode 100644
> index 00000000000..9161dd3d4ec
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> @@ -0,0 +1,24 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2
> +-fzero-call-used-regs=all-gpr" } */
> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler-not "vsetvli" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> new file mode 100644
> index 00000000000..824fe9e548f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> @@ -0,0 +1,57 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O2
> +-fzero-call-used-regs=all" } */
> +
> +void
> +foo (void)
> +{
> +}
> +
> +/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" }
> +} */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */
> +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
> +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
> +/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */
> --
> 2.39.2


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v5] RISC-V: Fix regression of -fzero-call-used-regs=all
  2023-04-11 12:00   ` Wang, Yanzhang
@ 2023-04-11 14:11     ` Kito Cheng
  0 siblings, 0 replies; 14+ messages in thread
From: Kito Cheng @ 2023-04-11 14:11 UTC (permalink / raw)
  To: Wang, Yanzhang; +Cc: gcc-patches, juzhe.zhong, Li, Pan2, jeffreyalaw

Hi Yanzhang:

Thanks, applied to trunk now, and also congrats for your first patch on GCC!

On Tue, Apr 11, 2023 at 8:00 PM Wang, Yanzhang <yanzhang.wang@intel.com> wrote:
>
> Hi Kito, Juzhe, Jeff,
>
> Thanks for your kindly reviews. I have modified based on the comments and ran the testsuite on my local. Could you please take another look ? If any more comments please let me know.
>
> Thanks
> Yanzhang
>
> > -----Original Message-----
> > From: Wang, Yanzhang <yanzhang.wang@intel.com>
> > Sent: Tuesday, April 11, 2023 7:38 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2
> > <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> > Subject: [PATCH v5] RISC-V: Fix regression of -fzero-call-used-regs=all
> >
> > From: Yanzhang Wang <yanzhang.wang@intel.com>
> >
> > This patch registers a riscv specific function to
> > TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will
> > clean gpr and vector relevant registers.
> >
> >       PR 109104
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl):
> >       * config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl):
> >       (emit_vlmax_vsetvl):
> >       * config/riscv/riscv.cc (vector_zero_call_used_regs):
> >       (riscv_zero_call_used_regs):
> >       (TARGET_ZERO_CALL_USED_REGS):
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/zero-scratch-regs-1.c: New test.
> >       * gcc.target/riscv/zero-scratch-regs-2.c: New test.
> >       * gcc.target/riscv/zero-scratch-regs-3.c: New test.
> >
> > Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> > Co-authored-by: Pan Li <pan2.li@intel.com>
> > Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> > Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
> > ---
> >  gcc/config/riscv/riscv-protos.h               |  1 +
> >  gcc/config/riscv/riscv-v.cc                   | 15 +++-
> >  gcc/config/riscv/riscv.cc                     | 75 +++++++++++++++++++
> >  .../gcc.target/riscv/zero-scratch-regs-1.c    |  9 +++
> >  .../gcc.target/riscv/zero-scratch-regs-2.c    | 24 ++++++
> >  .../gcc.target/riscv/zero-scratch-regs-3.c    | 57 ++++++++++++++
> >  6 files changed, 178 insertions(+), 3 deletions(-)  create mode 100644
> > gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> >
> > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-
> > protos.h index 4611447ddde..5244e8dcbf0 100644
> > --- a/gcc/config/riscv/riscv-protos.h
> > +++ b/gcc/config/riscv/riscv-protos.h
> > @@ -159,6 +159,7 @@ bool check_builtin_call (location_t, vec<location_t>,
> > unsigned int,  bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
> > HOST_WIDE_INT);  bool legitimize_move (rtx, rtx, machine_mode);  void
> > emit_vlmax_vsetvl (machine_mode, rtx);
> > +void emit_hard_vlmax_vsetvl (machine_mode, rtx);
> >  void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);  void
> > emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);  void
> > emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); diff --git
> > a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index
> > 2e91d019f6c..392f5d02e17 100644
> > --- a/gcc/config/riscv/riscv-v.cc
> > +++ b/gcc/config/riscv/riscv-v.cc
> > @@ -118,6 +118,17 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT
> > minval,
> >         && IN_RANGE (INTVAL (elt), minval, maxval));  }
> >
> > +/* Emit a vlmax vsetvl instruction.  This should only be used when
> > +   optimization is disabled or after vsetvl insertion pass.  */ void
> > +emit_hard_vlmax_vsetvl (machine_mode vmode, rtx vl) {
> > +  unsigned int sew = get_sew (vmode);
> > +  emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
> > +                      gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
> > +                      const0_rtx));
> > +}
> > +
> >  void
> >  emit_vlmax_vsetvl (machine_mode vmode, rtx vl)  { @@ -126,9 +137,7 @@
> > emit_vlmax_vsetvl (machine_mode vmode, rtx vl)
> >    unsigned int ratio = calculate_ratio (sew, vlmul);
> >
> >    if (!optimize)
> > -    emit_insn (gen_vsetvl (Pmode, vl, RVV_VLMAX, gen_int_mode (sew,
> > Pmode),
> > -                        gen_int_mode (get_vlmul (vmode), Pmode), const0_rtx,
> > -                        const0_rtx));
> > +    emit_hard_vlmax_vsetvl (vmode, vl);
> >    else
> >      emit_insn (gen_vlmax_avl (Pmode, vl, gen_int_mode (ratio,
> > Pmode)));  } diff --git a/gcc/config/riscv/riscv.cc
> > b/gcc/config/riscv/riscv.cc index 5f542932d13..a9c9e1aa32b 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -7066,6 +7066,78 @@ riscv_shamt_matches_mask_p (int shamt,
> > HOST_WIDE_INT mask)
> >    return shamt == ctz_hwi (mask);
> >  }
> >
> > +HARD_REG_SET
> > +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) {
> > +  HARD_REG_SET zeroed_hardregs;
> > +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> > +
> > +  /* Find a register to hold vl.  */
> > +  unsigned vl_regno = INVALID_REGNUM;
> > +  /* Skip the first GPR, otherwise the existing vl is kept due to the
> > same
> > +     between vl and avl.  */
> > +  for (unsigned regno = GP_REG_FIRST + 1; regno <= GP_REG_LAST; regno++)
> > +    {
> > +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> > +     {
> > +       vl_regno = regno;
> > +       break;
> > +     }
> > +    }
> > +
> > +  if (vl_regno > GP_REG_LAST)
> > +    sorry ("cannot allocate vl register for %qs on this target",
> > +        "-fzero-call-used-regs");
> > +
> > +  /* Vector configurations need not be saved and restored here.  The
> > +     -fzero-call-used-regs=* option will zero all vector registers and
> > +     return.  So there's no vector operations between them.  */
> > +
> > +  bool emitted_vlmax_vsetvl = false;
> > +  rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX.  */
> > +  for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno)
> > +    {
> > +      if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
> > +     {
> > +       rtx target = regno_reg_rtx[regno];
> > +       machine_mode mode = GET_MODE (target);
> > +       poly_uint16 nunits = GET_MODE_NUNITS (mode);
> > +       machine_mode mask_mode = riscv_vector::get_vector_mode (BImode,
> > +                                                               nunits)
> > +         .require ();
> > +
> > +       if (!emitted_vlmax_vsetvl)
> > +         {
> > +           riscv_vector::emit_hard_vlmax_vsetvl (mode, vl);
> > +           emitted_vlmax_vsetvl = true;
> > +         }
> > +
> > +       riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,
> > +                                    CONST0_RTX (mode), vl, mask_mode);
> > +
> > +       SET_HARD_REG_BIT (zeroed_hardregs, regno);
> > +     }
> > +    }
> > +
> > +  return zeroed_hardregs;
> > +}
> > +
> > +/* Generate a sequence of instructions that zero registers specified by
> > +   NEED_ZEROED_HARDREGS.  Return the ZEROED_HARDREGS that are actually
> > +   zeroed.  */
> > +HARD_REG_SET
> > +riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) {
> > +  HARD_REG_SET zeroed_hardregs;
> > +  CLEAR_HARD_REG_SET (zeroed_hardregs);
> > +
> > +  if (TARGET_VECTOR)
> > +    zeroed_hardregs |= vector_zero_call_used_regs
> > + (need_zeroed_hardregs);
> > +
> > +  return zeroed_hardregs | default_zero_call_used_regs
> > (need_zeroed_hardregs
> > +                                                     & ~zeroed_hardregs);
> > +}
> > +
> >  /* Initialize the GCC target structure.  */  #undef
> > TARGET_ASM_ALIGNED_HI_OP  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> > @@ -7317,6 +7389,9 @@ riscv_shamt_matches_mask_p (int shamt,
> > HOST_WIDE_INT mask)  #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
> >  #define TARGET_DWARF_POLY_INDETERMINATE_VALUE
> > riscv_dwarf_poly_indeterminate_value
> >
> > +#undef TARGET_ZERO_CALL_USED_REGS
> > +#define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
> > +
> >  struct gcc_target targetm = TARGET_INITIALIZER;
> >
> >  #include "gt-riscv.h"
> > diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> > b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> > new file mode 100644
> > index 00000000000..41d94ab921a
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c
> > @@ -0,0 +1,9 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gc -mabi=lp64 -O2
> > +-fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */
> > +
> > +void
> > +foo (void)
> > +{
> > +}
> > +
> > +/* { dg-final { scan-assembler-not "li\t" } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> > b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> > new file mode 100644
> > index 00000000000..9161dd3d4ec
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c
> > @@ -0,0 +1,24 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gc -mabi=lp64 -O2
> > +-fzero-call-used-regs=all-gpr" } */
> > +
> > +void
> > +foo (void)
> > +{
> > +}
> > +
> > +/* { dg-final { scan-assembler-not "vsetvli" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
> > diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> > b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> > new file mode 100644
> > index 00000000000..824fe9e548f
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-3.c
> > @@ -0,0 +1,57 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-march=rv64gcv -mabi=lp64 -O2
> > +-fzero-call-used-regs=all" } */
> > +
> > +void
> > +foo (void)
> > +{
> > +}
> > +
> > +/* { dg-final { scan-assembler "vsetvli\[ \t\]*t0,zero,e32,m1,tu,mu" }
> > +} */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v0,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v1,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v2,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v3,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v4,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v5,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v6,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v7,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v8,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v9,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v10,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v11,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v12,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v13,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v14,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v15,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v16,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v17,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v18,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v19,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v20,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v21,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v22,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v23,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v24,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v25,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v26,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v27,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v28,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v29,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v30,0" } } */
> > +/* { dg-final { scan-assembler "vmv.v.i\[ \t\]*v31,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */
> > +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */
> > +/* { dg-final { scan-assembler "fmv.d.x\[ \t\]*ft0,zero" } } */
> > --
> > 2.39.2
>

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2023-04-11 14:12 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-06 13:34 [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all yanzhang.wang
2023-04-06 13:47 ` juzhe.zhong
2023-04-06 14:59   ` Kito Cheng
2023-04-07  6:59 ` [PATCH v2] " yanzhang.wang
2023-04-07  7:07   ` Kito Cheng
2023-04-07 12:32 ` [PATCH v3] " yanzhang.wang
2023-04-08 18:39   ` Jeff Law
2023-04-10  2:21     ` Wang, Yanzhang
2023-04-10  3:11       ` Kito Cheng
2023-04-10 20:57         ` Jeff Law
2023-04-10  3:00 ` [PATCH v4] " yanzhang.wang
2023-04-11 11:37 ` [PATCH v5] " yanzhang.wang
2023-04-11 12:00   ` Wang, Yanzhang
2023-04-11 14:11     ` Kito Cheng

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