From: Kito Cheng <kito.cheng@gmail.com>
To: "Maciej W. Rozycki" <macro@embecosm.com>
Cc: gcc-patches@gcc.gnu.org, Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations
Date: Sun, 19 Nov 2023 14:44:54 +0800 [thread overview]
Message-ID: <CA+yXCZBjQbFWH2g7JwN5tM08_fW9HBg7z=J=gDrGAeuzVs4NLA@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.20.2311171516550.5892@tpp.orcam.me.uk>
LGTM, thanks for those test cases!
On Sun, Nov 19, 2023 at 1:37 PM Maciej W. Rozycki <macro@embecosm.com> wrote:
>
> Verify, for T-Head, Ventana and Zicond targets and the integer
> conditional-move operations that already work as expected, that
> if-conversion does *not* trigger at the respective sufficiently low
> `-mbranch-cost=' settings that make original branched code sequences
> cheaper than their branchless equivalents if-conversion would emit.
> Cover all integer relational operations to make sure no corner case
> escapes.
>
> The reason to XFAIL movdibne-thead.c and movsibne-thead.c is the
> branchless T-Head sequence:
>
> sub a1,a0,a1
> th.mveqz a2,a3,a1
> mv a0,a2
> ret
>
> produced rather than its original branched counterpart:
>
> beq a0,a1,.L3
> mv a0,a2
> ret
> .L3:
> mv a0,a3
> ret
>
> at `-mbranch-cost=1', even though under this setting the latter sequence
> is obviously cheaper performance-wise. This is because the final move
> instruction in the branchless sequence is not counted towards its cost
> and consequently the cost of both sequences works out at 8 each, making
> if-conversion prefer the branchless variant. Use the XFAIL mark to keep
> track of these cases for future consideration.
>
> gcc/testsuite/
> * gcc.target/riscv/movdibeq-thead.c: New test.
> * gcc.target/riscv/movdibge-ventana.c: New test.
> * gcc.target/riscv/movdibge-zicond.c: New test.
> * gcc.target/riscv/movdibgeu-ventana.c: New test.
> * gcc.target/riscv/movdibgeu-zicond.c: New test.
> * gcc.target/riscv/movdibgt-ventana.c: New test.
> * gcc.target/riscv/movdibgt-zicond.c: New test.
> * gcc.target/riscv/movdible-ventana.c: New test.
> * gcc.target/riscv/movdible-zicond.c: New test.
> * gcc.target/riscv/movdibleu-ventana.c: New test.
> * gcc.target/riscv/movdibleu-zicond.c: New test.
> * gcc.target/riscv/movdiblt-ventana.c: New test.
> * gcc.target/riscv/movdiblt-zicond.c: New test.
> * gcc.target/riscv/movdibne-thead.c: New test.
> * gcc.target/riscv/movsibeq-thead.c: New test.
> * gcc.target/riscv/movsibge-ventana.c: New test.
> * gcc.target/riscv/movsibge-zicond.c: New test.
> * gcc.target/riscv/movsibgeu-ventana.c: New test.
> * gcc.target/riscv/movsibgeu-zicond.c: New test.
> * gcc.target/riscv/movsibgt-ventana.c: New test.
> * gcc.target/riscv/movsibgt-zicond.c: New test.
> * gcc.target/riscv/movsible-ventana.c: New test.
> * gcc.target/riscv/movsible-zicond.c: New test.
> * gcc.target/riscv/movsibleu-ventana.c: New test.
> * gcc.target/riscv/movsibleu-zicond.c: New test.
> * gcc.target/riscv/movsiblt-ventana.c: New test.
> * gcc.target/riscv/movsiblt-zicond.c: New test.
> * gcc.target/riscv/movsibne-thead.c: New test.
> ---
> gcc/testsuite/gcc.target/riscv/movdibeq-thead.c | 27 +++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibge-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibge-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdible-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdible-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movdibne-thead.c | 29 +++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibeq-thead.c | 27 +++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibge-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibge-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsible-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsible-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c | 28 ++++++++++++++++++++
> gcc/testsuite/gcc.target/riscv/movsibne-thead.c | 29 +++++++++++++++++++++
> 28 files changed, 784 insertions(+)
>
> gcc-riscv-branch-cost-test-movcc-branch.diff
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibeq-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibeq-thead.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdieq (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w == x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bne a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibge-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + blt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibge-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibge-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + blt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bltu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgeu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bltu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + ble a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibgt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + ble a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdible-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdible-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdible-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdible-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibleu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgtu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibleu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgtu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdiblt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bge a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdiblt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bge a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movdibne-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movdibne-thead.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (DI))) int_t;
> +
> +int_t
> +movdine (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w != x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + beq a0,a1,.L3
> + mv a0,a2
> + ret
> +.L3:
> + mv a0,a3
> + ret
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibeq-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibeq-thead.c
> @@ -0,0 +1,27 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsieq (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w == x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bne a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibge-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + blt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibge-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibge-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsige (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + blt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bltu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgeu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigeu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w >= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bltu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + ble a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibgt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsigt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w > x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + ble a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsible-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsible-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsible-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsible-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsile (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgt a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibleu-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgtu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibleu-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef unsigned int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsileu (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w <= x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bgtu a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bgeu|bgtu|bleu|bltu)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgtu|sltu)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsiblt-ventana.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target rv64 } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bge a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskc\\s" } } */
> +/* { dg-final { scan-assembler-not "\\svt\\.maskcn\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsiblt-zicond.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mtune=rocket -mbranch-cost=3 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsilt (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w < x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + bge a0,a1,.L2
> + mv a3,a2
> +.L2:
> + mv a0,a3
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" } } */
> +/* { dg-final { scan-assembler-times "\\s(?:bge|bgt|ble|blt)\\s" 1 } } */
> +/* { dg-final { scan-assembler-not "\\s(?:sgt|slt)\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.eqz\\s" } } */
> +/* { dg-final { scan-assembler-not "\\sczero\\.nez\\s" } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
> Index: gcc/gcc/testsuite/gcc.target/riscv/movsibne-thead.c
> ===================================================================
> --- /dev/null
> +++ gcc/gcc/testsuite/gcc.target/riscv/movsibne-thead.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_xtheadcondmov -mtune=thead-c906 -mbranch-cost=1 -fdump-rtl-ce1" { target { rv32 } } } */
> +
> +typedef int __attribute__ ((mode (SI))) int_t;
> +
> +int_t
> +movsine (int_t w, int_t x, int_t y, int_t z)
> +{
> + return w != x ? y : z;
> +}
> +
> +/* Expect branched assembly like:
> +
> + beq a0,a1,.L3
> + mv a0,a2
> + ret
> +.L3:
> + mv a0,a3
> + ret
> + */
> +
> +/* { dg-final { scan-rtl-dump-not "Conversion succeeded on pass \[0-9\]+\\." "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-rtl-dump-not "if-conversion succeeded through" "ce1" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-times "\\s(?:beq|bne)\\s" 1 { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\ssub\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:th\\.mveqz|th\\.mvnez)\\s" { xfail "*-*-*" } } } */
> +/* { dg-final { scan-assembler-not "\\s(?:seqz|snez)\\s" } } */
next prev parent reply other threads:[~2023-11-19 6:45 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-19 5:35 [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Maciej W. Rozycki
2023-11-18 16:50 ` [PATCH 13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations Maciej W. Rozycki
2023-11-18 18:03 ` Jeff Law
2023-11-19 6:27 ` Maciej W. Rozycki
2023-11-19 5:37 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 01/44] testsuite: Add cases for conditional-move and conditional-add operations Maciej W. Rozycki
2023-11-19 5:52 ` Kito Cheng
2023-11-20 10:16 ` Maciej W. Rozycki
2023-11-20 12:57 ` Richard Biener
2023-11-22 1:33 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 02/44] RISC-V/testsuite: Add cases for integer SFB cond-move operations Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:35 ` [PATCH 03/44] RISC-V: Reorder comment on SFB patterns Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 04/44] RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare' Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 5:54 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 06/44] RISC-V: Avoid repeated GET_MODE calls " Maciej W. Rozycki
2023-11-19 5:55 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 07/44] RISC-V: Use `nullptr' " Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 08/44] RISC-V: Simplify EQ vs NE selection " Maciej W. Rozycki
2023-11-19 5:56 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 09/44] RISC-V: Rework branch costing model for if-conversion Maciej W. Rozycki
2023-11-19 18:52 ` Jeff Law
2023-11-23 18:34 ` Maciej W. Rozycki
2023-11-29 1:19 ` Jeff Law
2023-11-29 12:01 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations Maciej W. Rozycki
2023-11-19 6:44 ` Kito Cheng [this message]
2023-11-19 5:37 ` [PATCH 11/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 6:47 ` Kito Cheng
2023-11-23 19:18 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 12/44] RISC-V/testsuite: Add branched cases for FP " Maciej W. Rozycki
2023-11-19 6:48 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 14/44] RISC-V: Also invert the cond-move condition for GEU and LEU Maciej W. Rozycki
2023-11-19 6:50 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations Maciej W. Rozycki
2023-11-19 17:42 ` Jeff Law
2023-11-19 5:38 ` [PATCH 16/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 7:22 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:38 ` [PATCH 18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:39 ` [PATCH 19/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:46 ` Jeff Law
2023-11-19 5:39 ` [PATCH 20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands Maciej W. Rozycki
2023-11-19 17:48 ` Jeff Law
2023-11-19 5:39 ` [PATCH 21/44] RISC-V: Also accept constants for T-Head cond-move data input operands Maciej W. Rozycki
2023-11-19 17:50 ` Jeff Law
2023-11-19 5:40 ` [PATCH 22/44] RISC-V: Fold all the cond-move variants together Maciej W. Rozycki
2023-11-19 18:35 ` Jeff Law
2023-11-19 5:40 ` [PATCH 23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 24/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 25/44] RISC-V: Implement `riscv_emit_unary' helper Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 26/44] RISC-V: Add `movMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-23 22:16 ` Maciej W. Rozycki
2023-11-19 5:40 ` [PATCH 27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-19 5:41 ` [PATCH 28/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:19 ` Jeff Law
2023-11-19 5:41 ` [PATCH 29/44] RISC-V: Add `addMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-23 22:36 ` Maciej W. Rozycki
2023-11-19 5:41 ` [PATCH 30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-19 5:41 ` [PATCH 31/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:25 ` Jeff Law
2023-11-23 22:48 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' Maciej W. Rozycki
2023-11-19 18:26 ` Jeff Law
2023-11-19 5:42 ` [PATCH 33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 18:30 ` Jeff Law
2023-11-23 22:55 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion Maciej W. Rozycki
2023-11-19 19:42 ` Jeff Law
2023-11-23 23:26 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons Maciej W. Rozycki
2023-11-19 19:44 ` Jeff Law
2023-11-19 5:42 ` [PATCH 36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves Maciej W. Rozycki
2023-11-19 19:45 ` Jeff Law
2023-11-19 5:43 ` [PATCH 37/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 39/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:47 ` Jeff Law
2023-11-19 5:43 ` [PATCH 40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion Maciej W. Rozycki
2023-11-19 19:51 ` Jeff Law
2023-11-22 1:37 ` Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 42/44] " Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 44/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 5:52 ` [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Kito Cheng
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