From: "Maciej W. Rozycki" <macro@embecosm.com>
To: gcc-patches@gcc.gnu.org
Cc: Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion
Date: Sun, 19 Nov 2023 05:38:35 +0000 (GMT) [thread overview]
Message-ID: <alpine.DEB.2.20.2311180424040.5892@tpp.orcam.me.uk> (raw)
In-Reply-To: <alpine.DEB.2.20.2311171315580.5892@tpp.orcam.me.uk>
In the non-zero case there is no need for the conditional value used by
Ventana and Zicond integer conditional operations to be specifically 1.
Regardless we canonicalize it by producing an extraneous conditional-set
operation, such as with the sequence below:
(insn 22 6 23 2 (set (reg:DI 141)
(minus:DI (reg/v:DI 135 [ w ])
(reg/v:DI 136 [ x ]))) 11 {subdi3}
(nil))
(insn 23 22 24 2 (set (reg:DI 140)
(ne:DI (reg:DI 141)
(const_int 0 [0]))) 307 {*sne_zero_didi}
(nil))
(insn 24 23 25 2 (set (reg:DI 143)
(if_then_else:DI (eq:DI (reg:DI 140)
(const_int 0 [0]))
(const_int 0 [0])
(reg:DI 13 a3 [ z ]))) 27913 {*czero.eqz.didi}
(nil))
(insn 25 24 26 2 (set (reg:DI 142)
(if_then_else:DI (ne:DI (reg:DI 140)
(const_int 0 [0]))
(const_int 0 [0])
(reg/v:DI 137 [ y ]))) 27914 {*czero.nez.didi}
(nil))
(insn 26 25 18 2 (set (reg/v:DI 138 [ z ])
(ior:DI (reg:DI 142)
(reg:DI 143))) 105 {iordi3}
(nil))
where insn 23 can well be removed without changing the semantics of the
sequence. This is actually fixed up later on by combine and the insn
does not make it to output meaning no SNEZ (or SEQZ in the reverse case)
appears in the assembly produced, however it counts towards the cost of
the sequence calculated by if-conversion, raising the trigger level for
the branchless sequence to be chosen. Arguably to emit this extraneous
operation it can be also considered rather sloppy of our backend's.
Remove the check for operand 1 being constant 0 in the Ventana/Zicond
case for equality comparisons then, observing that `riscv_zero_if_equal'
called via `riscv_emit_int_compare' will canonicalize the comparison if
required, removing the extraneous insn from output:
(insn 22 6 23 2 (set (reg:DI 142)
(minus:DI (reg/v:DI 135 [ w ])
(reg/v:DI 136 [ x ]))) 11 {subdi3}
(nil))
(insn 23 22 24 2 (set (reg:DI 141)
(if_then_else:DI (eq:DI (reg:DI 142)
(const_int 0 [0]))
(const_int 0 [0])
(reg:DI 13 a3 [ z ]))) 27913 {*czero.eqz.didi}
(nil))
(insn 24 23 25 2 (set (reg:DI 140)
(if_then_else:DI (ne:DI (reg:DI 142)
(const_int 0 [0]))
(const_int 0 [0])
(reg/v:DI 137 [ y ]))) 27914 {*czero.nez.didi}
(nil))
(insn 25 24 18 2 (set (reg/v:DI 138 [ z ])
(ior:DI (reg:DI 140)
(reg:DI 141))) 105 {iordi3}
(nil))
while keeping actual assembly produced the same.
Adjust branch costs across the test cases affected accordingly.
gcc/
* config/riscv/riscv.cc (riscv_expand_conditional_move): Remove
the check for operand 1 being constant 0 in the Ventana/Zicond
case for equality comparisons.
gcc/testsuite/
* gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c:
Lower `-mbranch-cost=' setting.
* gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c:
Likewise.
* gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c:
Likewise.
---
gcc/config/riscv/riscv.cc | 6 +++---
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c | 4 ++--
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c | 4 ++--
7 files changed, 15 insertions(+), 15 deletions(-)
gcc-riscv-expand-conditional-move-zicond-equality.diff
Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -4132,9 +4132,9 @@ riscv_expand_conditional_move (rtx dest,
return false;
/* Canonicalize the comparison. It must be an equality comparison
- against 0. If it isn't, then emit an SCC instruction so that
- we can then use an equality comparison against zero. */
- if (!equality_operator (op, VOIDmode) || op1 != CONST0_RTX (mode))
+ of integer operands. If it isn't, then emit an SCC instruction
+ so that we can then use an equality comparison against zero. */
+ if (!equality_operator (op, VOIDmode) || !INTEGRAL_MODE_P (mode0))
{
bool *invert_ptr = nullptr;
bool invert = false;
Index: gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c
+++ gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_imm.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=3" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=3" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
long primitiveSemantics_compare_imm_return_imm_imm_00(long a, long b) {
Index: gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c
+++ gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_imm_reg.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=3" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=3" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
long primitiveSemantics_compare_imm_return_imm_reg_00(long a, long b) {
Index: gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c
+++ gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_imm_return_reg_reg.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=5" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=5" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
long primitiveSemantics_compare_imm_return_reg_reg_00(long a, long b, long c) {
Index: gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c
+++ gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_imm.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=3" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=3" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
long primitiveSemantics_compare_reg_return_imm_imm_00(long a, long b, long c) {
Index: gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c
+++ gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_imm_reg.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=3" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=3" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
long primitiveSemantics_compare_reg_return_imm_reg_00(long a, long b, long c) {
Index: gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c
===================================================================
--- gcc.orig/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c
+++ gcc/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_return_reg_reg.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=5" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=5" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" { target { rv32 } } } */
/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
long primitiveSemantics_compare_reg_return_reg_reg_00(long a, long b, long c,
next prev parent reply other threads:[~2023-11-19 5:38 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-19 5:35 [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Maciej W. Rozycki
2023-11-18 16:50 ` [PATCH 13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations Maciej W. Rozycki
2023-11-18 18:03 ` Jeff Law
2023-11-19 6:27 ` Maciej W. Rozycki
2023-11-19 5:37 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 01/44] testsuite: Add cases for conditional-move and conditional-add operations Maciej W. Rozycki
2023-11-19 5:52 ` Kito Cheng
2023-11-20 10:16 ` Maciej W. Rozycki
2023-11-20 12:57 ` Richard Biener
2023-11-22 1:33 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 02/44] RISC-V/testsuite: Add cases for integer SFB cond-move operations Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:35 ` [PATCH 03/44] RISC-V: Reorder comment on SFB patterns Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 04/44] RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare' Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 5:54 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 06/44] RISC-V: Avoid repeated GET_MODE calls " Maciej W. Rozycki
2023-11-19 5:55 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 07/44] RISC-V: Use `nullptr' " Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 08/44] RISC-V: Simplify EQ vs NE selection " Maciej W. Rozycki
2023-11-19 5:56 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 09/44] RISC-V: Rework branch costing model for if-conversion Maciej W. Rozycki
2023-11-19 18:52 ` Jeff Law
2023-11-23 18:34 ` Maciej W. Rozycki
2023-11-29 1:19 ` Jeff Law
2023-11-29 12:01 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations Maciej W. Rozycki
2023-11-19 6:44 ` Kito Cheng
2023-11-19 5:37 ` [PATCH 11/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 6:47 ` Kito Cheng
2023-11-23 19:18 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 12/44] RISC-V/testsuite: Add branched cases for FP " Maciej W. Rozycki
2023-11-19 6:48 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 14/44] RISC-V: Also invert the cond-move condition for GEU and LEU Maciej W. Rozycki
2023-11-19 6:50 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations Maciej W. Rozycki
2023-11-19 17:42 ` Jeff Law
2023-11-19 5:38 ` [PATCH 16/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 7:22 ` Kito Cheng
2023-11-19 5:38 ` Maciej W. Rozycki [this message]
2023-11-19 17:45 ` [PATCH 17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion Jeff Law
2023-11-19 5:38 ` [PATCH 18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:39 ` [PATCH 19/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:46 ` Jeff Law
2023-11-19 5:39 ` [PATCH 20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands Maciej W. Rozycki
2023-11-19 17:48 ` Jeff Law
2023-11-19 5:39 ` [PATCH 21/44] RISC-V: Also accept constants for T-Head cond-move data input operands Maciej W. Rozycki
2023-11-19 17:50 ` Jeff Law
2023-11-19 5:40 ` [PATCH 22/44] RISC-V: Fold all the cond-move variants together Maciej W. Rozycki
2023-11-19 18:35 ` Jeff Law
2023-11-19 5:40 ` [PATCH 23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 24/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 25/44] RISC-V: Implement `riscv_emit_unary' helper Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 26/44] RISC-V: Add `movMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-23 22:16 ` Maciej W. Rozycki
2023-11-19 5:40 ` [PATCH 27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-19 5:41 ` [PATCH 28/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:19 ` Jeff Law
2023-11-19 5:41 ` [PATCH 29/44] RISC-V: Add `addMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-23 22:36 ` Maciej W. Rozycki
2023-11-19 5:41 ` [PATCH 30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-19 5:41 ` [PATCH 31/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:25 ` Jeff Law
2023-11-23 22:48 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' Maciej W. Rozycki
2023-11-19 18:26 ` Jeff Law
2023-11-19 5:42 ` [PATCH 33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 18:30 ` Jeff Law
2023-11-23 22:55 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion Maciej W. Rozycki
2023-11-19 19:42 ` Jeff Law
2023-11-23 23:26 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons Maciej W. Rozycki
2023-11-19 19:44 ` Jeff Law
2023-11-19 5:42 ` [PATCH 36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves Maciej W. Rozycki
2023-11-19 19:45 ` Jeff Law
2023-11-19 5:43 ` [PATCH 37/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 39/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:47 ` Jeff Law
2023-11-19 5:43 ` [PATCH 40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion Maciej W. Rozycki
2023-11-19 19:51 ` Jeff Law
2023-11-22 1:37 ` Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 42/44] " Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 44/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 5:52 ` [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Kito Cheng
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