From: "Maciej W. Rozycki" <macro@embecosm.com>
To: gcc-patches@gcc.gnu.org
Cc: Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons
Date: Sun, 19 Nov 2023 05:42:37 +0000 (GMT) [thread overview]
Message-ID: <alpine.DEB.2.20.2311182249380.5892@tpp.orcam.me.uk> (raw)
In-Reply-To: <alpine.DEB.2.20.2311171315580.5892@tpp.orcam.me.uk>
We have floating-point coditional-set machine instructions for a subset
of FP comparisons, so avoid going through a comparison against constant
zero in `riscv_expand_float_scc' where not necessary, preventing an
extraneous RTL instruction from being produced that counts against the
cost of the replacement branchless code sequence in if-conversion, e.g.:
(insn 29 6 30 2 (set (reg:DI 142)
(ge:DI (reg/v:DF 135 [ w ])
(reg/v:DF 136 [ x ]))) 297 {*cstoredfdi4}
(nil))
(insn 30 29 31 2 (set (reg:DI 143)
(ne:DI (reg:DI 142)
(const_int 0 [0]))) 319 {*sne_zero_didi}
(nil))
(insn 31 30 32 2 (set (reg:DI 141)
(reg:DI 143)) 206 {*movdi_64bit}
(nil))
(insn 32 31 33 2 (set (reg:DI 144)
(neg:DI (reg:DI 141))) 15 {negdi2}
(nil))
(insn 33 32 34 2 (set (reg:DI 145)
(and:DI (reg:DI 144)
(reg/v:DI 137 [ y ]))) 102 {*anddi3}
(nil))
(insn 34 33 35 2 (set (reg:DI 146)
(not:DI (reg:DI 144))) 111 {one_cmpldi2}
(nil))
(insn 35 34 36 2 (set (reg:DI 147)
(and:DI (reg:DI 146)
(reg/v:DI 138 [ z ]))) 102 {*anddi3}
(nil))
(insn 36 35 21 2 (set (reg/v:DI 138 [ z ])
(ior:DI (reg:DI 145)
(reg:DI 147))) 105 {iordi3}
(nil))
where the second insn effectively just copies its input. This now gets
simplified to:
(insn 29 6 30 2 (set (reg:DI 141)
(ge:DI (reg/v:DF 135 [ w ])
(reg/v:DF 136 [ x ]))) 297 {*cstoredfdi4}
(nil))
(insn 30 29 31 2 (set (reg:DI 142)
(neg:DI (reg:DI 141))) 15 {negdi2}
(nil))
(insn 31 30 32 2 (set (reg:DI 143)
(and:DI (reg:DI 142)
(reg/v:DI 137 [ y ]))) 102 {*anddi3}
(nil))
(insn 32 31 33 2 (set (reg:DI 144)
(not:DI (reg:DI 142))) 111 {one_cmpldi2}
(nil))
(insn 33 32 34 2 (set (reg:DI 145)
(and:DI (reg:DI 144)
(reg/v:DI 138 [ z ]))) 102 {*anddi3}
(nil))
(insn 34 33 21 2 (set (reg/v:DI 138 [ z ])
(ior:DI (reg:DI 143)
(reg:DI 145))) 105 {iordi3}
(nil))
lowering the cost of the code sequence produced (even though combine
would swallow the second insn anyway).
We still need to produce a comparison against constant zero where the
instruction following a floating-point coditional-set operation is a
branch, so add canonicalization to `riscv_expand_conditional_branch'
instead.
gcc/
* config/riscv/riscv.cc (riscv_emit_float_compare) <NE>: Handle
separately.
<EQ, LE, LT, GE, GT>: Return operands supplied as is.
(riscv_emit_binary): Call `riscv_emit_binary' directly rather
than going through a temporary register for word-mode targets.
(riscv_expand_conditional_branch): Canonicalize the comparison
if not against constant zero.
---
gcc/config/riscv/riscv.cc | 29 +++++++++++++++++++++--------
1 file changed, 21 insertions(+), 8 deletions(-)
gcc-riscv-emit-float-compare-fcmp.diff
Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -4029,9 +4029,10 @@ riscv_emit_float_compare (enum rtx_code
#undef UNORDERED_COMPARISON
case NE:
- fp_code = EQ;
*code = EQ;
- /* Fall through. */
+ *op0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1);
+ *op1 = const0_rtx;
+ break;
case EQ:
case LE:
@@ -4039,8 +4040,9 @@ riscv_emit_float_compare (enum rtx_code
case GE:
case GT:
/* We have instructions for these cases. */
- *op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1);
- *op1 = const0_rtx;
+ *code = fp_code;
+ *op0 = cmp_op0;
+ *op1 = cmp_op1;
break;
case LTGT:
@@ -4080,10 +4082,14 @@ riscv_expand_float_scc (rtx target, enum
{
riscv_emit_float_compare (&code, &op0, &op1);
- rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
- if (GET_MODE (target) != word_mode)
- cmp = lowpart_subreg (GET_MODE (target), cmp, word_mode);
- riscv_emit_set (target, cmp);
+ machine_mode mode = GET_MODE (target);
+ if (mode != word_mode)
+ {
+ rtx cmp = riscv_force_binary (word_mode, code, op0, op1);
+ riscv_emit_set (target, lowpart_subreg (mode, cmp, word_mode));
+ }
+ else
+ riscv_emit_binary (code, target, op0, op1);
}
/* Jump to LABEL if (CODE OP0 OP1) holds. */
@@ -4096,6 +4102,13 @@ riscv_expand_conditional_branch (rtx lab
else
riscv_emit_int_compare (&code, &op0, &op1);
+ if (FLOAT_MODE_P (GET_MODE (op0)))
+ {
+ op0 = riscv_force_binary (word_mode, code, op0, op1);
+ op1 = const0_rtx;
+ code = NE;
+ }
+
rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
emit_jump_insn (gen_condjump (condition, label));
}
next prev parent reply other threads:[~2023-11-19 5:42 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-19 5:35 [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Maciej W. Rozycki
2023-11-18 16:50 ` [PATCH 13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations Maciej W. Rozycki
2023-11-18 18:03 ` Jeff Law
2023-11-19 6:27 ` Maciej W. Rozycki
2023-11-19 5:37 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 01/44] testsuite: Add cases for conditional-move and conditional-add operations Maciej W. Rozycki
2023-11-19 5:52 ` Kito Cheng
2023-11-20 10:16 ` Maciej W. Rozycki
2023-11-20 12:57 ` Richard Biener
2023-11-22 1:33 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 02/44] RISC-V/testsuite: Add cases for integer SFB cond-move operations Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:35 ` [PATCH 03/44] RISC-V: Reorder comment on SFB patterns Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 04/44] RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare' Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 5:54 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 06/44] RISC-V: Avoid repeated GET_MODE calls " Maciej W. Rozycki
2023-11-19 5:55 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 07/44] RISC-V: Use `nullptr' " Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 08/44] RISC-V: Simplify EQ vs NE selection " Maciej W. Rozycki
2023-11-19 5:56 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 09/44] RISC-V: Rework branch costing model for if-conversion Maciej W. Rozycki
2023-11-19 18:52 ` Jeff Law
2023-11-23 18:34 ` Maciej W. Rozycki
2023-11-29 1:19 ` Jeff Law
2023-11-29 12:01 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations Maciej W. Rozycki
2023-11-19 6:44 ` Kito Cheng
2023-11-19 5:37 ` [PATCH 11/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 6:47 ` Kito Cheng
2023-11-23 19:18 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 12/44] RISC-V/testsuite: Add branched cases for FP " Maciej W. Rozycki
2023-11-19 6:48 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 14/44] RISC-V: Also invert the cond-move condition for GEU and LEU Maciej W. Rozycki
2023-11-19 6:50 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations Maciej W. Rozycki
2023-11-19 17:42 ` Jeff Law
2023-11-19 5:38 ` [PATCH 16/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 7:22 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:38 ` [PATCH 18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:39 ` [PATCH 19/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:46 ` Jeff Law
2023-11-19 5:39 ` [PATCH 20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands Maciej W. Rozycki
2023-11-19 17:48 ` Jeff Law
2023-11-19 5:39 ` [PATCH 21/44] RISC-V: Also accept constants for T-Head cond-move data input operands Maciej W. Rozycki
2023-11-19 17:50 ` Jeff Law
2023-11-19 5:40 ` [PATCH 22/44] RISC-V: Fold all the cond-move variants together Maciej W. Rozycki
2023-11-19 18:35 ` Jeff Law
2023-11-19 5:40 ` [PATCH 23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 24/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 25/44] RISC-V: Implement `riscv_emit_unary' helper Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 26/44] RISC-V: Add `movMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-23 22:16 ` Maciej W. Rozycki
2023-11-19 5:40 ` [PATCH 27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-19 5:41 ` [PATCH 28/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:19 ` Jeff Law
2023-11-19 5:41 ` [PATCH 29/44] RISC-V: Add `addMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-23 22:36 ` Maciej W. Rozycki
2023-11-19 5:41 ` [PATCH 30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-19 5:41 ` [PATCH 31/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:25 ` Jeff Law
2023-11-23 22:48 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' Maciej W. Rozycki
2023-11-19 18:26 ` Jeff Law
2023-11-19 5:42 ` [PATCH 33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 18:30 ` Jeff Law
2023-11-23 22:55 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion Maciej W. Rozycki
2023-11-19 19:42 ` Jeff Law
2023-11-23 23:26 ` Maciej W. Rozycki
2023-11-19 5:42 ` Maciej W. Rozycki [this message]
2023-11-19 19:44 ` [PATCH 35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons Jeff Law
2023-11-19 5:42 ` [PATCH 36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves Maciej W. Rozycki
2023-11-19 19:45 ` Jeff Law
2023-11-19 5:43 ` [PATCH 37/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 39/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:47 ` Jeff Law
2023-11-19 5:43 ` [PATCH 40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion Maciej W. Rozycki
2023-11-19 19:51 ` Jeff Law
2023-11-22 1:37 ` Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 42/44] " Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 44/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 5:52 ` [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Kito Cheng
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