From: "Maciej W. Rozycki" <macro@embecosm.com>
To: gcc-patches@gcc.gnu.org
Cc: Andrew Waterman <andrew@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Kito Cheng <kito.cheng@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion
Date: Sun, 19 Nov 2023 05:43:34 +0000 (GMT) [thread overview]
Message-ID: <alpine.DEB.2.20.2311190143100.5892@tpp.orcam.me.uk> (raw)
In-Reply-To: <alpine.DEB.2.20.2311171315580.5892@tpp.orcam.me.uk>
We have no FNE.fmt machine instructions, but we can emulate them for the
purpose of conditional-move and conditional-add operations by using the
respective FEQ.fmt instruction and then swapping the data input operands
or complementing the mask for the conditional addend respectively, so
update our handlers accordingly.
gcc/
* config/riscv/riscv-protos.h (riscv_expand_float_scc): Add
`invert_ptr' parameter.
* config/riscv/riscv.cc (riscv_emit_float_compare): Add NE
inversion handling.
(riscv_expand_float_scc): Pass `invert_ptr' through to
`riscv_emit_float_compare'.
(riscv_expand_conditional_move): Pass `&invert' to
`riscv_expand_float_scc'.
* config/riscv/riscv.md (add<mode>cc): Likewise.
---
gcc/config/riscv/riscv-protos.h | 3 ++-
gcc/config/riscv/riscv.cc | 23 +++++++++++++++--------
gcc/config/riscv/riscv.md | 2 +-
3 files changed, 18 insertions(+), 10 deletions(-)
gcc-riscv-emit-float-compare-ne.diff
Index: gcc/gcc/config/riscv/riscv-protos.h
===================================================================
--- gcc.orig/gcc/config/riscv/riscv-protos.h
+++ gcc/gcc/config/riscv/riscv-protos.h
@@ -132,7 +132,8 @@ riscv_zcmp_valid_stack_adj_bytes_p (HOST
#ifdef RTX_CODE
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0);
-extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
+extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx,
+ bool *invert_ptr = nullptr);
extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
extern rtx riscv_emit_unary (enum rtx_code code, rtx dest, rtx x);
extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -3965,7 +3965,8 @@ riscv_emit_int_compare (enum rtx_code *c
/* Like riscv_emit_int_compare, but for floating-point comparisons. */
static void
-riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1)
+riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1,
+ bool *invert_ptr = nullptr)
{
rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1;
enum rtx_code fp_code = *code;
@@ -4029,10 +4030,15 @@ riscv_emit_float_compare (enum rtx_code
#undef UNORDERED_COMPARISON
case NE:
- *code = EQ;
- *op0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1);
- *op1 = const0_rtx;
- break;
+ fp_code = EQ;
+ if (invert_ptr != nullptr)
+ *invert_ptr = !*invert_ptr;
+ else
+ {
+ cmp_op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1);
+ cmp_op1 = const0_rtx;
+ }
+ gcc_fallthrough ();
case EQ:
case LE:
@@ -4078,9 +4084,10 @@ riscv_expand_int_scc (rtx target, enum r
/* Like riscv_expand_int_scc, but for floating-point comparisons. */
void
-riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
+riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1,
+ bool *invert_ptr)
{
- riscv_emit_float_compare (&code, &op0, &op1);
+ riscv_emit_float_compare (&code, &op0, &op1, invert_ptr);
machine_mode mode = GET_MODE (target);
if (mode != word_mode)
@@ -4171,7 +4178,7 @@ riscv_expand_conditional_move (rtx dest,
riscv_expand_int_scc (tmp, code, op0, op1, invert_ptr);
else if (FLOAT_MODE_P (mode0)
&& fp_scc_comparison (op, GET_MODE (op)))
- riscv_expand_float_scc (tmp, code, op0, op1);
+ riscv_expand_float_scc (tmp, code, op0, op1, &invert);
else
return false;
Index: gcc/gcc/config/riscv/riscv.md
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.md
+++ gcc/gcc/config/riscv/riscv.md
@@ -2697,7 +2697,7 @@
if (INTEGRAL_MODE_P (mode0))
riscv_expand_int_scc (reg0, code, cmp0, cmp1, &invert);
else if (FLOAT_MODE_P (mode0) && fp_scc_comparison (cmp, GET_MODE (cmp)))
- riscv_expand_float_scc (reg0, code, cmp0, cmp1);
+ riscv_expand_float_scc (reg0, code, cmp0, cmp1, &invert);
else
FAIL;
next prev parent reply other threads:[~2023-11-19 5:43 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-19 5:35 [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Maciej W. Rozycki
2023-11-18 16:50 ` [PATCH 13/44] RISC-V/testsuite: Add branchless cases for FP cond-move operations Maciej W. Rozycki
2023-11-18 18:03 ` Jeff Law
2023-11-19 6:27 ` Maciej W. Rozycki
2023-11-19 5:37 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 01/44] testsuite: Add cases for conditional-move and conditional-add operations Maciej W. Rozycki
2023-11-19 5:52 ` Kito Cheng
2023-11-20 10:16 ` Maciej W. Rozycki
2023-11-20 12:57 ` Richard Biener
2023-11-22 1:33 ` Maciej W. Rozycki
2023-11-19 5:35 ` [PATCH 02/44] RISC-V/testsuite: Add cases for integer SFB cond-move operations Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:35 ` [PATCH 03/44] RISC-V: Reorder comment on SFB patterns Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 04/44] RISC-V: Sanitise NEED_EQ_NE_P case with `riscv_emit_int_compare' Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 05/44] RISC-V: Fix `mode' usage in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 5:54 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 06/44] RISC-V: Avoid repeated GET_MODE calls " Maciej W. Rozycki
2023-11-19 5:55 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 07/44] RISC-V: Use `nullptr' " Maciej W. Rozycki
2023-11-19 5:53 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 08/44] RISC-V: Simplify EQ vs NE selection " Maciej W. Rozycki
2023-11-19 5:56 ` Kito Cheng
2023-11-19 5:36 ` [PATCH 09/44] RISC-V: Rework branch costing model for if-conversion Maciej W. Rozycki
2023-11-19 18:52 ` Jeff Law
2023-11-23 18:34 ` Maciej W. Rozycki
2023-11-29 1:19 ` Jeff Law
2023-11-29 12:01 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 10/44] RISC-V/testsuite: Add branched cases for integer cond-move operations Maciej W. Rozycki
2023-11-19 6:44 ` Kito Cheng
2023-11-19 5:37 ` [PATCH 11/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 6:47 ` Kito Cheng
2023-11-23 19:18 ` Maciej W. Rozycki
2023-11-19 5:37 ` [PATCH 12/44] RISC-V/testsuite: Add branched cases for FP " Maciej W. Rozycki
2023-11-19 6:48 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 14/44] RISC-V: Also invert the cond-move condition for GEU and LEU Maciej W. Rozycki
2023-11-19 6:50 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 15/44] RISC-V/testsuite: Add branched cases for GEU and LEU cond-move operations Maciej W. Rozycki
2023-11-19 17:42 ` Jeff Law
2023-11-19 5:38 ` [PATCH 16/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 7:22 ` Kito Cheng
2023-11-19 5:38 ` [PATCH 17/44] RISC-V: Avoid extraneous EQ or NE operation in cond-move expansion Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:38 ` [PATCH 18/44] RISC-V/testsuite: Add branched cases for equality cond-move operations Maciej W. Rozycki
2023-11-19 17:45 ` Jeff Law
2023-11-19 5:39 ` [PATCH 19/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:46 ` Jeff Law
2023-11-19 5:39 ` [PATCH 20/44] RISC-V: Also accept constants for T-Head cond-move comparison operands Maciej W. Rozycki
2023-11-19 17:48 ` Jeff Law
2023-11-19 5:39 ` [PATCH 21/44] RISC-V: Also accept constants for T-Head cond-move data input operands Maciej W. Rozycki
2023-11-19 17:50 ` Jeff Law
2023-11-19 5:40 ` [PATCH 22/44] RISC-V: Fold all the cond-move variants together Maciej W. Rozycki
2023-11-19 18:35 ` Jeff Law
2023-11-19 5:40 ` [PATCH 23/44] RISC-V/testsuite: Add branched cases for T-Head non-equality cond moves Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 24/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 25/44] RISC-V: Implement `riscv_emit_unary' helper Maciej W. Rozycki
2023-11-19 17:54 ` Jeff Law
2023-11-19 5:40 ` [PATCH 26/44] RISC-V: Add `movMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-23 22:16 ` Maciej W. Rozycki
2023-11-19 5:40 ` [PATCH 27/44] RISC-V/testsuite: Add branched cases for generic integer cond moves Maciej W. Rozycki
2023-11-19 18:18 ` Jeff Law
2023-11-19 5:41 ` [PATCH 28/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:19 ` Jeff Law
2023-11-19 5:41 ` [PATCH 29/44] RISC-V: Add `addMODEcc' implementation for generic targets Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-23 22:36 ` Maciej W. Rozycki
2023-11-19 5:41 ` [PATCH 30/44] RISC-V/testsuite: Add branched cases for generic integer cond adds Maciej W. Rozycki
2023-11-19 18:23 ` Jeff Law
2023-11-19 5:41 ` [PATCH 31/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 18:25 ` Jeff Law
2023-11-23 22:48 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 32/44] RISC-V: Only use SUBREG if applicable in `riscv_expand_float_scc' Maciej W. Rozycki
2023-11-19 18:26 ` Jeff Law
2023-11-19 5:42 ` [PATCH 33/44] RISC-V: Also allow FP conditions in `riscv_expand_conditional_move' Maciej W. Rozycki
2023-11-19 18:30 ` Jeff Law
2023-11-23 22:55 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 34/44] RISC-V: Provide FP conditional-branch instructions for if-conversion Maciej W. Rozycki
2023-11-19 19:42 ` Jeff Law
2023-11-23 23:26 ` Maciej W. Rozycki
2023-11-19 5:42 ` [PATCH 35/44] RISC-V: Avoid extraneous integer comparison for FP comparisons Maciej W. Rozycki
2023-11-19 19:44 ` Jeff Law
2023-11-19 5:42 ` [PATCH 36/44] RISC-V/testsuite: Add branched cases for generic FP cond moves Maciej W. Rozycki
2023-11-19 19:45 ` Jeff Law
2023-11-19 5:43 ` [PATCH 37/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 38/44] RISC-V/testsuite: Add branched cases for generic FP cond adds Maciej W. Rozycki
2023-11-19 19:46 ` Jeff Law
2023-11-19 5:43 ` [PATCH 39/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 19:47 ` Jeff Law
2023-11-19 5:43 ` Maciej W. Rozycki [this message]
2023-11-19 19:51 ` [PATCH 40/44] RISC-V: Handle FP NE operator via inversion in cond-operation expansion Jeff Law
2023-11-22 1:37 ` Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 41/44] RISC-V/testsuite: Add branched cases for FP NE cond-move operations Maciej W. Rozycki
2023-11-19 5:43 ` [PATCH 42/44] " Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 43/44] RISC-V/testsuite: Add branched cases for FP NE cond-add operation Maciej W. Rozycki
2023-11-19 5:44 ` [PATCH 44/44] RISC-V/testsuite: Add branchless " Maciej W. Rozycki
2023-11-19 5:52 ` [PATCH 00/44] RISC-V: Various if-conversion fixes and improvements Kito Cheng
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