From: Manolis Tsamis <manolis.tsamis@vrull.eu>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: Richard Biener <richard.guenther@gmail.com>, gcc-patches@gcc.gnu.org
Subject: Re: [PATCH 1/2] Implementation of new RISCV optimizations pass: fold-mem-offsets.
Date: Wed, 31 May 2023 15:19:05 +0300 [thread overview]
Message-ID: <CAM3yNXpGE=Xrfmkg+4py5Ab=C8m67LoS32cfJqkk+_20CwE_BA@mail.gmail.com> (raw)
In-Reply-To: <f807f7d9-825f-f5f9-0e68-788ef4354d14@gmail.com>
On Tue, May 30, 2023 at 2:30 AM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 5/25/23 08:02, Manolis Tsamis wrote:
> > On Thu, May 25, 2023 at 4:53 PM Richard Biener via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> >>
> >> On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches
> >> <gcc-patches@gcc.gnu.org> wrote:
> >>>
> >>>
> >>>
> >>> On 5/25/23 07:01, Richard Biener via Gcc-patches wrote:
> >>>> On Thu, May 25, 2023 at 2:36 PM Manolis Tsamis <manolis.tsamis@vrull.eu> wrote:
> >>>>>
> >>>>> Implementation of the new RISC-V optimization pass for memory offset
> >>>>> calculations, documentation and testcases.
> >>>>
> >>>> Why do fwprop or combine not what you want to do?
> >>> I think a lot of them end up coming from register elimination.
> >>
> >> Why isn't this a problem for other targets then? Or maybe it is and this
> >> shouldn't be a machine specific pass? Maybe postreload-gcse should
> >> perform strength reduction (I can't think of any other post reload pass
> >> that would do something even remotely related).
> >>
> >> Richard.
> >>
> >
> > It should be a problem for other targets as well (especially RISC-style ISAs).
> >
> > It can be easily seen by comparing the generated code for the
> > testcases: Example for testcase-2 on AArch64:
> > https://godbolt.org/z/GMT1K7Ebr
> > Although the patterns in the test cases are the ones that are simple
> > as the complex ones manifest in complex programs, the case still
> > holds.
> > The code for this pass is quite generic and could work for most/all
> > targets if that would be interesting.
> Interestly enough, fold-mem-offsets seems to interact strangely with the
> load/store pair support on aarch64. Note show store2a uses 2 stp
> instructions on the trunk, but 4 str instructions with fold-mem-offsets.
> Yet in load1r we're able to generate a load-quad rather than two load
> pairs. Weird.
>
I'm confused, where is this comparison from?
The fold-mem-offsets pass is only run on RISCV and doesn't (shouldn't)
affect AArch64.
I only see the 2x stp / 4x str in the godbolt link, but that is gcc vs
clang, no fold-mem-offsets involved here.
Manolis
> jeff
next prev parent reply other threads:[~2023-05-31 12:19 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-25 12:35 [PATCH 0/2] RISC-V: New pass to optimize calculation of offsets for memory operations Manolis Tsamis
2023-05-25 12:35 ` [PATCH 1/2] Implementation of new RISCV optimizations pass: fold-mem-offsets Manolis Tsamis
2023-05-25 13:01 ` Richard Biener
2023-05-25 13:25 ` Manolis Tsamis
2023-05-25 13:31 ` Jeff Law
2023-05-25 13:50 ` Richard Biener
2023-05-25 14:02 ` Manolis Tsamis
2023-05-29 23:30 ` Jeff Law
2023-05-31 12:19 ` Manolis Tsamis [this message]
2023-05-31 14:00 ` Jeff Law
2023-05-25 14:13 ` Jeff Law
2023-05-25 14:18 ` Philipp Tomsich
2023-06-08 5:37 ` Jeff Law
2023-06-12 7:36 ` Manolis Tsamis
2023-06-12 14:37 ` Jeff Law
2023-06-09 0:57 ` Jeff Law
2023-06-12 7:32 ` Manolis Tsamis
2023-06-12 21:58 ` Jeff Law
2023-06-15 17:34 ` Manolis Tsamis
2023-06-10 15:49 ` Jeff Law
2023-06-12 7:41 ` Manolis Tsamis
2023-06-12 21:36 ` Jeff Law
2023-05-25 12:35 ` [PATCH 2/2] cprop_hardreg: Enable propagation of the stack pointer if possible Manolis Tsamis
2023-05-25 13:38 ` Jeff Law
2023-05-31 12:15 ` Manolis Tsamis
2023-06-07 22:16 ` Jeff Law
2023-06-07 22:18 ` Jeff Law
2023-06-08 6:15 ` Manolis Tsamis
2023-06-15 20:13 ` Philipp Tomsich
2023-06-19 16:57 ` Thiago Jung Bauermann
2023-06-19 17:07 ` Manolis Tsamis
2023-06-19 23:40 ` Andrew Pinski
2023-06-19 23:48 ` Andrew Pinski
2023-06-20 2:16 ` Jeff Law
2023-06-20 4:52 ` Tamar Christina
2023-06-20 5:00 ` Jeff Law
2023-06-21 23:42 ` Thiago Jung Bauermann
2023-06-22 7:37 ` Richard Biener
2023-06-22 7:58 ` Philipp Tomsich
2023-05-25 13:42 ` [PATCH 0/2] RISC-V: New pass to optimize calculation of offsets for memory operations Jeff Law
2023-05-25 13:57 ` Manolis Tsamis
2023-06-15 15:04 ` Jeff Law
2023-06-15 15:30 ` Manolis Tsamis
2023-06-15 15:56 ` Jeff Law
2023-06-18 18:11 ` Jeff Law
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