From: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
To: Andrea Corallo <Andrea.Corallo@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,
Andrea Corallo <Andrea.Corallo@arm.com>
Subject: RE: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
Date: Fri, 28 Apr 2023 16:27:37 +0000 [thread overview]
Message-ID: <PAXPR08MB69263BDF3F404443E8483C51936B9@PAXPR08MB6926.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <20230428113002.482343-2-andrea.corallo@arm.com>
> -----Original Message-----
> From: Andrea Corallo <andrea.corallo@arm.com>
> Sent: Friday, April 28, 2023 12:30 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>; Andrea Corallo <Andrea.Corallo@arm.com>
> Subject: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite
>
> Hi all,
>
> this patch fixes the vstrwq* MVE instrinsics failing to emit the
> correct sequence of instruction due to a missing predicates. Also the
> immediate range is fixed to be multiples of 2 up between [-252, 252].
>
Ok.
Thanks,
Kyrill
> Best Regards
>
> Andrea
>
> gcc/ChangeLog:
>
> * config/arm/constraints.md (mve_vldrd_immediate): Move it to
> predicates.md.
> (Ri): Move constraint definition from predicates.md.
> (Rl): Define new constraint.
> * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si):
> Add
> missing constraint.
> (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
> for op 1, use mve_vstrw_immediate predicate and Rl constraint for
> op 2. Fix asm output spacing.
> (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing
> constraint.
> * config/arm/predicates.md (Ri) Move constraint to constraints.md
> (mve_vldrd_immediate): Move it from
> constraints.md.
> (mve_vstrw_immediate): New predicate.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use
> check-function-bodies instead of scan-assembler checks. Use
> extern "C" for C++ testing.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c:
> Likewise.
> *
> gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c:
> Likewise.
> * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise.
> ---
> gcc/config/arm/constraints.md | 20 ++++++++--
> gcc/config/arm/mve.md | 10 ++---
> gcc/config/arm/predicates.md | 14 +++----
> .../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++---
> .../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++---
> .../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++--
> .../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++--
> .../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++--
> .../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++--
> .../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++---
> .../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++---
> .../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++---
> .../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++---
> .../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++---
> 33 files changed, 922 insertions(+), 178 deletions(-)
>
> diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
> index 504cd938b26..05a4ebbdd67 100644
> --- a/gcc/config/arm/constraints.md
> +++ b/gcc/config/arm/constraints.md
> @@ -102,10 +102,6 @@ (define_constraint "Rg"
> (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2)
> || (ival == 4) || (ival == 8))")))
>
> -;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
> -(define_predicate "mve_vldrd_immediate"
> - (match_test "satisfies_constraint_Ri (op)"))
> -
> (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
> "The VFP registers @code{s0}-@code{s31}.")
>
> @@ -574,6 +570,22 @@ (define_constraint "US"
> (match_code "symbol_ref")
> )
>
> +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
> +(define_constraint "Ri"
> + "@internal In Thumb-2 state a constant is multiple of 8 and in range
> + of -/+ 1016 for MVE"
> + (and (match_code "const_int")
> + (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
> + && ((ival % 8) == 0)")))
> +
> +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
> +(define_constraint "Rl"
> + "@internal In Thumb-2 state a constant is multiple of 2 and in range
> + of -/+ 252 for MVE"
> + (and (match_code "const_int")
> + (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252)
> + && ((ival % 2) == 0)")))
> +
> (define_memory_constraint "Uz"
> "@internal
> A memory access that is accessible as an LDC/STC operand"
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 35eab6c94bf..161794e470c 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -9359,7 +9359,7 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_<supf>v4si"
> [(match_operand:V4SI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V4SI 3 "s_register_operand" "w")
> - (match_operand:V4BI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSTRWSBWBQ))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9408,9 +9408,9 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_fv4sf"
> [(set (mem:BLK (scratch))
> (unspec:BLK
> [(match_operand:V4SI 1 "s_register_operand" "0")
> - (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> + (match_operand:SI 2 "mve_vstrw_immediate" "Rl")
> (match_operand:V4SF 3 "s_register_operand" "w")
> - (match_operand:V4BI 4 "vpr_register_operand")]
> + (match_operand:V4BI 4 "vpr_register_operand" "Up")]
> VSTRWQSBWB_F))
> (set (match_operand:V4SI 0 "s_register_operand" "=w")
> (unspec:V4SI [(match_dup 1) (match_dup 2)]
> @@ -9422,7 +9422,7 @@ (define_insn
> "mve_vstrwq_scatter_base_wb_p_fv4sf"
> ops[0] = operands[1];
> ops[1] = operands[2];
> ops[2] = operands[3];
> - output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops);
> + output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops);
> return "";
> }
> [(set_attr "length" "8")])
> @@ -9461,7 +9461,7 @@ (define_insn
> "mve_vstrdq_scatter_base_wb_p_<supf>v2di"
> [(match_operand:V2DI 1 "s_register_operand" "0")
> (match_operand:SI 2 "mve_vldrd_immediate" "Ri")
> (match_operand:V2DI 3 "s_register_operand" "w")
> - (match_operand:V2QI 4 "vpr_register_operand")]
> + (match_operand:V2QI 4 "vpr_register_operand" "Up")]
> VSTRDSBWBQ))
> (set (match_operand:V2DI 0 "s_register_operand" "=w")
> (unspec:V2DI [(match_dup 1) (match_dup 2)]
> diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
> index 3139750c606..00995a590ab 100644
> --- a/gcc/config/arm/predicates.md
> +++ b/gcc/config/arm/predicates.md
> @@ -73,13 +73,13 @@ (define_predicate "mve_imm_32"
> (define_predicate "mve_imm_selective_upto_8"
> (match_test "satisfies_constraint_Rg (op)"))
>
> -;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE.
> -(define_constraint "Ri"
> - "@internal In Thumb-2 state a constant is multiple of 8 and in range
> - of -/+ 1016 for MVE"
> - (and (match_code "const_int")
> - (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016)
> - && ((ival % 8) == 0)")))
> +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE.
> +(define_predicate "mve_vldrd_immediate"
> + (match_test "satisfies_constraint_Ri (op)"))
> +
> +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE.
> +(define_predicate "mve_vstrw_immediate"
> + (match_test "satisfies_constraint_Rl (op)"))
>
> ; Predicate for stack protector guard's address in
> ; stack_protect_combined_set_insn and stack_protect_combined_test_insn
> patterns
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> index 8aa04fcbdee..e92ecb0f6bc 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4_t value)
> +foo (float32_t *base, float32x4_t value)
> {
> - vstrwq_f32 (addr, value);
> + return vstrwq_f32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4_t value)
> +foo1 (float32_t *base, float32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> index 411de6414f7..f1992a67736 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * addr, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_f32 (addr, value, p);
> + return vstrwq_p_f32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> index 3b042814d27..a00aeabb9fe 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_s32 (addr, value, p);
> + return vstrwq_p_s32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> index b9e92204c88..05fded8aac8 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p_u32 (addr, value, p);
> + return vstrwq_p_u32 (base, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_p (addr, value, p);
> + return vstrwq_p (base, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> index c7b3d91a972..b2a184f3c66 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * addr, int32x4_t value)
> +foo (int32_t *base, int32x4_t value)
> {
> - vstrwq_s32 (addr, value);
> + return vstrwq_s32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * addr, int32x4_t value)
> +foo1 (int32_t *base, int32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> index f8b56917295..c80e8d9cdc5 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, float32x4_t value)
> {
> - vstrwq_scatter_base_f32 (addr, 8, value);
> + return vstrwq_scatter_base_f32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, float32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> index 4a75e6503e1..237843c0661 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_f32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_f32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> index 5ac4f300a7d..5f4f4a09664 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_s32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_s32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> index e564f26b9c7..8c5cf63f861 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p_u32 (addr, 8, value, p);
> + return vstrwq_scatter_base_p_u32 (addr, 0, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_p (addr, 8, value, p);
> + return vstrwq_scatter_base_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> index 5bba36db5cb..5208cf4f808 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, int32x4_t value)
> {
> - vstrwq_scatter_base_s32 (addr, 8, value);
> + return vstrwq_scatter_base_s32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, int32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> index 1dcbb5a739c..e728db2b9f1 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo (uint32x4_t addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_u32 (addr, 8, value);
> + return vstrwq_scatter_base_u32 (addr, 0, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> foo1 (uint32x4_t addr, uint32x4_t value)
> {
> - vstrwq_scatter_base (addr, 8, value);
> + return vstrwq_scatter_base (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.u32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> index b2cc6e555ae..e481191aa57 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, float32x4_t value)
> +foo (uint32x4_t *addr, float32x4_t value)
> {
> - vstrwq_scatter_base_wb_f32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_f32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, float32x4_t value)
> +foo1 (uint32x4_t *addr, float32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> index 4befd49d7b9..8d217d46230 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32
> .c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
> #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> index dfb1827c4f0..afc47adcd7f 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32
> .c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
> #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> index 4eb78c600be..65191c2f1ed 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u3
> 2.c
> @@ -1,19 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_base_wb_p (addr, 8, value, p);
> + return vstrwq_scatter_base_wb_p (addr, 0, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+,
> #\[0-9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> index 618dbaf5aa6..b6a9f6cd1f4 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, const int offset, int32x4_t value)
> +foo (uint32x4_t *addr, int32x4_t value)
> {
> - vstrwq_scatter_base_wb_s32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_s32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, const int offset, int32x4_t value)
> +foo1 (uint32x4_t *addr, int32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> index 912a4590cf5..81a278f4e2b 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c
> @@ -1,19 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32x4_t * addr, uint32x4_t value)
> +foo (uint32x4_t *addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_wb_u32 (addr, 8, value);
> + return vstrwq_scatter_base_wb_u32 (addr, 0, value);
> }
>
> +
> +/*
> +**foo1:
> +** ...
> +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32x4_t * addr, uint32x4_t value)
> +foo1 (uint32x4_t *addr, uint32x4_t value)
> {
> - vstrwq_scatter_base_wb (addr, 8, value);
> + return vstrwq_scatter_base_wb (addr, 0, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-
> 9\]+\\\]!" 2 } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> index c14d3ce607b..b81df68aa21 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_offset_f32 (base, offset, value);
> + return vstrwq_scatter_offset_f32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> index 115be56ec00..8aee42f76a3 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_f32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_f32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> index 48652af3cff..9c74ae7a8d8 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_s32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> index dcd42ec453f..015a202b548 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p_u32 (base, offset, value, p);
> + return vstrwq_scatter_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_offset_p (base, offset, value, p);
> + return vstrwq_scatter_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> index 04672e5a4aa..df373111b78 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_offset_s32 (base, offset, value);
> + return vstrwq_scatter_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> index e3d312550c6..a74696ca273 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_offset_u32 (base, offset, value);
> + return vstrwq_scatter_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_offset (base, offset, value);
> + return vstrwq_scatter_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> index b20c4c7ed3a..1c9b29a57b8 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_f32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_f32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _f32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_f32.c
> index 1682f702dc6..08e1572854e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _f32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_f32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
> /* { dg-add-options arm_v8_1m_mve_fp } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _s32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_s32.c
> index eef6ea6e196..2b8f8a7d61f 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _s32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_s32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_u32.c
> index b11e7e04dc4..3e4e87bf79a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p
> _u32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> p_u32.c
> @@ -1,21 +1,49 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p);
> }
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|)
> +** ...
> +** vpst(?: @.*|)
> +** ...
> +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p)
> {
> - vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> + return vstrwq_scatter_shifted_offset_p (base, offset, value, p);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrwt.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> index 8ac25c47554..7f25490a69a 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s
> 32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_s32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_s32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value)
> +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u
> 32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> u32.c
> index 1ce0ddacc7a..a96220c4f6e 100644
> ---
> a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u
> 32.c
> +++
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_
> u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_shifted_offset_u32 (base, offset, value);
> + return vstrwq_scatter_shifted_offset_u32 (base, offset, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?:
> @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value)
> {
> - vstrwq_scatter_shifted_offset (base, offset, value);
> + return vstrwq_scatter_shifted_offset (base, offset, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> index 4aec9935b84..df554af79a6 100644
> --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c
> @@ -1,21 +1,41 @@
> /* { dg-require-effective-target arm_v8_1m_mve_ok } */
> /* { dg-add-options arm_v8_1m_mve } */
> /* { dg-additional-options "-O2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
>
> #include "arm_mve.h"
>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/*
> +**foo:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo (uint32_t * addr, uint32x4_t value)
> +foo (uint32_t *base, uint32x4_t value)
> {
> - vstrwq_u32 (addr, value);
> + return vstrwq_u32 (base, value);
> }
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
>
> +/*
> +**foo1:
> +** ...
> +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|)
> +** ...
> +*/
> void
> -foo1 (uint32_t * addr, uint32x4_t value)
> +foo1 (uint32_t *base, uint32x4_t value)
> {
> - vstrwq (addr, value);
> + return vstrwq (base, value);
> +}
> +
> +#ifdef __cplusplus
> }
> +#endif
>
> -/* { dg-final { scan-assembler "vstrw.32" } } */
> +/* { dg-final { scan-assembler-not "__ARM_undef" } } */
> --
> 2.25.1
next prev parent reply other threads:[~2023-04-28 16:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 11:29 [PATCH 01/10] arm: Mve testsuite improvements Andrea Corallo
2023-04-28 11:29 ` [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Andrea Corallo
2023-04-28 16:27 ` Kyrylo Tkachov [this message]
2023-05-02 8:21 ` Christophe Lyon
2023-05-02 8:45 ` Andrea Corallo
2023-05-02 10:18 ` Andrea Corallo
2023-04-28 11:29 ` [PATCH 03/10] arm: Mve backend + testsuite fixes 2 Andrea Corallo
2023-04-28 16:40 ` Kyrylo Tkachov
2023-05-02 11:53 ` Andrea Corallo
2023-04-28 11:29 ` [PATCH 04/10] arm: Stop vadcq, vsbcq intrinsics from overwriting the FPSCR NZ flags Andrea Corallo
2023-04-28 16:45 ` Kyrylo Tkachov
2023-05-03 12:19 ` Stamatis Markianos-Wright
2023-05-03 12:55 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 05/10] arm: Add vorrq_n overloading into vorrq _Generic Andrea Corallo
2023-04-28 16:47 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 06/10] arm: Fix overloading of MVE scalar constant parameters on vbicq, vmvnq_m Andrea Corallo
2023-04-28 16:47 ` Kyrylo Tkachov
2023-04-28 11:29 ` [PATCH 07/10] arm: Fix MVE header pointer overloads this time (and a bit more tidying) Andrea Corallo
2023-04-28 16:51 ` Kyrylo Tkachov
2023-04-28 11:30 ` [PATCH 08/10] arm testsuite: Remove reduntant tests Andrea Corallo
2023-04-28 16:52 ` Kyrylo Tkachov
2023-04-28 11:30 ` [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests Andrea Corallo
2023-04-28 16:54 ` Kyrylo Tkachov
2023-05-02 12:17 ` Stamatis Markianos-Wright
2023-05-02 8:28 ` Christophe Lyon
2023-05-02 9:33 ` Stamatis Markianos-Wright
2023-04-28 11:30 ` [PATCH 10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes Andrea Corallo
2023-04-28 16:58 ` Kyrylo Tkachov
2023-05-03 12:34 ` Stamatis Markianos-Wright
2023-05-03 12:56 ` Kyrylo Tkachov
2023-04-28 16:27 ` [PATCH 01/10] arm: Mve testsuite improvements Kyrylo Tkachov
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as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).