[PATCH v2 1/5] sim: Allow toggling of quiet NaN-bit semantics

[Faraz Shahbazker <fshahbazker@wavecomp.com>]

IEEE754-1985 specifies the top bit of the mantissa as an indicator
of signalling vs. quiet NaN, but does not define the precise semantics.
Most architectures treat this bit as indicating quiet NaN, but legacy
(pre-R6) MIPS goes the other way and treats it as signalling NaN.

This used to be controlled by a macro that was only defined for MIPS.
This patch replaces the macro with a variable to track the current
semantics of the NaN bit and allows differentiation between older
(pre-R6) and and newer MIPS cores.

2021-05-24  Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/common/ChangeLog:
	* sim-fpu.c (sim_fpu_quiet_nan_inverted): New.
	(pack_fpu, unpack_fpu): Allow reversal of quiet NaN semantics.
	* sim-fpu.h (sim_fpu_quiet_nan_inverted): New extern.

sim/mips/ChangeLog:
	* cp1.h (fcsr_NAN2008_mask, fcsr_NAN2008_shift): New.
	* mips.igen (check_fpu): Select default quiet NaN mode
	for legacy MIPS.
	* sim-main.h (SIM_QUIET_NAN_NEGATED): Remove.
---

Notes:
    Changes from v1:
      Use bool/true/false for sim_fpu_quiet_nan_inverted flag.
      White space changes

 sim/common/sim-fpu.c | 35 ++++++++++++++++++++---------------
 sim/common/sim-fpu.h |  2 ++
 sim/mips/cp1.h       |  4 ++++
 sim/mips/mips.igen   |  3 +++
 sim/mips/sim-main.h  |  3 ---
 5 files changed, 29 insertions(+), 18 deletions(-)

diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index fe8ecf8a3ce..4edd651fd52 100644
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -198,11 +198,10 @@ pack_fpu (const sim_fpu *src,
       /* Force fraction to correct class.  */
       fraction = src->fraction;
       fraction >>= NR_GUARDS;
-#ifdef SIM_QUIET_NAN_NEGATED
-      fraction |= QUIET_NAN - 1;
-#else
-      fraction |= QUIET_NAN;
-#endif
+      if (sim_fpu_quiet_nan_inverted)
+	fraction |= QUIET_NAN - 1;
+      else
+	fraction |= QUIET_NAN;
       break;
     case sim_fpu_class_snan:
       sign = src->sign;
@@ -210,11 +209,10 @@ pack_fpu (const sim_fpu *src,
       /* Force fraction to correct class.  */
       fraction = src->fraction;
       fraction >>= NR_GUARDS;
-#ifdef SIM_QUIET_NAN_NEGATED
-      fraction |= QUIET_NAN;
-#else
-      fraction &= ~QUIET_NAN;
-#endif
+      if (sim_fpu_quiet_nan_inverted)
+        fraction |= QUIET_NAN;
+      else
+	fraction &= ~QUIET_NAN;
       break;
     case sim_fpu_class_infinity:
       sign = src->sign;
@@ -372,11 +370,10 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_double)
 	  /* Non zero fraction, means NaN.  */
 	  dst->sign = sign;
 	  dst->fraction = (fraction << NR_GUARDS);
-#ifdef SIM_QUIET_NAN_NEGATED
-	  qnan = (fraction & QUIET_NAN) == 0;
-#else
-	  qnan = fraction >= QUIET_NAN;
-#endif
+	  if (sim_fpu_quiet_nan_inverted)
+	    qnan = (fraction & QUIET_NAN) == 0;
+	  else
+	    qnan = fraction >= QUIET_NAN;
 	  if (qnan)
 	    dst->class = sim_fpu_class_qnan;
 	  else
@@ -2530,6 +2527,14 @@ const sim_fpu sim_fpu_max32 = {
 const sim_fpu sim_fpu_max64 = {
   sim_fpu_class_number, 0, LSMASK64 (NR_FRAC_GUARD, NR_GUARDS64), NORMAL_EXPMAX64
 };
+
+/* IEEE 754-1985 specifies the top bit of the mantissa as an indicator
+   of signalling vs. quiet NaN, but does not specify the semantics.
+   Most architectures treat this bit as quiet NaN, but legacy (pre-R6)
+   MIPS goes the other way and treats it as signalling.  This variable
+   tracks the current semantics of the NaN bit and allows differentiation
+   between pre-R6 and R6 MIPS cores.  */
+bool sim_fpu_quiet_nan_inverted = false;
 #endif
 
 
diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h
index 89e6de7e35f..51bb7d2be92 100644
--- a/sim/common/sim-fpu.h
+++ b/sim/common/sim-fpu.h
@@ -375,7 +375,9 @@ enum {
 INLINE_SIM_FPU (int) sim_fpu_is (const sim_fpu *l);
 INLINE_SIM_FPU (int) sim_fpu_cmp (const sim_fpu *l, const sim_fpu *r);
 
+/* Toggle quiet NaN semantics.  */
 
+extern bool sim_fpu_quiet_nan_inverted;
 
 /* A number of useful constants.  */
 
diff --git a/sim/mips/cp1.h b/sim/mips/cp1.h
index 3a78bf4c6b3..0babdc28eca 100644
--- a/sim/mips/cp1.h
+++ b/sim/mips/cp1.h
@@ -40,6 +40,10 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 #define fcsr_RM_mask       (0x00000003)
 #define fcsr_RM_shift      (0)
 
+/* FCSR bits for IEEE754-2008 compliance.  */
+#define fcsr_NAN2008_mask       (0x00040000)
+#define fcsr_NAN2008_shift      (18)
+
 #define fenr_FS            (0x00000004)
 
 /* Macros to update and retrieve the FCSR condition-code bits.  This
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 522cad6fe45..160ca2a8c45 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -5050,6 +5050,9 @@
 {
   if (! COP_Usable (1))
     SignalExceptionCoProcessorUnusable (1);
+
+  FCSR &= ~fcsr_NAN2008_mask;
+  sim_fpu_quiet_nan_inverted = true;
 }
 
 
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 8c9abfa0b0b..e8531405ebc 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -20,9 +20,6 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 #ifndef SIM_MAIN_H
 #define SIM_MAIN_H
 
-/* MIPS uses an unusual format for floating point quiet NaNs.  */
-#define SIM_QUIET_NAN_NEGATED
-
 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
 
-- 
2.25.1