From: Dragan Mladjenovic <Dragan.Mladjenovic@syrmia.com>
To: gdb-patches@sourceware.org
Cc: Mike Frysinger <vapier@gentoo.org>,
"Maciej W . Rozycki" <macro@orcam.me.uk>,
Chao-ying Fu <cfu@wavecomp.com>,
Faraz Shahbazker <fshahbazker@wavecomp.com>
Subject: [PATCH v5 2/4] sim: Factor out NaN handling in floating point operations
Date: Wed, 2 Feb 2022 11:17:23 +0100 [thread overview]
Message-ID: <20220202101725.23671-3-Dragan.Mladjenovic@syrmia.com> (raw)
In-Reply-To: <20220202101725.23671-1-Dragan.Mladjenovic@syrmia.com>
From: Faraz Shahbazker <fshahbazker@wavecomp.com>
2022-02-01 Faraz Shahbazker <fshahbazker@wavecomp.com>
sim/common/ChangeLog:
* sim-fpu.c (sim_fpu_op_nan): New.
(sim_fpu_add): Factor out NaN operand handling with
a call to sim_fpu_op_nan.
(sim_fpu_sub, sim_fpu_mul, sim_fpu_div): Likewise.
(sim_fpu_rem, sim_fpu_max, sim_fpu_min): Likewise.
* sim-fpu.h (sim_fpu_op_nan): New declaration.
---
sim/common/sim-fpu.c | 189 +++++++------------------------------------
sim/common/sim-fpu.h | 10 +++
2 files changed, 41 insertions(+), 158 deletions(-)
diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index 276ad234174..9174eaf17b4 100644
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -986,7 +986,24 @@ sim_fpu_round_64 (sim_fpu *f,
return do_round (f, 1, round, denorm);
}
+/* NaN handling for binary operations. */
+INLINE_SIM_FPU (int)
+sim_fpu_op_nan (sim_fpu *f, const sim_fpu *l, const sim_fpu *r)
+{
+ if (sim_fpu_is_snan (l) || sim_fpu_is_snan (r))
+ {
+ *f = sim_fpu_is_snan (l) ? *l : *r;
+ f->class = sim_fpu_class_qnan;
+ return sim_fpu_status_invalid_snan;
+ }
+ ASSERT (sim_fpu_is_nan (l) || sim_fpu_is_nan (r));
+ if (sim_fpu_is_qnan (l))
+ *f = *l;
+ else /* if (sim_fpu_is_qnan (r)) */
+ *f = *r;
+ return 0;
+}
/* Arithmetic ops */
@@ -995,28 +1012,8 @@ sim_fpu_add (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r)
@@ -1144,28 +1141,8 @@ sim_fpu_sub (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r)
@@ -1298,28 +1275,8 @@ sim_fpu_mul (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_zero (r))
@@ -1423,30 +1380,8 @@ sim_fpu_div (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r))
@@ -1556,30 +1491,8 @@ sim_fpu_rem (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
*f = sim_fpu_qnan;
@@ -1639,28 +1552,8 @@ sim_fpu_max (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r)
@@ -1722,28 +1615,8 @@ sim_fpu_min (sim_fpu *f,
const sim_fpu *l,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (l))
- {
- *f = *l;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_snan (r))
- {
- *f = *r;
- f->class = sim_fpu_class_qnan;
- return sim_fpu_status_invalid_snan;
- }
- if (sim_fpu_is_qnan (l))
- {
- *f = *l;
- return 0;
- }
- if (sim_fpu_is_qnan (r))
- {
- *f = *r;
- return 0;
- }
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ return sim_fpu_op_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r)
diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h
index b0b318cb283..2a141981687 100644
--- a/sim/common/sim-fpu.h
+++ b/sim/common/sim-fpu.h
@@ -261,6 +261,16 @@ INLINE_SIM_FPU (int) sim_fpu_sqrt (sim_fpu *f,
+/* NaN handling.
+
+ Assuming that at least one of the inputs is NAN choose the correct
+ NAN result for the binary operation. */
+
+INLINE_SIM_FPU (int) sim_fpu_op_nan (sim_fpu *f,
+ const sim_fpu *l, const sim_fpu *r);
+
+
+
/* Conversion of integer <-> floating point. */
INLINE_SIM_FPU (int) sim_fpu_i32to (sim_fpu *f, int32_t i,
--
2.17.1
next prev parent reply other threads:[~2022-02-02 10:17 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 7:45 [PATCH 0/5] Add support for MIPS32/64 revision 6 Faraz Shahbazker
2021-05-20 7:45 ` [PATCH 1/5] sim: Allow toggling of quiet NaN-bit semantics Faraz Shahbazker
2021-05-22 1:16 ` Mike Frysinger
2021-05-20 7:45 ` [PATCH 2/5] sim: Factor out NaN handling in floating point operations Faraz Shahbazker
2021-05-22 1:25 ` Mike Frysinger
2021-05-23 6:32 ` [EXTERNAL]Re: " Faraz Shahbazker
2021-05-24 1:26 ` Mike Frysinger
2021-05-20 7:45 ` [PATCH 3/5] sim: Add partial support for IEEE 754-2008 Faraz Shahbazker
2021-05-22 1:34 ` Mike Frysinger
2021-05-20 7:45 ` [PATCH 4/5] sim: mips: Add simulator support for mips32r6/mips64r6 Faraz Shahbazker
2021-05-22 1:46 ` Mike Frysinger
2021-05-22 6:20 ` Eli Zaretskii
2021-06-27 19:25 ` [EXTERNAL]Re: " Faraz Shahbazker
2021-06-27 19:33 ` Simon Marchi
2021-06-27 19:44 ` Eli Zaretskii
2021-06-27 20:24 ` Faraz Shahbazker
2021-06-28 12:17 ` Eli Zaretskii
2021-07-02 10:10 ` Faraz Shahbazker
2021-12-24 18:42 ` Mike Frysinger
2021-06-28 1:16 ` Mike Frysinger
2021-05-22 6:44 ` Faraz Shahbazker
2021-05-24 17:57 ` [PATCH v2 0/5] Add support for MIPS32/64 revision 6 Faraz Shahbazker
2021-05-24 17:57 ` [PATCH v2 1/5] sim: Allow toggling of quiet NaN-bit semantics Faraz Shahbazker
2021-05-24 17:57 ` [PATCH v2 2/5] sim: Factor out NaN handling in floating point operations Faraz Shahbazker
2021-05-24 17:58 ` [PATCH v2 3/5] sim: Add partial support for IEEE 754-2008 Faraz Shahbazker
2021-05-24 17:58 ` [PATCH v2 4/5] sim: mips: Add simulator support for mips32r6/mips64r6 Faraz Shahbazker
2021-05-24 17:58 ` [PATCH v2 5/5] gdb: mips: Add MIPSR6 support Faraz Shahbazker
2021-05-29 1:53 ` Simon Marchi
2021-06-27 19:10 ` [PATCH v3 " Faraz Shahbazker
2021-05-20 7:45 ` [PATCH " Faraz Shahbazker
2022-02-02 10:17 ` [PATCH v5 0/4] sim: Add support for MIPS32/64 revision 6 Dragan Mladjenovic
2022-02-02 10:17 ` [PATCH v5 1/4] sim: Allow toggling of quiet NaN-bit semantics Dragan Mladjenovic
2022-02-02 10:17 ` Dragan Mladjenovic [this message]
2022-02-02 10:17 ` [PATCH v5 3/4] sim: Add partial support for IEEE 754-2008 Dragan Mladjenovic
2022-02-02 10:17 ` [PATCH v5 4/4] sim: mips: Add simulator support for mips32r6/mips64r6 Dragan Mladjenovic
2022-12-25 0:26 ` Mike Frysinger
2022-12-27 19:35 ` Dragan Mladjenovic
2022-12-28 0:12 ` Mike Frysinger
2023-01-13 14:09 ` Dragan Mladjenovic
2022-02-04 5:48 ` [PATCH v5 0/4] sim: Add support for MIPS32/64 revision 6 Mike Frysinger
2022-02-04 12:29 ` Dragan Mladjenovic
2022-02-06 14:57 ` Joel Brobecker
2022-02-06 15:38 ` Dragan Mladjenovic
2022-02-06 16:28 ` Joel Brobecker
2022-02-06 18:49 ` Mike Frysinger
2022-02-07 11:48 ` Dragan Mladjenovic
2022-02-13 13:43 ` Joel Brobecker
2022-02-14 0:04 ` Mike Frysinger
2022-04-15 7:24 ` Dragan Mladjenovic
2022-04-15 7:35 ` Eli Zaretskii
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