From: Faraz Shahbazker <fshahbazker@wavecomp.com>
To: gdb-patches@sourceware.org, Mike Frysinger <vapier@gentoo.org>
Cc: Chao-ying Fu <cfu@wavecomp.com>,
Faraz Shahbazker <fshahbazker@wavecomp.com>
Subject: [PATCH v2 3/5] sim: Add partial support for IEEE 754-2008
Date: Mon, 24 May 2021 23:28:00 +0530 [thread overview]
Message-ID: <20210524175802.875687-4-fshahbazker@wavecomp.com> (raw)
In-Reply-To: <20210524175802.875687-1-fshahbazker@wavecomp.com>
2021-05-24 Faraz Shahbazker <fshahbazker@wavecomp.com>
sim/common/ChangeLog:
* sim-fpu.c (sim_fpu_minmax_nan): New.
(sim_fpu_max): Add variant behaviour for IEEE 754-2008.
(sim_fpu_min): Likewise.
(sim_fpu_is_un, sim_fpu_is_or): New.
(sim_fpu_un, sim_fpu_or): New.
(sim_fpu_current_mode): New.
(sim_fpu_is_ieee754_2008, sim_fpu_is_ieee754_1985): New.
(sim_fpu_set_mode): New.
(sim_fpu_classify): New.
* sim-fpu.h (sim_fpu_is_un, sim_fpu_is_or): New declarations.
(sim_fpu_mode): New.
(sim_fpu_is_ieee754_2008): New declaration.
(sim_fpu_is_ieee754_1985): New declaration.
(sim_fpu_set_mode): New declaration.
(sim_fpu_classify): New declaration.
---
Notes:
Changes from v1:
- whitespace and style fixes only
sim/common/sim-fpu.c | 124 +++++++++++++++++++++++++++++++++++++++++--
sim/common/sim-fpu.h | 15 +++++-
2 files changed, 134 insertions(+), 5 deletions(-)
diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index 96b1776e986..26ada87c154 100644
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -1005,6 +1005,29 @@ sim_fpu_op_nan (sim_fpu *f, const sim_fpu *l, const sim_fpu *r)
return 0;
}
+/* NaN handling specific to min/max operations. */
+
+INLINE_SIM_FPU (int)
+sim_fpu_minmax_nan (sim_fpu *f, const sim_fpu *l, const sim_fpu *r)
+{
+ if (sim_fpu_is_snan (l)
+ || sim_fpu_is_snan (r)
+ || sim_fpu_is_ieee754_1985 ())
+ return sim_fpu_op_nan (f, l, r);
+ else
+ /* if sim_fpu_is_ieee754_2008()
+ && ((sim_fpu_is_qnan (l) || sim_fpu_is_qnan (r))) */
+ {
+ /* In IEEE754-2008:
+ * "minNum/maxNum is ... the canonicalized number if one
+ * operand is a number and the other a quiet NaN." */
+ if (sim_fpu_is_qnan (l))
+ *f = *r;
+ else if (sim_fpu_is_qnan (r))
+ *f = *l;
+ }
+}
+
/* Arithmetic ops */
INLINE_SIM_FPU (int)
@@ -1553,7 +1576,7 @@ sim_fpu_max (sim_fpu *f,
const sim_fpu *r)
{
if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
- return sim_fpu_op_nan (f, l, r);
+ return sim_fpu_minmax_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r)
@@ -1616,7 +1639,7 @@ sim_fpu_min (sim_fpu *f,
const sim_fpu *r)
{
if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
- return sim_fpu_op_nan (f, l, r);
+ return sim_fpu_minmax_nan (f, l, r);
if (sim_fpu_is_infinity (l))
{
if (sim_fpu_is_infinity (r)
@@ -1677,7 +1700,7 @@ INLINE_SIM_FPU (int)
sim_fpu_neg (sim_fpu *f,
const sim_fpu *r)
{
- if (sim_fpu_is_snan (r))
+ if (sim_fpu_is_ieee754_1985 () && sim_fpu_is_snan (r))
{
*f = *r;
f->class = sim_fpu_class_qnan;
@@ -1700,7 +1723,7 @@ sim_fpu_abs (sim_fpu *f,
{
*f = *r;
f->sign = 0;
- if (sim_fpu_is_snan (r))
+ if (sim_fpu_is_ieee754_1985 () && sim_fpu_is_snan (r))
{
f->class = sim_fpu_class_qnan;
return sim_fpu_status_invalid_snan;
@@ -2255,6 +2278,23 @@ sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r)
return is;
}
+INLINE_SIM_FPU (int)
+sim_fpu_is_un (const sim_fpu *l,
+ const sim_fpu *r)
+{
+ int is;
+ sim_fpu_un (&is, l, r);
+ return is;
+}
+
+INLINE_SIM_FPU (int)
+sim_fpu_is_or (const sim_fpu *l,
+ const sim_fpu *r)
+{
+ int is;
+ sim_fpu_or (&is, l, r);
+ return is;
+}
/* Compare operators */
@@ -2378,10 +2418,68 @@ sim_fpu_gt (int *is,
return sim_fpu_lt (is, r, l);
}
+INLINE_SIM_FPU (int)
+sim_fpu_un (int *is, const sim_fpu *l, const sim_fpu *r)
+{
+ if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r))
+ {
+ *is = 1;
+ return 0;
+ }
+
+ *is = 0;
+ return 0;
+}
+
+INLINE_SIM_FPU (int)
+sim_fpu_or (int *is, const sim_fpu *l, const sim_fpu *r)
+{
+ sim_fpu_un (is, l, r);
+
+ /* Invert result. */
+ *is = !*is;
+ return 0;
+}
+
+INLINE_SIM_FPU(int)
+sim_fpu_classify (const sim_fpu *f)
+{
+ switch (f->class)
+ {
+ case sim_fpu_class_snan: return SIM_FPU_IS_SNAN;
+ case sim_fpu_class_qnan: return SIM_FPU_IS_QNAN;
+ case sim_fpu_class_infinity:
+ if (!f->sign)
+ return SIM_FPU_IS_PINF;
+ else
+ return SIM_FPU_IS_NINF;
+ case sim_fpu_class_zero:
+ if (!f->sign)
+ return SIM_FPU_IS_PZERO;
+ else
+ return SIM_FPU_IS_NZERO;
+ case sim_fpu_class_number:
+ if (!f->sign)
+ return SIM_FPU_IS_PNUMBER;
+ else
+ return SIM_FPU_IS_NNUMBER;
+ case sim_fpu_class_denorm:
+ if (!f->sign)
+ return SIM_FPU_IS_PDENORM;
+ else
+ return SIM_FPU_IS_NDENORM;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+ return 0;
+}
/* A number of useful constants */
#if EXTERN_SIM_FPU_P
+static sim_fpu_mode sim_fpu_current_mode = sim_fpu_ieee754_1985;
+
const sim_fpu sim_fpu_zero = {
sim_fpu_class_zero, 0, 0, 0
};
@@ -2410,6 +2508,24 @@ const sim_fpu sim_fpu_max64 = {
bool sim_fpu_quiet_nan_inverted = false;
#endif
+/* Specification swapping behaviour */
+INLINE_SIM_FPU (bool)
+sim_fpu_is_ieee754_1985 (void)
+{
+ return (sim_fpu_current_mode == sim_fpu_ieee754_1985);
+}
+
+INLINE_SIM_FPU (bool)
+sim_fpu_is_ieee754_2008 (void)
+{
+ return (sim_fpu_current_mode == sim_fpu_ieee754_2008);
+}
+
+INLINE_SIM_FPU (void)
+sim_fpu_set_mode (const sim_fpu_mode m)
+{
+ sim_fpu_current_mode = m;
+}
/* For debugging */
diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h
index 51bb7d2be92..e4abe6ac96f 100644
--- a/sim/common/sim-fpu.h
+++ b/sim/common/sim-fpu.h
@@ -295,7 +295,8 @@ INLINE_SIM_FPU (double) sim_fpu_2d (const sim_fpu *d);
/* INLINE_SIM_FPU (void) sim_fpu_f2 (sim_fpu *f, float s); */
INLINE_SIM_FPU (void) sim_fpu_d2 (sim_fpu *f, double d);
-
+/* IEEE754-2008 classifiction function. */
+INLINE_SIM_FPU (int) sim_fpu_classify (const sim_fpu *f);
/* Specific number classes.
@@ -343,8 +344,20 @@ INLINE_SIM_FPU (int) sim_fpu_is_eq (const sim_fpu *l, const sim_fpu *r);
INLINE_SIM_FPU (int) sim_fpu_is_ne (const sim_fpu *l, const sim_fpu *r);
INLINE_SIM_FPU (int) sim_fpu_is_ge (const sim_fpu *l, const sim_fpu *r);
INLINE_SIM_FPU (int) sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r);
+INLINE_SIM_FPU (int) sim_fpu_is_un (const sim_fpu *l, const sim_fpu *r);
+INLINE_SIM_FPU (int) sim_fpu_is_or (const sim_fpu *l, const sim_fpu *r);
+/* Changes the behaviour of the library to IEEE754-2008 or IEEE754-1985.
+ * The default for the library is IEEE754-1985. */
+typedef enum
+{
+ sim_fpu_ieee754_1985,
+ sim_fpu_ieee754_2008,
+} sim_fpu_mode;
+INLINE_SIM_FPU (bool) sim_fpu_is_ieee754_1985 (void);
+INLINE_SIM_FPU (bool) sim_fpu_is_ieee754_2008 (void);
+INLINE_SIM_FPU (void) sim_fpu_set_mode (const sim_fpu_mode m);
/* General number class and comparison operators.
--
2.25.1
next prev parent reply other threads:[~2021-05-24 17:58 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 7:45 [PATCH 0/5] Add support for MIPS32/64 revision 6 Faraz Shahbazker
2021-05-20 7:45 ` [PATCH 1/5] sim: Allow toggling of quiet NaN-bit semantics Faraz Shahbazker
2021-05-22 1:16 ` Mike Frysinger
2021-05-20 7:45 ` [PATCH 2/5] sim: Factor out NaN handling in floating point operations Faraz Shahbazker
2021-05-22 1:25 ` Mike Frysinger
2021-05-23 6:32 ` [EXTERNAL]Re: " Faraz Shahbazker
2021-05-24 1:26 ` Mike Frysinger
2021-05-20 7:45 ` [PATCH 3/5] sim: Add partial support for IEEE 754-2008 Faraz Shahbazker
2021-05-22 1:34 ` Mike Frysinger
2021-05-20 7:45 ` [PATCH 4/5] sim: mips: Add simulator support for mips32r6/mips64r6 Faraz Shahbazker
2021-05-22 1:46 ` Mike Frysinger
2021-05-22 6:20 ` Eli Zaretskii
2021-06-27 19:25 ` [EXTERNAL]Re: " Faraz Shahbazker
2021-06-27 19:33 ` Simon Marchi
2021-06-27 19:44 ` Eli Zaretskii
2021-06-27 20:24 ` Faraz Shahbazker
2021-06-28 12:17 ` Eli Zaretskii
2021-07-02 10:10 ` Faraz Shahbazker
2021-12-24 18:42 ` Mike Frysinger
2021-06-28 1:16 ` Mike Frysinger
2021-05-22 6:44 ` Faraz Shahbazker
2021-05-24 17:57 ` [PATCH v2 0/5] Add support for MIPS32/64 revision 6 Faraz Shahbazker
2021-05-24 17:57 ` [PATCH v2 1/5] sim: Allow toggling of quiet NaN-bit semantics Faraz Shahbazker
2021-05-24 17:57 ` [PATCH v2 2/5] sim: Factor out NaN handling in floating point operations Faraz Shahbazker
2021-05-24 17:58 ` Faraz Shahbazker [this message]
2021-05-24 17:58 ` [PATCH v2 4/5] sim: mips: Add simulator support for mips32r6/mips64r6 Faraz Shahbazker
2021-05-24 17:58 ` [PATCH v2 5/5] gdb: mips: Add MIPSR6 support Faraz Shahbazker
2021-05-29 1:53 ` Simon Marchi
2021-06-27 19:10 ` [PATCH v3 " Faraz Shahbazker
2021-05-20 7:45 ` [PATCH " Faraz Shahbazker
2022-02-02 10:17 ` [PATCH v5 0/4] sim: Add support for MIPS32/64 revision 6 Dragan Mladjenovic
2022-02-02 10:17 ` [PATCH v5 1/4] sim: Allow toggling of quiet NaN-bit semantics Dragan Mladjenovic
2022-02-02 10:17 ` [PATCH v5 2/4] sim: Factor out NaN handling in floating point operations Dragan Mladjenovic
2022-02-02 10:17 ` [PATCH v5 3/4] sim: Add partial support for IEEE 754-2008 Dragan Mladjenovic
2022-02-02 10:17 ` [PATCH v5 4/4] sim: mips: Add simulator support for mips32r6/mips64r6 Dragan Mladjenovic
2022-12-25 0:26 ` Mike Frysinger
2022-12-27 19:35 ` Dragan Mladjenovic
2022-12-28 0:12 ` Mike Frysinger
2023-01-13 14:09 ` Dragan Mladjenovic
2022-02-04 5:48 ` [PATCH v5 0/4] sim: Add support for MIPS32/64 revision 6 Mike Frysinger
2022-02-04 12:29 ` Dragan Mladjenovic
2022-02-06 14:57 ` Joel Brobecker
2022-02-06 15:38 ` Dragan Mladjenovic
2022-02-06 16:28 ` Joel Brobecker
2022-02-06 18:49 ` Mike Frysinger
2022-02-07 11:48 ` Dragan Mladjenovic
2022-02-13 13:43 ` Joel Brobecker
2022-02-14 0:04 ` Mike Frysinger
2022-04-15 7:24 ` Dragan Mladjenovic
2022-04-15 7:35 ` Eli Zaretskii
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