From: Mike Frysinger <vapier@gentoo.org>
To: gdb-patches@sourceware.org
Subject: [PATCH 14/20] sim: pru: move arch-specific settings to internal header
Date: Fri, 23 Dec 2022 01:07:07 -0500 [thread overview]
Message-ID: <20221223060713.28821-15-vapier@gentoo.org> (raw)
In-Reply-To: <20221223060713.28821-1-vapier@gentoo.org>
There's no need for these settings to be in sim-main.h which is shared
with common/ sim code, so drop the pru.h include and move the remaining
pru-specific settings into it.
---
sim/pru/pru.h | 56 ++++++++++++++++++++++++++++++++++++++++++++
sim/pru/sim-main.h | 58 ----------------------------------------------
2 files changed, 56 insertions(+), 58 deletions(-)
diff --git a/sim/pru/pru.h b/sim/pru/pru.h
index f6b633b29bd0..375a988ddc1f 100644
--- a/sim/pru/pru.h
+++ b/sim/pru/pru.h
@@ -19,6 +19,8 @@
#ifndef PRU_H
#define PRU_H
+#include <stdint.h>
+
#include "opcode/pru.h"
/* Needed for handling the dual PRU address space. */
@@ -108,4 +110,58 @@
/* 32 GP registers plus PC. */
#define NUM_REGS 33
+/* The machine state.
+ This state is maintained in host byte order. The
+ fetch/store register functions must translate between host
+ byte order and the target processor byte order.
+ Keeping this data in target byte order simplifies the register
+ read/write functions. Keeping this data in host order improves
+ the performance of the simulator. Simulation speed is deemed more
+ important. */
+
+/* For clarity, please keep the same relative order in this enum as in the
+ corresponding group of GP registers.
+
+ In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
+ the GP registers. MAC registers are implicitly addressed when executing
+ the XIN/XOUT instructions to access them. Transfer to/from a MAC register
+ can happen only from/to its corresponding GP peer register. */
+
+enum pru_macreg_id {
+ /* MAC register CPU GP register Description. */
+ PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */
+ PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */
+ PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */
+ PRU_MACREG_OP_0, /* r28 */ /* First operand. */
+ PRU_MACREG_OP_1, /* r29 */ /* Second operand. */
+ PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */
+ PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC
+ accumulator. */
+ PRU_MAC_NREGS
+};
+
+struct pru_regset
+{
+ uint32_t regs[32]; /* Primary registers. */
+ uint16_t pc; /* IMEM _word_ address. */
+ uint32_t pc_addr_space_marker; /* IMEM virtual linker offset. This
+ is the artificial offset that
+ we invent in order to "separate"
+ the DMEM and IMEM memory spaces. */
+ unsigned int carry : 1;
+ uint32_t ctable[32]; /* Constant offsets table for xBCO. */
+ uint32_t macregs[PRU_MAC_NREGS];
+ uint32_t scratchpads[XFRID_MAX + 1][32];
+ struct {
+ uint16_t looptop; /* LOOP top (PC of loop instr). */
+ uint16_t loopend; /* LOOP end (PC of loop end label). */
+ int loop_in_progress; /* Whether to check for PC==loopend. */
+ uint32_t loop_counter; /* LOOP counter. */
+ } loop;
+ int cycles;
+ int insts;
+};
+
+#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
+
#endif /* PRU_H */
diff --git a/sim/pru/sim-main.h b/sim/pru/sim-main.h
index ada1e3886278..0925c3a120d9 100644
--- a/sim/pru/sim-main.h
+++ b/sim/pru/sim-main.h
@@ -19,65 +19,7 @@
#ifndef PRU_SIM_MAIN
#define PRU_SIM_MAIN
-#include <stdint.h>
-#include <stddef.h>
-#include "pru.h"
#include "sim-basics.h"
-
#include "sim-base.h"
-/* The machine state.
- This state is maintained in host byte order. The
- fetch/store register functions must translate between host
- byte order and the target processor byte order.
- Keeping this data in target byte order simplifies the register
- read/write functions. Keeping this data in host order improves
- the performance of the simulator. Simulation speed is deemed more
- important. */
-
-/* For clarity, please keep the same relative order in this enum as in the
- corresponding group of GP registers.
-
- In PRU ISA, Multiplier-Accumulator-Unit's registers are like "shadows" of
- the GP registers. MAC registers are implicitly addressed when executing
- the XIN/XOUT instructions to access them. Transfer to/from a MAC register
- can happen only from/to its corresponding GP peer register. */
-
-enum pru_macreg_id {
- /* MAC register CPU GP register Description. */
- PRU_MACREG_MODE, /* r25 */ /* Mode (MUL/MAC). */
- PRU_MACREG_PROD_L, /* r26 */ /* Lower 32 bits of product. */
- PRU_MACREG_PROD_H, /* r27 */ /* Higher 32 bits of product. */
- PRU_MACREG_OP_0, /* r28 */ /* First operand. */
- PRU_MACREG_OP_1, /* r29 */ /* Second operand. */
- PRU_MACREG_ACC_L, /* N/A */ /* Accumulator (not exposed) */
- PRU_MACREG_ACC_H, /* N/A */ /* Higher 32 bits of MAC
- accumulator. */
- PRU_MAC_NREGS
-};
-
-struct pru_regset
-{
- uint32_t regs[32]; /* Primary registers. */
- uint16_t pc; /* IMEM _word_ address. */
- uint32_t pc_addr_space_marker; /* IMEM virtual linker offset. This
- is the artificial offset that
- we invent in order to "separate"
- the DMEM and IMEM memory spaces. */
- unsigned int carry : 1;
- uint32_t ctable[32]; /* Constant offsets table for xBCO. */
- uint32_t macregs[PRU_MAC_NREGS];
- uint32_t scratchpads[XFRID_MAX + 1][32];
- struct {
- uint16_t looptop; /* LOOP top (PC of loop instr). */
- uint16_t loopend; /* LOOP end (PC of loop end label). */
- int loop_in_progress; /* Whether to check for PC==loopend. */
- uint32_t loop_counter; /* LOOP counter. */
- } loop;
- int cycles;
- int insts;
-};
-
-#define PRU_SIM_CPU(cpu) ((struct pru_regset *) CPU_ARCH_DATA (cpu))
-
#endif /* PRU_SIM_MAIN */
--
2.39.0
next prev parent reply other threads:[~2022-12-23 6:07 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-23 6:06 [PATCH 00/20] sim: reduce sim-main.h pollution Mike Frysinger
2022-12-23 6:06 ` [PATCH 01/20] sim: avr: move arch-specific settings to internal header Mike Frysinger
2022-12-23 6:06 ` [PATCH 02/20] sim: aarch64: " Mike Frysinger
2022-12-23 6:06 ` [PATCH 03/20] sim: arm: " Mike Frysinger
2022-12-23 6:06 ` [PATCH 04/20] sim: cr16: " Mike Frysinger
2022-12-23 6:06 ` [PATCH 05/20] sim: d10v: " Mike Frysinger
2022-12-23 6:06 ` [PATCH 06/20] sim: ft32: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 07/20] sim: msp430: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 08/20] sim: v850: standardize the arch-specific settings a little Mike Frysinger
2022-12-23 6:07 ` [PATCH 09/20] sim: riscv: move arch-specific settings to internal header Mike Frysinger
2022-12-23 6:07 ` [PATCH 10/20] sim: moxie: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 11/20] sim: example-synacor: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 12/20] sim: microblaze: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 13/20] sim: mn10300: standardize the arch-specific settings a little Mike Frysinger
2022-12-23 6:07 ` Mike Frysinger [this message]
2022-12-23 6:07 ` [PATCH 15/20] sim: h8300: move arch-specific settings to internal header Mike Frysinger
2022-12-23 6:07 ` [PATCH 16/20] sim: mcore: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 17/20] sim: sh: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 18/20] sim: m68hc11: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 19/20] sim: bfin: " Mike Frysinger
2022-12-23 6:07 ` [PATCH 20/20] sim: m32r: " Mike Frysinger
2022-12-24 1:55 ` [PATCH] sim: or1k: " Mike Frysinger
2022-12-24 10:18 ` Stafford Horne
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