[PATCH v2 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support

[<jaydeep.patil@imgtec.com>]

From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Andrew,

Addressed review comments. Simulator specific tests are added in sim/testsuite/riscv/c-ext.s file.

This is a collection of patches that add simulation of compressed integer
instruction set ("c") and semi-hosting support to the RISC-V simulator. Two tests are
added in gdb.arch to test basic semi-hosting and then the simulation of
compressed integer instructions.

Patch #1 adds basic semi-hosting support (OPEN, EXIT and GET_CMDLINE)
and gdb.arch/riscv-exit-getcmd.c test

Patch #2 adds support for compressed integer instruction set ("c")
and gdb.arch/riscv-insn-simulation.c and sim/testsuite/riscv/c-ext.s tests

Patch #3 adds support for remaining semi-hosting calls

Contributions from:
  Joseph Faulls (Joseph.Faulls@imgtec.com)
  Jaydeep Patil (Jaydeep.Patil@imgtec.com)
  Bhushan Attarde (Bhushan.Attarde@imgtec.com)

Jaydeep Patil (3):
  [sim/riscv] Add basic semi-hosting support
  [sim/riscv] Add support for compressed integer instruction set
  [sim/riscv] Add semi-hosting support

 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c    |   26 +
 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp  |   27 +
 .../gdb.arch/riscv-insn-simulation.c          | 1542 +++++++++++++++++
 .../gdb.arch/riscv-insn-simulation.exp        |   32 +
 sim/riscv/riscv-sim.h                         |   57 +
 sim/riscv/sim-main.c                          | 1050 ++++++++++-
 sim/testsuite/riscv/c-ext.s                   |  110 ++
 7 files changed, 2829 insertions(+), 15 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp
 create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.c
 create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp
 create mode 100644 sim/testsuite/riscv/c-ext.s

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2.25.1