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From: Mike Frysinger <vapier@gentoo.org>
To: jaydeep.patil@imgtec.com
Cc: gdb-patches@sourceware.org, aburgess@redhat.com,
	joseph.faulls@imgtec.com, bhushan.attarde@imgtec.com
Subject: Re: [PATCH v2 1/3] [sim/riscv] Add basic semi-hosting support
Date: Wed, 29 Nov 2023 02:57:30 -0500	[thread overview]
Message-ID: <ZWbu6jj7CSSS9i91@vapier> (raw)
In-Reply-To: <20231030130042.1472535-2-jaydeep.patil@imgtec.com>

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On 30 Oct 2023 13:00, jaydeep.patil@imgtec.com wrote:
> Added support for basic semi-hosting calls OPEN, EXIT and GET_CMDLINE.

what host environment are you implementing ?  none of the syscalls you've
defined match what have long been in the riscv libgloss port.  those are
the only ones i'd really expect at this point to be wired up.

> Added gdb.arch/riscv-exit-getcmd.c to test it.
> ---
>  gdb/testsuite/gdb.arch/riscv-exit-getcmd.c   |  26 +++
>  gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp |  27 +++
>  sim/riscv/riscv-sim.h                        |  32 +++
>  sim/riscv/sim-main.c                         | 230 ++++++++++++++++++-

you're missing sim/ tests.  gdb tests are great, but not sufficient.

> @@ -990,6 +1209,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>      case INSN_CLASS_A:
>        return execute_a (cpu, iw, op);
>      case INSN_CLASS_I:
> +    case INSN_CLASS_ZICSR:
>        return execute_i (cpu, iw, op);

seems unrelated to this patch
-mike

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  reply	other threads:[~2023-11-29  7:57 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-30 13:00 [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and " jaydeep.patil
2023-10-30 13:00 ` [PATCH v2 1/3] [sim/riscv] Add basic " jaydeep.patil
2023-11-29  7:57   ` Mike Frysinger [this message]
2023-12-12 17:24     ` Andrew Burgess
2023-12-13  3:43       ` Mike Frysinger
2023-12-18 12:44         ` Andrew Burgess
2023-12-18 23:06           ` Mike Frysinger
2023-12-19  6:13     ` [EXTERNAL] " Jaydeep Patil
2023-12-20  1:45       ` Mike Frysinger
2023-12-20  8:52         ` Jaydeep Patil
2023-12-12 17:57   ` Andrew Burgess
2023-10-30 13:00 ` [PATCH v2 2/3] [sim/riscv] Add support for compressed integer instruction set jaydeep.patil
2023-11-29  7:58   ` Mike Frysinger
2023-12-19  6:11     ` [EXTERNAL] " Jaydeep Patil
2023-12-20  1:32       ` Mike Frysinger
2023-10-30 13:00 ` [PATCH v2 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-11-13 12:07 ` [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and " Jaydeep Patil

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