From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
To: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Cc: "aburgess@redhat.com" <aburgess@redhat.com>,
"vapier@gentoo.org" <vapier@gentoo.org>,
Joseph Faulls <Joseph.Faulls@imgtec.com>,
"Bhushan Attarde" <Bhushan.Attarde@imgtec.com>
Subject: RE: [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support
Date: Mon, 13 Nov 2023 12:07:42 +0000 [thread overview]
Message-ID: <CWXP265MB53216A631E2D283D9DCDA29F8CB3A@CWXP265MB5321.GBRP265.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <20231030130042.1472535-1-jaydeep.patil@imgtec.com>
Hi Andrew,
Could you please find some time to review this?
Thank you,
Jaydeep
-----Original Message-----
From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
Sent: Monday, October 30, 2023 6:31 PM
To: gdb-patches@sourceware.org
Cc: aburgess@redhat.com; vapier@gentoo.org; Joseph Faulls <Joseph.Faulls@imgtec.com>; Bhushan Attarde <Bhushan.Attarde@imgtec.com>; Jaydeep Patil <Jaydeep.Patil@imgtec.com>
Subject: [PATCH v2 0/3] sim: riscv: Compressed instruction simulation and semi-hosting support
*** NOTE: This is an internal email from Imagination Technologies ***
From: Jaydeep Patil <jaydeep.patil@imgtec.com>
Hi Andrew,
Addressed review comments. Simulator specific tests are added in sim/testsuite/riscv/c-ext.s file.
This is a collection of patches that add simulation of compressed integer instruction set ("c") and semi-hosting support to the RISC-V simulator. Two tests are added in gdb.arch to test basic semi-hosting and then the simulation of compressed integer instructions.
Patch #1 adds basic semi-hosting support (OPEN, EXIT and GET_CMDLINE) and gdb.arch/riscv-exit-getcmd.c test
Patch #2 adds support for compressed integer instruction set ("c") and gdb.arch/riscv-insn-simulation.c and sim/testsuite/riscv/c-ext.s tests
Patch #3 adds support for remaining semi-hosting calls
Contributions from:
Joseph Faulls (Joseph.Faulls@imgtec.com)
Jaydeep Patil (Jaydeep.Patil@imgtec.com)
Bhushan Attarde (Bhushan.Attarde@imgtec.com)
Jaydeep Patil (3):
[sim/riscv] Add basic semi-hosting support
[sim/riscv] Add support for compressed integer instruction set
[sim/riscv] Add semi-hosting support
gdb/testsuite/gdb.arch/riscv-exit-getcmd.c | 26 +
gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp | 27 +
.../gdb.arch/riscv-insn-simulation.c | 1542 +++++++++++++++++
.../gdb.arch/riscv-insn-simulation.exp | 32 +
sim/riscv/riscv-sim.h | 57 +
sim/riscv/sim-main.c | 1050 ++++++++++-
sim/testsuite/riscv/c-ext.s | 110 ++
7 files changed, 2829 insertions(+), 15 deletions(-) create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c
create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp
create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.c
create mode 100755 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp
create mode 100644 sim/testsuite/riscv/c-ext.s
--
2.25.1
prev parent reply other threads:[~2023-11-13 12:08 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 13:00 jaydeep.patil
2023-10-30 13:00 ` [PATCH v2 1/3] [sim/riscv] Add basic " jaydeep.patil
2023-11-29 7:57 ` Mike Frysinger
2023-12-12 17:24 ` Andrew Burgess
2023-12-13 3:43 ` Mike Frysinger
2023-12-18 12:44 ` Andrew Burgess
2023-12-18 23:06 ` Mike Frysinger
2023-12-19 6:13 ` [EXTERNAL] " Jaydeep Patil
2023-12-20 1:45 ` Mike Frysinger
2023-12-20 8:52 ` Jaydeep Patil
2023-12-12 17:57 ` Andrew Burgess
2023-10-30 13:00 ` [PATCH v2 2/3] [sim/riscv] Add support for compressed integer instruction set jaydeep.patil
2023-11-29 7:58 ` Mike Frysinger
2023-12-19 6:11 ` [EXTERNAL] " Jaydeep Patil
2023-12-20 1:32 ` Mike Frysinger
2023-10-30 13:00 ` [PATCH v2 3/3] [sim/riscv] Add semi-hosting support jaydeep.patil
2023-11-13 12:07 ` Jaydeep Patil [this message]
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