Re: [PATCH v2 1/3] [sim/riscv] Add basic semi-hosting support

[Andrew Burgess <aburgess@redhat.com>]

Mike Frysinger <vapier@gentoo.org> writes:

> On 30 Oct 2023 13:00, jaydeep.patil@imgtec.com wrote:
>> Added support for basic semi-hosting calls OPEN, EXIT and GET_CMDLINE.
>
> what host environment are you implementing ?  none of the syscalls you've
> defined match what have long been in the riscv libgloss port.  those are
> the only ones i'd really expect at this point to be wired up.

This would be the RISC-V semihosting target, which is included in
newlib (since 2020), but is separate to libgloss.

Where libgloss syscalls use ecall, the semihosting uses ebreak with two
specific nop instructions (one before, one after the ebreak).

Do you see any reason why we can't support both of these syscall
libraries?  Potentially we could have a switch to select between them,
but I'm inclined to say we should just support both until someone comes
with a use-case where supporting both is a bad idea...  But maybe you
have some deeper insights here.

>
>> Added gdb.arch/riscv-exit-getcmd.c to test it.
>> ---
>>  gdb/testsuite/gdb.arch/riscv-exit-getcmd.c   |  26 +++
>>  gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp |  27 +++
>>  sim/riscv/riscv-sim.h                        |  32 +++
>>  sim/riscv/sim-main.c                         | 230 ++++++++++++++++++-
>
> you're missing sim/ tests.  gdb tests are great, but not sufficient.

100% agree with this.

Thanks,
Andrew

>
>> @@ -990,6 +1209,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>>      case INSN_CLASS_A:
>>        return execute_a (cpu, iw, op);
>>      case INSN_CLASS_I:
>> +    case INSN_CLASS_ZICSR:
>>        return execute_i (cpu, iw, op);
>
> seems unrelated to this patch
> -mike