[PATCH 01/15] sim: aarch64: fix -Wshadow=local warnings

[PATCH 01/15] sim: aarch64: fix -Wshadow=local warnings

[Mike Frysinger]

These functions have local vars named "val" of type float, and
then create nested vars named "val" of type double.  This is a
bit confusing and causes build time warnings.
---
 sim/aarch64/simulator.c | 42 ++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c
index 8825819a3910..e7537b739aa0 100644
--- a/sim/aarch64/simulator.c
+++ b/sim/aarch64/simulator.c
@@ -7942,44 +7942,44 @@ do_FRINT (sim_cpu *cpu)
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
   if (INSTR (22, 22))
     {
-      double val = aarch64_get_FP_double (cpu, rs);
+      double dval = aarch64_get_FP_double (cpu, rs);
 
       switch (rmode)
 	{
 	case 0: /* mode N: nearest or even.  */
 	  {
-	    double rval = round (val);
+	    double rval = round (dval);
 
-	    if (val - rval == 0.5)
+	    if (dval - rval == 0.5)
 	      {
 		if (((rval / 2.0) * 2.0) != rval)
 		  rval += 1.0;
 	      }
 
-	    aarch64_set_FP_double (cpu, rd, round (val));
+	    aarch64_set_FP_double (cpu, rd, round (dval));
 	    return;
 	  }
 
 	case 1: /* mode P: towards +inf.  */
-	  if (val < 0.0)
-	    aarch64_set_FP_double (cpu, rd, trunc (val));
+	  if (dval < 0.0)
+	    aarch64_set_FP_double (cpu, rd, trunc (dval));
 	  else
-	    aarch64_set_FP_double (cpu, rd, round (val));
+	    aarch64_set_FP_double (cpu, rd, round (dval));
 	  return;
 
 	case 2: /* mode M: towards -inf.  */
-	  if (val < 0.0)
-	    aarch64_set_FP_double (cpu, rd, round (val));
+	  if (dval < 0.0)
+	    aarch64_set_FP_double (cpu, rd, round (dval));
 	  else
-	    aarch64_set_FP_double (cpu, rd, trunc (val));
+	    aarch64_set_FP_double (cpu, rd, trunc (dval));
 	  return;
 
 	case 3: /* mode Z: towards 0.  */
-	  aarch64_set_FP_double (cpu, rd, trunc (val));
+	  aarch64_set_FP_double (cpu, rd, trunc (dval));
 	  return;
 
 	case 4: /* mode A: away from 0.  */
-	  aarch64_set_FP_double (cpu, rd, round (val));
+	  aarch64_set_FP_double (cpu, rd, round (dval));
 	  return;
 
 	case 6: /* mode X: use FPCR with exactness check.  */
@@ -9186,29 +9186,29 @@ do_scalar_FCM (sim_cpu *cpu)
   TRACE_DECODE (cpu, "emulated at line %d", __LINE__);
   if (INSTR (22, 22))
     {
-      double val1 = aarch64_get_FP_double (cpu, rn);
-      double val2 = aarch64_get_FP_double (cpu, rm);
+      double dval1 = aarch64_get_FP_double (cpu, rn);
+      double dval2 = aarch64_get_FP_double (cpu, rm);
 
       switch (EUac)
 	{
 	case 0: /* 000 */
-	  result = val1 == val2;
+	  result = dval1 == dval2;
 	  break;
 
 	case 3: /* 011 */
-	  val1 = fabs (val1);
-	  val2 = fabs (val2);
+	  dval1 = fabs (dval1);
+	  dval2 = fabs (dval2);
 	  ATTRIBUTE_FALLTHROUGH;
 	case 2: /* 010 */
-	  result = val1 >= val2;
+	  result = dval1 >= dval2;
 	  break;
 
 	case 7: /* 111 */
-	  val1 = fabs (val1);
-	  val2 = fabs (val2);
+	  dval1 = fabs (dval1);
+	  dval2 = fabs (dval2);
 	  ATTRIBUTE_FALLTHROUGH;
 	case 6: /* 110 */
-	  result = val1 > val2;
+	  result = dval1 > dval2;
 	  break;
 
 	default:
-- 
2.43.0

[PATCH 02/15] sim: arm: fix -Wshadow=local warnings

[Mike Frysinger]

Remove duplicate nested variable declarations, rename some to avoid
confusion when the type is different or the original value should be
retained, and fix some weirdness with nested enums in structs.
---
 sim/arm/armemu.c   | 38 +++++++++++++++++---------------------
 sim/arm/thumbemu.c | 22 ++++++----------------
 sim/arm/wrapper.c  | 16 +++++++---------
 3 files changed, 30 insertions(+), 46 deletions(-)

diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c
index 2b8ae007cb56..cafaabbf637c 100644
--- a/sim/arm/armemu.c
+++ b/sim/arm/armemu.c
@@ -1023,7 +1023,7 @@ handle_v6_insn (ARMul_State * state, ARMword instr)
 	Rn = BITS (0, 3);
 	if (Rn != 0xF)
 	  {
-	    ARMword val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
+	    val = state->Reg[Rn] & ~(-(1 << ((msb + 1) - lsb)));
 	    state->Reg[Rd] |= val << lsb;
 	  }
 	return 1;
@@ -1434,8 +1434,6 @@ ARMul_Emulate26 (ARMul_State * state)
 	    {
 	      if (BITS (25, 27) == 5) /* BLX(1) */
 		{
-		  ARMword dest;
-
 		  state->Reg[14] = pc + 4;
 
 		  /* Force entry into Thumb mode.  */
@@ -1568,10 +1566,10 @@ check_PMUintr:
 
 		  if (do_int && (cp14r0 & ARMul_CP14_R0_INTEN2))
 		    {
-		      ARMword temp;
+		      ARMword cp;
 
-		      if (state->CPRead[13] (state, 8, & temp)
-			  && (temp & ARMul_CP13_R8_PMUS))
+		      if (state->CPRead[13] (state, 8, & cp)
+			  && (cp & ARMul_CP13_R8_PMUS))
 		        ARMul_Abort (state, ARMul_FIQV);
 		      else
 		        ARMul_Abort (state, ARMul_IRQV);
@@ -1604,8 +1602,8 @@ check_PMUintr:
 		  if (BITS (4, 7) == 0xD)
 		    {
 		      /* XScale Load Consecutive insn.  */
-		      ARMword temp = GetLS7RHS (state, instr);
-		      ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
+		      ARMword temp1 = GetLS7RHS (state, instr);
+		      ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1;
 		      ARMword addr = BIT (24) ? temp2 : LHS;
 
 		      if (BIT (12))
@@ -1630,8 +1628,8 @@ check_PMUintr:
 		  else if (BITS (4, 7) == 0xF)
 		    {
 		      /* XScale Store Consecutive insn.  */
-		      ARMword temp = GetLS7RHS (state, instr);
-		      ARMword temp2 = BIT (23) ? LHS + temp : LHS - temp;
+		      ARMword temp1 = GetLS7RHS (state, instr);
+		      ARMword temp2 = BIT (23) ? LHS + temp1 : LHS - temp1;
 		      ARMword addr = BIT (24) ? temp2 : LHS;
 
 		      if (BIT (12))
@@ -2313,15 +2311,13 @@ check_PMUintr:
 		  if (BITS (4, 7) == 3)
 		    {
 		      /* BLX(2) */
-		      ARMword temp;
-
 		      if (TFLAG)
-			temp = (pc + 2) | 1;
+			dest = (pc + 2) | 1;
 		      else
-			temp = pc + 4;
+			dest = pc + 4;
 
 		      WriteR15Branch (state, state->Reg[RHSReg]);
-		      state->Reg[14] = temp;
+		      state->Reg[14] = dest;
 		      break;
 		    }
 		}
@@ -2487,7 +2483,7 @@ check_PMUintr:
 		      /* ElSegundo SMLALxy insn.  */
 		      ARMdword op1 = state->Reg[BITS (0, 3)];
 		      ARMdword op2 = state->Reg[BITS (8, 11)];
-		      ARMdword dest;
+		      ARMdword result;
 
 		      if (BIT (5))
 			op1 >>= 16;
@@ -2500,11 +2496,11 @@ check_PMUintr:
 		      if (op2 & 0x8000)
 			op2 -= 65536;
 
-		      dest = (ARMdword) state->Reg[BITS (16, 19)] << 32;
-		      dest |= state->Reg[BITS (12, 15)];
-		      dest += op1 * op2;
-		      state->Reg[BITS (12, 15)] = dest;
-		      state->Reg[BITS (16, 19)] = dest >> 32;
+		      result = (ARMdword) state->Reg[BITS (16, 19)] << 32;
+		      result |= state->Reg[BITS (12, 15)];
+		      result += op1 * op2;
+		      state->Reg[BITS (12, 15)] = result;
+		      state->Reg[BITS (16, 19)] = result >> 32;
 		      break;
 		    }
 
diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index 99f51ef34691..58a9c85ce2b9 100644
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -2131,14 +2131,11 @@ ARMul_ThumbDecode (ARMul_State * state,
       if ((tinstr & (1 << 10)) == 0)
 	{
 	  /* Format 4 */
-	  struct
-	  {
+	  struct insn_format {
 	    ARMword opcode;
-	    enum
-	    { t_norm, t_shift, t_neg, t_mul }
-	    otype;
-	  }
-	  subset[16] =
+	    enum { t_norm, t_shift, t_neg, t_mul } otype;
+	  };
+	  struct insn_format subset[16] =
 	  {
 	    { 0xE0100000, t_norm},			/* ANDS Rd,Rd,Rs     */
 	    { 0xE0300000, t_norm},			/* EORS Rd,Rd,Rs     */
@@ -2161,14 +2158,7 @@ ARMul_ThumbDecode (ARMul_State * state,
 
 	  if (in_IT_block ())
 	    {
-	      struct
-	      {
-		ARMword opcode;
-		enum
-		  { t_norm, t_shift, t_neg, t_mul }
-		  otype;
-	      }
-	      subset[16] =
+	      struct insn_format it_subset[16] =
 		{
 		  { 0xE0000000, t_norm},	/* AND  Rd,Rd,Rs     */
 		  { 0xE0200000, t_norm},	/* EOR  Rd,Rd,Rs     */
@@ -2187,7 +2177,7 @@ ARMul_ThumbDecode (ARMul_State * state,
 		  { 0xE1C00000, t_norm},	/* BIC  Rd,Rd,Rs     */
 		  { 0xE1E00000, t_norm}		/* MVN  Rd,Rs        */
 		};
-	      *ainstr = subset[(tinstr & 0x03C0) >> 6].opcode;	/* base */
+	      *ainstr = it_subset[(tinstr & 0x03C0) >> 6].opcode;	/* base */
 	    }
 
 	  switch (subset[(tinstr & 0x03C0) >> 6].otype)
diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c
index 8d928a6f79f9..06512754725b 100644
--- a/sim/arm/wrapper.c
+++ b/sim/arm/wrapper.c
@@ -746,14 +746,14 @@ sim_target_parse_command_line (int argc, char ** argv)
 
       while (* ptr)
 	{
-	  int i;
+	  int o;
 
-	  for (i = ARRAY_SIZE (options); i--;)
-	    if (strncmp (ptr, options[i].swi_option,
-			 strlen (options[i].swi_option)) == 0)
+	  for (o = ARRAY_SIZE (options); o--;)
+	    if (strncmp (ptr, options[o].swi_option,
+			 strlen (options[o].swi_option)) == 0)
 	      {
-		swi_mask |= options[i].swi_mask;
-		ptr += strlen (options[i].swi_option);
+		swi_mask |= options[o].swi_mask;
+		ptr += strlen (options[o].swi_option);
 
 		if (* ptr == ',')
 		  ++ ptr;
@@ -761,7 +761,7 @@ sim_target_parse_command_line (int argc, char ** argv)
 		break;
 	      }
 
-	  if (i < 0)
+	  if (o < 0)
 	    break;
 	}
 
@@ -884,8 +884,6 @@ sim_open (SIM_OPEN_KIND kind,
 
   if (argv_copy[1] != NULL)
     {
-      int i;
-
       /* Scan for memory-size switches.  */
       for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++)
 	if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')
-- 
2.43.0

[PATCH 03/15] sim: bfin: fix -Wshadow=local warnings

[Mike Frysinger]

Rename the shadowed var to avoid confusion with the function argument
as to which address this code is using.
---
 sim/bfin/dv-bfin_mmu.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/bfin/dv-bfin_mmu.c b/sim/bfin/dv-bfin_mmu.c
index c14e2088c1f1..3d244344ac0c 100644
--- a/sim/bfin/dv-bfin_mmu.c
+++ b/sim/bfin/dv-bfin_mmu.c
@@ -144,7 +144,7 @@ bfin_mmu_io_write_buffer (struct hw *me, const void *source,
       *valuep = value;
       if (value)
 	{
-	  bu32 addr = mmu->sram_base_address   |
+	  bu32 sram_addr = mmu->sram_base_address   |
 	    ((value >> (26 - 11)) & (1 << 11)) | /* addr bit 11 (Way0/Way1)   */
 	    ((value >> (24 - 21)) & (1 << 21)) | /* addr bit 21 (Data/Inst)   */
 	    ((value >> (23 - 15)) & (1 << 15)) | /* addr bit 15 (Data Bank)   */
@@ -157,9 +157,9 @@ bfin_mmu_io_write_buffer (struct hw *me, const void *source,
 	    hw_abort (me, "DTEST_COMMAND bits undefined");
 
 	  if (value & TEST_WRITE)
-	    sim_write (hw_system (me), addr, mmu->dtest_data, 8);
+	    sim_write (hw_system (me), sram_addr, mmu->dtest_data, 8);
 	  else
-	    sim_read (hw_system (me), addr, mmu->dtest_data, 8);
+	    sim_read (hw_system (me), sram_addr, mmu->dtest_data, 8);
 	}
       break;
     default:
-- 
2.43.0

[PATCH 04/15] sim: common: fix -Wshadow=local warnings

[Mike Frysinger]

Rename shadowed vars with different types, and delete redundant decls.
---
 sim/common/sim-fpu.c     | 4 ++--
 sim/common/sim-options.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index 491a99b7212e..4ee26723ee26 100644
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -413,9 +413,9 @@ unpack_fpu (sim_fpu *dst, uint64_t packed, int is_double)
       }
     else
       {
-	uint32_t val = pack_fpu (dst, 0);
+	uint32_t fval = pack_fpu (dst, 0);
 	uint32_t org = packed;
-	ASSERT (val == org);
+	ASSERT (fval == org);
       }
   }
 }
diff --git a/sim/common/sim-options.c b/sim/common/sim-options.c
index 9f238339fb8f..c695db687cb1 100644
--- a/sim/common/sim-options.c
+++ b/sim/common/sim-options.c
@@ -496,7 +496,7 @@ standard_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
 
     case OPTION_ENV_UNSET:
       {
-	int i, varlen;
+	int varlen;
 	char **envp;
 
 	if (STATE_PROG_ENVP (sd) == NULL)
-- 
2.43.0

[PATCH 05/15] sim: cris: fix -Wshadow=local warnings

[Mike Frysinger]

Delete redundant local decls.
---
 sim/cris/mloop.in | 1 -
 sim/cris/sim-if.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/sim/cris/mloop.in b/sim/cris/mloop.in
index d0f3ee534167..9e3147a917f0 100644
--- a/sim/cris/mloop.in
+++ b/sim/cris/mloop.in
@@ -234,7 +234,6 @@ cat <<EOF
 	     for invalid programs.  */
 	  if (insn != 0 && CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
 	    {
-	      UHI insn;
 	      trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
 	      profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
 	      befaft_p = profile_p || trace_p;
diff --git a/sim/cris/sim-if.c b/sim/cris/sim-if.c
index 06803687ec7c..3919df0381ae 100644
--- a/sim/cris/sim-if.c
+++ b/sim/cris/sim-if.c
@@ -761,7 +761,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
       int len = strlen (name) + 1;
       USI epp, epp0;
       USI stacklen;
-      int i;
       char **prog_argv = STATE_PROG_ARGV (sd);
       int my_argc = 0;
       USI csp;
-- 
2.43.0

[PATCH 06/15] sim: erc32: fix -Wshadow=local warnings

[Mike Frysinger]

Rename shadowed vars with different types to avoid confusion.
---
 sim/erc32/exec.c | 63 ++++++++++++++++++++++++------------------------
 1 file changed, 31 insertions(+), 32 deletions(-)

diff --git a/sim/erc32/exec.c b/sim/erc32/exec.c
index 10a9dae603c0..c8186df02f1d 100644
--- a/sim/erc32/exec.c
+++ b/sim/erc32/exec.c
@@ -707,7 +707,7 @@ dispatch_instruction(struct pstate *sregs)
 	    case DIVScc:
 		{
 		  int sign;
-		  uint32_t result, remainder;
+		  uint32_t uresult, remainder;
 		  int c0, y31;
 
 		  if (!sparclite) {
@@ -723,7 +723,7 @@ dispatch_instruction(struct pstate *sregs)
 		     Otherwise, calculate remainder + divisor.  */
 		  if (sign == 0)
 		    operand2 = ~operand2 + 1;
-		  result = remainder + operand2;
+		  uresult = remainder + operand2;
 
 		  /* The SPARClite User's Manual is not clear on how
 		     the "carry out" of the above ALU operation is to
@@ -733,24 +733,23 @@ dispatch_instruction(struct pstate *sregs)
 		     even in cases where the divisor is subtracted
 		     from the remainder.  FIXME: get the true story
 		     from Fujitsu. */
-		  c0 = result < (uint32_t) remainder
-		       || result < (uint32_t) operand2;
+		  c0 = uresult < remainder || uresult < (uint32_t) operand2;
 
-		  if (result & 0x80000000)
+		  if (uresult & 0x80000000)
 		    sregs->psr |= PSR_N;
 		  else
 		    sregs->psr &= ~PSR_N;
 
 		  y31 = (sregs->y & 0x80000000) == 0x80000000;
 
-		  if (result == 0 && sign == y31)
+		  if (uresult == 0 && sign == y31)
 		    sregs->psr |= PSR_Z;
 		  else
 		    sregs->psr &= ~PSR_Z;
 
 		  sign = (sign && !y31) || (!c0 && (sign || !y31));
 
-		  if (sign ^ (result >> 31))
+		  if (sign ^ (uresult >> 31))
 		    sregs->psr |= PSR_V;
 		  else
 		    sregs->psr &= ~PSR_V;
@@ -760,7 +759,7 @@ dispatch_instruction(struct pstate *sregs)
 		  else
 		    sregs->psr &= ~PSR_C;
 
-		  sregs->y = result;
+		  sregs->y = uresult;
 
 		  if (rd != 0)
 		    *rdd = (rs1 << 1) | !sign;
@@ -773,21 +772,21 @@ dispatch_instruction(struct pstate *sregs)
 		break;
 	    case SMULCC:
 		{
-		  uint32_t result;
+		  uint32_t uresult;
 
-		  mul64 (rs1, operand2, &sregs->y, &result, 1);
+		  mul64 (rs1, operand2, &sregs->y, &uresult, 1);
 
-		  if (result & 0x80000000)
+		  if (uresult & 0x80000000)
 		    sregs->psr |= PSR_N;
 		  else
 		    sregs->psr &= ~PSR_N;
 
-		  if (result == 0)
+		  if (uresult == 0)
 		    sregs->psr |= PSR_Z;
 		  else
 		    sregs->psr &= ~PSR_Z;
 
-		  *rdd = result;
+		  *rdd = uresult;
 		}
 		break;
 	    case UMUL:
@@ -797,21 +796,21 @@ dispatch_instruction(struct pstate *sregs)
 		break;
 	    case UMULCC:
 		{
-		  uint32_t result;
+		  uint32_t uresult;
 
-		  mul64 (rs1, operand2, &sregs->y, &result, 0);
+		  mul64 (rs1, operand2, &sregs->y, &uresult, 0);
 
-		  if (result & 0x80000000)
+		  if (uresult & 0x80000000)
 		    sregs->psr |= PSR_N;
 		  else
 		    sregs->psr &= ~PSR_N;
 
-		  if (result == 0)
+		  if (uresult == 0)
 		    sregs->psr |= PSR_Z;
 		  else
 		    sregs->psr &= ~PSR_Z;
 
-		  *rdd = result;
+		  *rdd = uresult;
 		}
 		break;
 	    case SDIV:
@@ -831,7 +830,7 @@ dispatch_instruction(struct pstate *sregs)
 		break;
 	    case SDIVCC:
 		{
-		  uint32_t result;
+		  uint32_t uresult;
 
 		  if (sparclite) {
 		     sregs->trap = TRAP_UNIMP;
@@ -843,14 +842,14 @@ dispatch_instruction(struct pstate *sregs)
 		    break;
 		  }
 
-		  div64 (sregs->y, rs1, operand2, &result, 1);
+		  div64 (sregs->y, rs1, operand2, &uresult, 1);
 
-		  if (result & 0x80000000)
+		  if (uresult & 0x80000000)
 		    sregs->psr |= PSR_N;
 		  else
 		    sregs->psr &= ~PSR_N;
 
-		  if (result == 0)
+		  if (uresult == 0)
 		    sregs->psr |= PSR_Z;
 		  else
 		    sregs->psr &= ~PSR_Z;
@@ -858,7 +857,7 @@ dispatch_instruction(struct pstate *sregs)
 		  /* FIXME: should set overflow flag correctly.  */
 		  sregs->psr &= ~(PSR_C | PSR_V);
 
-		  *rdd = result;
+		  *rdd = uresult;
 		}
 		break;
 	    case UDIV:
@@ -878,7 +877,7 @@ dispatch_instruction(struct pstate *sregs)
 		break;
 	    case UDIVCC:
 		{
-		  uint32_t result;
+		  uint32_t uresult;
 
 		  if (sparclite) {
 		     sregs->trap = TRAP_UNIMP;
@@ -890,14 +889,14 @@ dispatch_instruction(struct pstate *sregs)
 		    break;
 		  }
 
-		  div64 (sregs->y, rs1, operand2, &result, 0);
+		  div64 (sregs->y, rs1, operand2, &uresult, 0);
 
-		  if (result & 0x80000000)
+		  if (uresult & 0x80000000)
 		    sregs->psr |= PSR_N;
 		  else
 		    sregs->psr &= ~PSR_N;
 
-		  if (result == 0)
+		  if (uresult == 0)
 		    sregs->psr |= PSR_Z;
 		  else
 		    sregs->psr &= ~PSR_Z;
@@ -905,7 +904,7 @@ dispatch_instruction(struct pstate *sregs)
 		  /* FIXME: should set overflow flag correctly.  */
 		  sregs->psr &= ~(PSR_C | PSR_V);
 
-		  *rdd = result;
+		  *rdd = uresult;
 		}
 		break;
 	    case IXNOR:
@@ -1168,7 +1167,7 @@ dispatch_instruction(struct pstate *sregs)
 
 	    case SCAN:
 		{
-		  uint32_t result, mask;
+		  uint32_t uresult, mask;
 		  int i;
 
 		  if (!sparclite) {
@@ -1176,12 +1175,12 @@ dispatch_instruction(struct pstate *sregs)
                      break;
 		  }
 		  mask = (operand2 & 0x80000000) | (operand2 >> 1);
-		  result = rs1 ^ mask;
+		  uresult = rs1 ^ mask;
 
 		  for (i = 0; i < 32; i++) {
-		    if (result & 0x80000000)
+		    if (uresult & 0x80000000)
 		      break;
-		    result <<= 1;
+		    uresult <<= 1;
 		  }
 
 		  *rdd = i == 32 ? 63 : i;
-- 
2.43.0

[PATCH 07/15] sim: frv: fix -Wshadow=local warnings

[Mike Frysinger]

Delete redundant decls, and rename conflicting vars.
---
 sim/frv/interrupts.c | 1 -
 sim/frv/options.c    | 6 +++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/sim/frv/interrupts.c b/sim/frv/interrupts.c
index 979360738bab..8faab5fe0db9 100644
--- a/sim/frv/interrupts.c
+++ b/sim/frv/interrupts.c
@@ -887,7 +887,6 @@ set_exception_status_registers (
 	  break;
 	default:
 	  {
-	    SIM_DESC sd = CPU_STATE (current_cpu);
 	    IADDR pc = CPU_PC_GET (current_cpu);
 	    sim_engine_abort (sd, current_cpu, pc,
 			      "invalid non-strict program interrupt kind: %d\n",
diff --git a/sim/frv/options.c b/sim/frv/options.c
index cb1729b9c403..d6425002901f 100644
--- a/sim/frv/options.c
+++ b/sim/frv/options.c
@@ -212,9 +212,9 @@ frv_option_handler (SIM_DESC sd, sim_cpu *current_cpu, int opt,
 	  }
 	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 	  {
-	    SIM_CPU *current_cpu = STATE_CPU (sd, i);
-	    FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu);
-	    FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu);
+	    SIM_CPU *cpu = STATE_CPU (sd, i);
+	    FRV_CACHE *insn_cache = CPU_INSN_CACHE (cpu);
+	    FRV_CACHE *data_cache = CPU_DATA_CACHE (cpu);
 	    insn_cache->memory_latency = cycles;
 	    data_cache->memory_latency = cycles;
 	  }
-- 
2.43.0

[PATCH 08/15] sim: h8300: fix -Wshadow=local warnings

[Mike Frysinger]

Delete conflicting decls when the existing scope has vars of the same
name & type for this exact use.
---
 sim/h8300/compile.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 8ae7757ee1b1..cfa6eeead5c1 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -1738,7 +1738,7 @@ init_pointers (SIM_DESC sd)
 #define OBITOP(name, f, s, op) 			\
 case O (name, SB):				\
 {						\
-  int m, tmp;					\
+  int m;					\
 	 					\
   if (f)					\
     if (fetch (sd, &code->dst, &ea))		\
@@ -4770,7 +4770,7 @@ sim_open (SIM_OPEN_KIND kind,
   /* CPU specific initialization.  */
   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
     {
-      SIM_CPU *cpu = STATE_CPU (sd, i);
+      cpu = STATE_CPU (sd, i);
 
       CPU_REG_FETCH (cpu) = h8300_reg_fetch;
       CPU_REG_STORE (cpu) = h8300_reg_store;
-- 
2.43.0

[PATCH 09/15] sim: iq2000: fix -Wshadow=local warnings

[Mike Frysinger]

Delete redundant decls.
---
 sim/iq2000/mloop.in | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sim/iq2000/mloop.in b/sim/iq2000/mloop.in
index 1d3df32ee777..9ffa167de2e8 100644
--- a/sim/iq2000/mloop.in
+++ b/sim/iq2000/mloop.in
@@ -191,7 +191,7 @@ cat <<EOF
 
           if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
 	    {
-              USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
+              insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
 	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
 
               if (likely_cti && IDESC_CTI_P (idesc))
-- 
2.43.0

[PATCH 10/15] sim: m68hc11: fix -Wshadow=local warnings

[Mike Frysinger]

Delete redundant decls when the existing scope has the same var and
type available for use.
---
 sim/m68hc11/dv-m68hc11.c    | 3 +--
 sim/m68hc11/dv-m68hc11sio.c | 2 +-
 sim/m68hc11/interp.c        | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/sim/m68hc11/dv-m68hc11.c b/sim/m68hc11/dv-m68hc11.c
index ef18f0999360..fc8b22cede3f 100644
--- a/sim/m68hc11/dv-m68hc11.c
+++ b/sim/m68hc11/dv-m68hc11.c
@@ -782,7 +782,6 @@ m68hc11_option_handler (SIM_DESC sd, sim_cpu *cpu,
           osc = &controller->oscillators[i];
           if (osc->event)
             {
-              double f;
               int cur_value;
               int next_value;
               char freq[32];
@@ -927,7 +926,7 @@ m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
       /* Scan IC3, IC2 and IC1.  Bit number is 3 - i.  */
       for (i = 0; i < 3; i++)
         {
-          uint8_t mask = (1 << i);
+          mask = (1 << i);
           
           if (delta & mask)
             {
diff --git a/sim/m68hc11/dv-m68hc11sio.c b/sim/m68hc11/dv-m68hc11sio.c
index 03b44613c180..f77dfdec1f99 100644
--- a/sim/m68hc11/dv-m68hc11sio.c
+++ b/sim/m68hc11/dv-m68hc11sio.c
@@ -227,7 +227,7 @@ m68hc11sio_port_event (struct hw *me,
            simulate some initial setup by the internal rom.  */
         if (((m68hc11_cpu->ios[M6811_HPRIO]) & (M6811_SMOD | M6811_MDA)) == M6811_SMOD)
           {
-            unsigned char val = 0x33;
+            val = 0x33;
             
             m68hc11sio_io_write_buffer (me, &val, io_map,
                                         (unsigned_word) M6811_BAUD, 1);
diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c
index df6bd7bea565..c4d5c22fa075 100644
--- a/sim/m68hc11/interp.c
+++ b/sim/m68hc11/interp.c
@@ -478,7 +478,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback,
   /* CPU specific initialization.  */
   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
     {
-      SIM_CPU *cpu = STATE_CPU (sd, i);
+      cpu = STATE_CPU (sd, i);
 
       CPU_REG_FETCH (cpu) = m68hc11_reg_fetch;
       CPU_REG_STORE (cpu) = m68hc11_reg_store;
-- 
2.43.0

[PATCH 11/15] sim: mips: fix -Wshadow=local warnings

[Mike Frysinger]

Delete redundant decls when the existing scope has the same var and
type available for use.
---
 sim/mips/interp.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 708e27f6b2b7..b15b228600c2 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -184,7 +184,7 @@ mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
 	 etc.). */
       for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
 	{
-	  sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+	  cpu = STATE_CPU (sd, cpu_nr);
 	  if (arg == NULL)
 	    STATE |= simTRACE;
 	  else if (strcmp (arg, "yes") == 0)
@@ -448,8 +448,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   else if (board != NULL
 	   && (strcmp(board, BOARD_BSP) == 0))
     {
-      int i;
-
       STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
 
       /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
@@ -481,7 +479,6 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
 	       strcmp(board, BOARD_JMR3904_DEBUG) == 0))
     {
       /* match VIRTUAL memory layout of JMR-TX3904 board */
-      int i;
 
       /* --- disable monitor unless forced on by user --- */
 
@@ -805,7 +802,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
   /* CPU specific initialization.  */
   for (i = 0; i < MAX_NR_PROCESSORS; ++i)
     {
-      SIM_CPU *cpu = STATE_CPU (sd, i);
+      cpu = STATE_CPU (sd, i);
 
       CPU_REG_FETCH (cpu) = mips_reg_fetch;
       CPU_REG_STORE (cpu) = mips_reg_store;
-- 
2.43.0

[PATCH 12/15] sim: ppc: fix -Wshadow=local warnings

[Mike Frysinger]

Use a local name in the macro to avoid shadowing wherever it's used.
---
 sim/ppc/debug.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sim/ppc/debug.h b/sim/ppc/debug.h
index 08ea5795fd89..28e42c7bb753 100644
--- a/sim/ppc/debug.h
+++ b/sim/ppc/debug.h
@@ -125,14 +125,14 @@ do { \
 #define DITRACE(OBJECT, ARGS) \
 do { \
   if (WITH_TRACE) { \
-    device *me = device_instance_device(instance); \
-    int trace_device = device_trace(me); \
+    device *_me = device_instance_device(instance); \
+    int trace_device = device_trace(_me); \
     if (ppc_trace[trace_devices] \
 	|| ppc_trace[trace_##OBJECT##_device] \
 	|| trace_device) { \
       sim_io_printf_filtered("%s:%d:%s:%s%s ", \
 			     filter_filename(__FILE__), __LINE__, #OBJECT, \
-			     trace_device ? device_path(me) : "",	\
+			     trace_device ? device_path(_me) : "",	\
 			     trace_device ? ":" : "");			\
       sim_io_printf_filtered ARGS; \
     } \
-- 
2.43.0

[PATCH 13/15] sim: riscv: fix -Wshadow=local warnings

[Mike Frysinger]

Inline the one usage of sd in these macros to avoid possible shadowing.
---
 sim/riscv/sim-main.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4d2053453950..b04d12c0de1c 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -48,10 +48,9 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   do { \
     if (RISCV_XLEN (cpu) != 32) \
       { \
-	SIM_DESC sd = CPU_STATE (cpu); \
 	TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \
-	sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \
-			 SIM_SIGILL); \
+	sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \
+			 sim_signalled, SIM_SIGILL); \
       } \
   } while (0)
 
@@ -59,10 +58,9 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   do { \
     if (RISCV_XLEN (cpu) != 64) \
       { \
-	SIM_DESC sd = CPU_STATE (cpu); \
 	TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \
-	sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \
-			 SIM_SIGILL); \
+	sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \
+			 sim_signalled, SIM_SIGILL); \
       } \
   } while (0)
 
-- 
2.43.0

[PATCH 14/15] sim: sh: fix -Wshadow=local warnings

[Mike Frysinger]

Rename the var to avoid shadowing & clobbering the higher context.
---
 sim/sh/interp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 01d7a1c7be91..bbf26bb11893 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -1046,8 +1046,8 @@ trap (SIM_DESC sd, int i, int *regs, unsigned char *insn_ptr,
 	    if (regs[5] < countargv (prog_argv))
 	      {
 		/* Include the termination byte.  */
-		int i = strlen (prog_argv[regs[5]]) + 1;
-		regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], i);
+		int len = strlen (prog_argv[regs[5]]) + 1;
+		regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], len);
 	      }
 	    else
 	      regs[0] = -1;
-- 
2.43.0

[PATCH 15/15] sim: warnings: enable -Wshadow=local

[Mike Frysinger]

This brings us in sync with current set of gdb warnings (for C).
---
 sim/configure                    | 1 +
 sim/m4/sim_ac_option_warnings.m4 | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/sim/m4/sim_ac_option_warnings.m4 b/sim/m4/sim_ac_option_warnings.m4
index faa7198a29b2..dca507076f55 100644
--- a/sim/m4/sim_ac_option_warnings.m4
+++ b/sim/m4/sim_ac_option_warnings.m4
@@ -46,7 +46,7 @@ dnl C++ -Wno-mismatched-tags
 dnl C++ -Wsuggest-override
 -Wimplicit-fallthrough=5
 -Wduplicated-cond
-dnl -Wshadow=local
+-Wshadow=local
 dnl C++ -Wdeprecated-copy
 dnl C++ -Wdeprecated-copy-dtor
 dnl C++ -Wredundant-move
-- 
2.43.0

Re: [PATCH 15/15] sim: warnings: enable -Wshadow=local

[Tom Tromey]

>>>>> "Mike" == Mike Frysinger <vapier@gentoo.org> writes:

Mike> This brings us in sync with current set of gdb warnings (for C).

FWIW I skimmed this series and it all looked reasonable to me.  I think
it's worth applying.  IIRC in gdb the shadow warning found a few real
bugs, so even if it didn't help the sim immediately, it can still be
helpful as bug prevention.

Tom

[PATCH] sim: m32c: fix -Wshadow=local warnings

[Mike Frysinger]

These decoders declare a lot of common variables for use by substeps,
and then shadows a few because of how the opc generator is implemented.
Easiest way around it is to rename the per-substep vars as needed as
anything more would require substantial changes to the opc logic.
---
 sim/m32c/m32c.opc | 13 +++++--------
 sim/m32c/r8c.opc  |  8 ++++----
 2 files changed, 9 insertions(+), 12 deletions(-)

diff --git a/sim/m32c/m32c.opc b/sim/m32c/m32c.opc
index cc6ef9fbc576..02c894d216b0 100644
--- a/sim/m32c/m32c.opc
+++ b/sim/m32c/m32c.opc
@@ -728,11 +728,11 @@ next_opcode:
   b = get_bit2 (sc, bit);
   set_zc (!b, b);
 
-  /** 00bb 101b				BTST:S src */
+  /** 00bb 101bit			BTST:S src */
 
   sc = decode_src23 (3, 3, 1); /* bit,base:19 */
-  b = get_bit2 (sc, bb*2 + b);
-  set_zc (!b, b);
+  bit = get_bit2 (sc, bb*2 + bit);
+  set_zc (!bit, bit);
 
   /** 1101 ddd0 dd10 0bit		BTSTC dest */
 
@@ -1170,9 +1170,9 @@ next_opcode:
 
   NOTYET();
 
-  /** 1101 0101 1110 1imm		LDIPL #IMM */
+  /** 1101 0101 1110 1flg		LDIPL #IMM */
 
-  set_flags (0x7000, imm*0x1000);
+  set_flags (0x7000, flg*0x1000);
 
   /** 0000 0001 1000 ddd w dd11 1111	MAX.size #IMM,dest */
 
@@ -1589,8 +1589,6 @@ next_opcode:
 
   /** 1010 111w				PUSH.size #IMM */
 
-  {
-  int a;
   prefix (0, 0, 0);
   imm = IMM(w+1);
   tprintf("push%s: %x\n", w ? "hi" : "qi", imm);
@@ -1600,7 +1598,6 @@ next_opcode:
   else
     mem_put_qi (a, imm);
   put_reg (sp, a);
-  }
 
   /** 1100 sss w ss00 1110		PUSH.size src */
 
diff --git a/sim/m32c/r8c.opc b/sim/m32c/r8c.opc
index c5d8929f6ab9..9c35e13f0c5d 100644
--- a/sim/m32c/r8c.opc
+++ b/sim/m32c/r8c.opc
@@ -880,9 +880,9 @@ decode_r8c (void)
     v = mem_get_qi (imm);
   put_dest (dc, v);
 
-  /** 0111 1101 1010 0imm  LDIPL #IMM */
+  /** 0111 1101 1010 0flg  LDIPL #IMM */
 
-  set_flags (0x700, imm*0x100);
+  set_flags (0x700, flg*0x100);
 
   /** 0111 010w 1100 dest  MOV.size:G #IMM,dest */
 
@@ -1380,13 +1380,13 @@ decode_r8c (void)
   a = sign_ext (get_reg (r1h), 8);
   shift_op (dc, 0, a);
 
-  /** 0111 110w 1110 100b  SMOVB.size */
+  /** 0111 110w 1110 100z  SMOVB.size */
 
   {
   int count = get_reg (r3);
   int s1 = get_reg (a0) + (get_reg (r1h) << 16);
   int s2 = get_reg (a1);
-  int inc = (w ? 2 : 1) * (b ? -1 : 1);
+  int inc = (w ? 2 : 1) * (z ? -1 : 1);
 
   while (count)
     {
-- 
2.43.0

[PATCH] sim: cris: disable -Wshadow=local in generated mloop files

[Mike Frysinger]

The mloop files include CGEN generated switch files which have some
nested assignments that expand into repeated shadowed variables.
Fixing this looks fairly non-trivial as it appears to be interplay
between the common CGEN code and how this particular set of cris
insns are defined.  Disable the warning instead.

In file included from sim/cris/mloop.in:286:
sim/cris/semcrisv10f-switch.c: In function ‘crisv10f_engine_run_full’:
sim/cris/semcrisv10f-switch.c:12383:8: error: declaration of ‘opval’ shadows a previous local [-Werror=shadow=local]
12383 |     SI opval = tmp_addr;
      |        ^~~~~
sim/cris/semcrisv10f-switch.c:12371:9: note: shadowed declaration is here
12371 |     USI opval = ({   SI tmp_addr;
      |         ^~~~~

And the code looks like:
	USI opval = ({
		...
			{
				SI opval = tmp_addr;
				...
			}
		...
	});

Since the CGEN code treats "opval" as an internal variable that the cpu
definitions don't have direct access to, the likelihood of this being a
real bug is low, so leave it be.  The warning is suppressed for more code
that is hand written (e.g. the mloop logic), but disabling for the entire
file is the easiest way to suppress while keeping it on everywhere else in
the sim.
---
 sim/Makefile.in   | 4 +++-
 sim/cris/local.mk | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/sim/Makefile.in b/sim/Makefile.in
index 604732c698c5..6b73533f9db3 100644
--- a/sim/Makefile.in
+++ b/sim/Makefile.in
@@ -2160,7 +2160,9 @@ testsuite_common_CPPFLAGS = \
 
 @SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
 @SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
-@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = -Wno-unused-but-set-variable
+@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o =  \
+@SIM_ENABLE_ARCH_cris_TRUE@	-Wno-unused-but-set-variable \
+@SIM_ENABLE_ARCH_cris_TRUE@	-Wno-shadow=local
 @SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = -Wno-unused-but-set-variable
 @SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \
 @SIM_ENABLE_ARCH_cris_TRUE@	cris/modules.c
diff --git a/sim/cris/local.mk b/sim/cris/local.mk
index 011f8029e49f..a8eea65572ad 100644
--- a/sim/cris/local.mk
+++ b/sim/cris/local.mk
@@ -19,6 +19,8 @@
 ## Some CGEN kludges are causing build-time warnings.  See cris.cpu for details.
 AM_CFLAGS_%C%_mloopv10f.o = -Wno-unused-but-set-variable
 AM_CFLAGS_%C%_mloopv32f.o = -Wno-unused-but-set-variable
+## Some CGEN assignments use variable names that are nested & repeated.
+AM_CFLAGS_%C%_mloopv10f.o += -Wno-shadow=local
 
 nodist_%C%_libsim_a_SOURCES = \
 	%D%/modules.c
-- 
2.43.0