[Bug libc/30643] New: Missing cache information on x86-64 under Intel TDX

[Bug libc/30643] New: Missing cache information on x86-64 under Intel TDX

[fweimer at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

            Bug ID: 30643
           Summary: Missing cache information on x86-64 under Intel TDX
           Product: glibc
           Version: unspecified
            Status: NEW
          Severity: normal
          Priority: P2
         Component: libc
          Assignee: unassigned at sourceware dot org
          Reporter: fweimer at redhat dot com
                CC: drepper.fsp at gmail dot com
  Target Milestone: ---
             Flags: security-

Bug 30037 has further consequences. While the immediate crash was fixed fixed
via bug 29953, glibc still does not produce correct cache geometry information
this case:

# getconf -a | grep CACHE
LEVEL1_ICACHE_SIZE                 0
LEVEL1_ICACHE_ASSOC                
LEVEL1_ICACHE_LINESIZE             0
LEVEL1_DCACHE_SIZE                 0
LEVEL1_DCACHE_ASSOC                0
LEVEL1_DCACHE_LINESIZE             0
LEVEL2_CACHE_SIZE                  0
LEVEL2_CACHE_ASSOC                 0
LEVEL2_CACHE_LINESIZE              0
LEVEL3_CACHE_SIZE                  0
LEVEL3_CACHE_ASSOC                 0
LEVEL3_CACHE_LINESIZE              0
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 
LEVEL4_CACHE_LINESIZE              

Some of these values are used for splitting arrays for processing, so a value
of 0 can result in an endless loop or a division-by-zero trap.

The information is apparently available somewhere else via CPUID, but the EAX=2
query is commonly used directly by applications, so it's not really clear to me
that a glibc fix is sufficient.

The following data is from an Azure TDX instance, share with permission.

# /usr/bin/cpuid -1 -r  
CPU:
   0x00000000 0x00: eax=0x00000021 ebx=0x756e6547 ecx=0x6c65746e edx=0x49656e69
   0x00000001 0x00: eax=0x000806f8 ebx=0x00020800 ecx=0xfffaba17 edx=0x1fabfbff
   0x00000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000004 0x00: eax=0x00004121 ebx=0x02c0003f ecx=0x0000003f edx=0x00000000
   0x00000004 0x01: eax=0x00004122 ebx=0x01c0003f ecx=0x0000003f edx=0x00000000
   0x00000004 0x02: eax=0x00004143 ebx=0x03c0003f ecx=0x000007ff edx=0x00000000
   0x00000004 0x03: eax=0x00004163 ebx=0x0380003f ecx=0x0001bfff edx=0x00000000
   0x00000004 0x04: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000005 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000007 0x00: eax=0x00000001 ebx=0xf1bf2ff9 ecx=0x1b415fe6 edx=0xffd14410
   0x00000007 0x01: eax=0x00001c30 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000000c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000000d 0x00: eax=0x000600e7 ebx=0x00002b00 ecx=0x00002b00 edx=0x00000000
   0x0000000d 0x01: eax=0x0000001f ebx=0x000029c0 ecx=0x00001800 edx=0x00000000
   0x0000000d 0x02: eax=0x00000100 ebx=0x00000240 ecx=0x00000000 edx=0x00000000
   0x0000000d 0x05: eax=0x00000040 ebx=0x00000440 ecx=0x00000000 edx=0x00000000
   0x0000000d 0x06: eax=0x00000200 ebx=0x00000480 ecx=0x00000000 edx=0x00000000
   0x0000000d 0x07: eax=0x00000400 ebx=0x00000680 ecx=0x00000000 edx=0x00000000
   0x0000000d 0x0b: eax=0x00000010 ebx=0x00000000 ecx=0x00000001 edx=0x00000000
   0x0000000d 0x0c: eax=0x00000018 ebx=0x00000000 ecx=0x00000001 edx=0x00000000
   0x0000000d 0x11: eax=0x00000040 ebx=0x00000ac0 ecx=0x00000002 edx=0x00000000
   0x0000000d 0x12: eax=0x00002000 ebx=0x00000b00 ecx=0x00000006 edx=0x00000000
   0x0000000e 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000000f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000010 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000011 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000012 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000012 0x01: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000012 0x02: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000013 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000014 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000015 0x00: eax=0x00000001 ebx=0x00000054 ecx=0x017d7840 edx=0x00000000
   0x00000016 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000017 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000018 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000019 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001b 0x01: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001c 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001d 0x00: eax=0x00000001 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001d 0x01: eax=0x04002000 ebx=0x00080040 ecx=0x00000010 edx=0x00000000
   0x0000001e 0x00: eax=0x00000000 ebx=0x00004010 ecx=0x00000000 edx=0x00000000
   0x0000001f 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x0000001f 0x01: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000020 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x00000021 0x00: eax=0x00000000 ebx=0x65746e49 ecx=0x20202020 edx=0x5844546c
   0x20000000 0x00: eax=0x00000000 ebx=0x65746e49 ecx=0x20202020 edx=0x5844546c
   0x40000000 0x00: eax=0x4000000c ebx=0x7263694d ecx=0x666f736f edx=0x76482074
   0x40000001 0x00: eax=0x31237648 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x40000002 0x00: eax=0x0000585d ebx=0x000a0000 ecx=0x00000001 edx=0x00000447
   0x40000003 0x00: eax=0x0000ae7f ebx=0x00628030 ecx=0x00000002 edx=0xe0be47a2
   0x40000004 0x00: eax=0x00360e24 ebx=0x00000fff ecx=0x00000034 edx=0x00000000
   0x40000005 0x00: eax=0x00000800 ebx=0x00000800 ecx=0x00009720 edx=0x00000000
   0x40000006 0x00: eax=0x0000000f ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x40000007 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x40000008 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x40000009 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x4000000a 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x4000000b 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x4000000c 0x00: eax=0x00000000 ebx=0x00000003 ecx=0x00000000 edx=0x00000000
   0x40000100 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000000 0x00: eax=0x80000008 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000001 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000121 edx=0x2c100800
   0x80000002 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000003 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000004 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000005 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000006 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000007 0x00: eax=0x00000000 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
   0x80000008 0x00: eax=0x00003934 ebx=0x00000200 ecx=0x00000000 edx=0x00000000
   0x80860000 0x00: eax=0x00000000 ebx=0x65746e49 ecx=0x20202020 edx=0x5844546c
   0xc0000000 0x00: eax=0x00000000 ebx=0x65746e49 ecx=0x20202020 edx=0x5844546c

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[fweimer at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

Florian Weimer <fweimer at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |fweimer at redhat dot com

--- Comment #1 from Florian Weimer <fweimer at redhat dot com> ---
Raised on libc-alpha and elsewhere:

Missing cache information on x86-64 under Intel TDX (glibc bug 30643)
<https://sourceware.org/pipermail/libc-alpha/2023-July/150115.html>

This quick hack produces more reasonable values:

# bash testrun.sh posix/getconf -a | grep CACHE
LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 49152
LEVEL1_DCACHE_ASSOC                12
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  2097152
LEVEL2_CACHE_ASSOC                 16
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  110100480
LEVEL3_CACHE_ASSOC                 15
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 
LEVEL4_CACHE_LINESIZE              

diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
index c98fa57a..814a314b 100644
--- a/sysdeps/x86/dl-cacheinfo.h
+++ b/sysdeps/x86/dl-cacheinfo.h
@@ -271,6 +271,10 @@ handle_intel (int name, const struct cpu_features
*cpu_features)
       unsigned int edx;
       __cpuid (2, eax, ebx, ecx, edx);

+      if (eax == 0 && ebx == 0 && ecx == 0 && edx == 0)
+       /* Redirect to other information source for Intel TDX.  */
+       eax = 0xff;
+
       /* The low byte of EAX in the first round contain the number of
         rounds we have to make.  At least one, the one we are already
         doing.  */

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[decui at microsoft dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

Dexuan Cui <decui at microsoft dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |decui at microsoft dot com

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[fweimer at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

Florian Weimer <fweimer at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://github.com/intel/td
                   |                            |x/issues/3

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[fweimer at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

Florian Weimer <fweimer at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           See Also|                            |https://bugzilla.redhat.com
                   |                            |/show_bug.cgi?id=2223287

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[hjl.tools at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |hjl.tools at gmail dot com

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[hjl.tools at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at sourceware dot org   |hjl.tools at gmail dot com

--- Comment #2 from H.J. Lu <hjl.tools at gmail dot com> ---
Created attachment 15087
  --> https://sourceware.org/bugzilla/attachment.cgi?id=15087&action=edit
A patch

Florian, can you try this?

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[fweimer at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

--- Comment #3 from Florian Weimer <fweimer at redhat dot com> ---
(In reply to H.J. Lu from comment #2)
> Created attachment 15087 [details]
> A patch
> 
> Florian, can you try this?

I no longer have access to an Azure TDX system to test. I'll see if I can get
another one, or have someone else test a glibc build on one.

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[decui at microsoft dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

--- Comment #4 from Dexuan Cui <decui at microsoft dot com> ---
I own a TDX blade in our lab, which runs a Hyper-V build similar to what is
running on Azure. I can help test a glibc build and run any command in my
virtual machine for you.

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

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--- Comment #5 from H.J. Lu <hjl.tools at gmail dot com> ---
Created attachment 15091
  --> https://sourceware.org/bugzilla/attachment.cgi?id=15091&action=edit
A static getconf

Please run

$ ./getconf-static -a | grep CACHE

and report the output.  Thanks.

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

[decui at microsoft dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

--- Comment #6 from Dexuan Cui <decui at microsoft dot com> ---
My TDX blade is running a Hyper-V dev build (July 26), which should be similar
to the version on Azure.

My Ubuntu 20.04 VM has glibc 2.31-0ubuntu9.9. I'm running this kernel [1] in
the VM: the kernel here means v6.5-rc4 + the patches in the Hyper-V tree's next
branch [2]  + a few other patches. The patches should not affect the values
returned from CPUID)

Hyper-V provides two modes for running Intel TDX VMs [3]:
  Mode A) TD Partitioning mode with a paravisor.
  Mode B) In "fully enlightened" mode with normal TDX shared bit control over
page encryption, and no paravisor.

This is the output for Mode A:
# ./getconf-static -a | grep CACHE
LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 49152
LEVEL1_DCACHE_ASSOC                12
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  2097152
LEVEL2_CACHE_ASSOC                 16
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  110100480
LEVEL3_CACHE_ASSOC                 15
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE
LEVEL4_CACHE_ASSOC
LEVEL4_CACHE_LINESIZE


This is the output for Mode B:
# ./getconf-static -a | grep CACHE
LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 49152
LEVEL1_DCACHE_ASSOC                12
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  2097152
LEVEL2_CACHE_ASSOC                 16
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE
LEVEL3_CACHE_ASSOC
LEVEL3_CACHE_LINESIZE
LEVEL4_CACHE_SIZE
LEVEL4_CACHE_ASSOC
LEVEL4_CACHE_LINESIZE

[1]
https://github.com/dcui/linux/commits/decui/upstream-hyperv/hyperv-next/TDX/0824-with-and-without-HCL
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git/log/?h=hyperv-next
[3]https://lwn.net/ml/linux-kernel/20230824080712.30327-1-decui@microsoft.com/

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--- Comment #7 from Dexuan Cui <decui at microsoft dot com> ---
Sorry, I need to make a correction to my last comment. I confused Mode A and
B...

The correct description is:
  Mode B) TD Partitioning mode with a paravisor.
  Mode A) In "fully enlightened" mode with normal TDX shared bit control over
page encryption, and no paravisor.
(The other part in my last comment still applies)

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--- Comment #8 from Florian Weimer <fweimer at redhat dot com> ---
(In reply to Dexuan Cui from comment #7)
> Sorry, I need to make a correction to my last comment. I confused Mode A and
> B...
> 
> The correct description is:
>   Mode B) TD Partitioning mode with a paravisor.
>   Mode A) In "fully enlightened" mode with normal TDX shared bit control
> over page encryption, and no paravisor.
> (The other part in my last comment still applies)

I was about to ask, given that mode A has more data. 8-)

For comparison, could you also share the output with unpatched glibc (system
getconf should work for that)? Thanks.

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[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

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--- Comment #9 from Dexuan Cui <decui at microsoft dot com> ---
//Mode A) In "fully enlightened" mode with normal TDX shared bit control over
page encryption, and no paravisor.
# getconf  -a | grep CACHE
LEVEL1_ICACHE_SIZE                 0
LEVEL1_ICACHE_ASSOC                0
LEVEL1_ICACHE_LINESIZE             0
LEVEL1_DCACHE_SIZE                 0
LEVEL1_DCACHE_ASSOC                0
LEVEL1_DCACHE_LINESIZE             0
LEVEL2_CACHE_SIZE                  0
LEVEL2_CACHE_ASSOC                 0
LEVEL2_CACHE_LINESIZE              0
LEVEL3_CACHE_SIZE                  0
LEVEL3_CACHE_ASSOC                 0
LEVEL3_CACHE_LINESIZE              0
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0


// Mode B) TD Partitioning mode with a paravisor.
# getconf  -a | grep CACHE
LEVEL1_ICACHE_SIZE                 0
LEVEL1_ICACHE_ASSOC                0
LEVEL1_ICACHE_LINESIZE             0
LEVEL1_DCACHE_SIZE                 0
LEVEL1_DCACHE_ASSOC                0
LEVEL1_DCACHE_LINESIZE             0
LEVEL2_CACHE_SIZE                  0
LEVEL2_CACHE_ASSOC                 0
LEVEL2_CACHE_LINESIZE              0
LEVEL3_CACHE_SIZE                  0
LEVEL3_CACHE_ASSOC                 0
LEVEL3_CACHE_LINESIZE              0
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 0
LEVEL4_CACHE_LINESIZE              0

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--- Comment #10 from Florian Weimer <fweimer at redhat dot com> ---
(In reply to Dexuan Cui from comment #9)
> //Mode A) In "fully enlightened" mode with normal TDX shared bit control
> over page encryption, and no paravisor.

(lots of zeroes)

Okay, so not much has changed on the hypervisor side, which means this test
environment is still valid.

I'm still worried about compatibility impact on applications which invoke CPUID
directly (they might have to be patched in ways similar to glibc). But at least
the glibc patch appears to be working.

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--- Comment #11 from H.J. Lu <hjl.tools at gmail dot com> ---
On Coffee Lake, I got

[hjl@gnu-cfl-3 binutils-gitlab]$ getconf -a | grep CACHE
LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 32768
LEVEL1_DCACHE_ASSOC                8
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  262144
LEVEL2_CACHE_ASSOC                 4
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  12582912
LEVEL3_CACHE_ASSOC                 16
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 
LEVEL4_CACHE_LINESIZE              
[hjl@gnu-cfl-3 binutils-gitlab]$

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--- Comment #12 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=1493622f4f9048ffede3fbedb64695efa49d662a

commit 1493622f4f9048ffede3fbedb64695efa49d662a
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Aug 28 12:08:14 2023 -0700

    x86: Check the lower byte of EAX of CPUID leaf 2 [BZ #30643]

    The old Intel software developer manual specified that the low byte of
    EAX of CPUID leaf 2 returned 1 which indicated the number of rounds of
    CPUDID leaf 2 was needed to retrieve the complete cache information. The
    newer Intel manual has been changed to that it should always return 1
    and be ignored.  If the lower byte isn't 1, CPUID leaf 2 can't be used.
    In this case, we ignore CPUID leaf 2 and use CPUID leaf 4 instead.  If
    CPUID leaf 4 doesn't contain the cache information, cache information
    isn't available at all.  This addresses BZ #30643.

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