From: "Junxian Zhu" <zhujunxian@oss.cipunited.com>
To: "YunQiang Su" <wzssyqa@gmail.com>
Cc: <libc-alpha@sourceware.org>
Subject: Re: [PATCH 2/2] MIPS: Hard-float rounding instructions support
Date: Tue, 2 Jan 2024 17:51:24 +0800 [thread overview]
Message-ID: <00bdff38-7446-4815-bc90-96203e4a473a@oss.cipunited.com> (raw)
In-Reply-To: <CAKcpw6Wt8xcx0Lvz1k3EkDaJVjKnm_AwFNnCpMA139GO+nYnJw@mail.gmail.com>
在 2023/12/25 20:36, YunQiang Su 写道:
>
> Junxian Zhu <zhujunxian@oss.cipunited.com> 于 2023年12月25日周一
> 18:38写道：
>
> From: Junxian Zhu <zhujunxian@oss.cipunited.com>
>
> Use hardware floating-point rounding instructions to implement
> roundeven, trunc, ceil and floor.
>
> * sysdeps/mips/mips32/Implies: Add source path.
> * sysdeps/mips/mips64/Implies: Likewise.
> * sysdeps/mips/fpu/Makefile: Newfile.
> * sysdeps/mips/fpu/s_ceil.c: Likewise.
> * sysdeps/mips/fpu/s_ceil_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_ceilf.c: Likewise.
> * sysdeps/mips/fpu/s_ceilf_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_floor.c: Likewise.
> * sysdeps/mips/fpu/s_floor_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_floorf.c: Likewise.
> * sysdeps/mips/fpu/s_floorf_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_roundeven.c: Likewise.
> * sysdeps/mips/fpu/s_roundeven_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_roundevenf.c: Likewise.
> * sysdeps/mips/fpu/s_roundevenf_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_trunc.c: Likewise.
> * sysdeps/mips/fpu/s_trunc_fpu.S: Likewise.
> * sysdeps/mips/fpu/s_truncf.c: Likewise.
> * sysdeps/mips/fpu/s_truncf_fpu.S: Likewise.
>
> Signed-off-by: Rong Zhang <rongrong@oss.cipunited.com>
> Signed-off-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
> ---
> sysdeps/mips/fpu/Makefile | 12 ++++
> sysdeps/mips/fpu/s_ceil.c | 30 ++++++++++
> sysdeps/mips/fpu/s_ceil_fpu.S | 90
> +++++++++++++++++++++++++++++
> sysdeps/mips/fpu/s_ceilf.c | 30 ++++++++++
> sysdeps/mips/fpu/s_ceilf_fpu.S | 82 ++++++++++++++++++++++++++
> sysdeps/mips/fpu/s_floor.c | 24 ++++++++
> sysdeps/mips/fpu/s_floor_fpu.S | 88 ++++++++++++++++++++++++++++
> sysdeps/mips/fpu/s_floorf.c | 24 ++++++++
> sysdeps/mips/fpu/s_floorf_fpu.S | 80 +++++++++++++++++++++++++
> sysdeps/mips/fpu/s_roundeven.c | 24 ++++++++
> sysdeps/mips/fpu/s_roundeven_fpu.S | 87 ++++++++++++++++++++++++++++
> sysdeps/mips/fpu/s_roundevenf.c | 24 ++++++++
> sysdeps/mips/fpu/s_roundevenf_fpu.S | 79 +++++++++++++++++++++++++
> sysdeps/mips/fpu/s_trunc.c | 24 ++++++++
> sysdeps/mips/fpu/s_trunc_fpu.S | 84 +++++++++++++++++++++++++++
> sysdeps/mips/fpu/s_truncf.c | 24 ++++++++
> sysdeps/mips/fpu/s_truncf_fpu.S | 76 ++++++++++++++++++++++++
> sysdeps/mips/mips32/Implies | 1 +
> sysdeps/mips/mips64/Implies | 1 +
> 19 files changed, 884 insertions(+)
> create mode 100644 sysdeps/mips/fpu/Makefile
> create mode 100644 sysdeps/mips/fpu/s_ceil.c
> create mode 100644 sysdeps/mips/fpu/s_ceil_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_ceilf.c
> create mode 100644 sysdeps/mips/fpu/s_ceilf_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_floor.c
> create mode 100644 sysdeps/mips/fpu/s_floor_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_floorf.c
> create mode 100644 sysdeps/mips/fpu/s_floorf_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_roundeven.c
> create mode 100644 sysdeps/mips/fpu/s_roundeven_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_roundevenf.c
> create mode 100644 sysdeps/mips/fpu/s_roundevenf_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_trunc.c
> create mode 100644 sysdeps/mips/fpu/s_trunc_fpu.S
> create mode 100644 sysdeps/mips/fpu/s_truncf.c
> create mode 100644 sysdeps/mips/fpu/s_truncf_fpu.S
>
> diff --git a/sysdeps/mips/fpu/Makefile b/sysdeps/mips/fpu/Makefile
> new file mode 100644
> index 0000000000..ad537d6bf1
> --- /dev/null
> +++ b/sysdeps/mips/fpu/Makefile
> @@ -0,0 +1,12 @@
> +ifeq ($(subdir),math)
> +sysdep_routines += s_floor_fpu s_floorf_fpu \
> + s_ceil_fpu s_ceilf_fpu \
> + s_trunc_fpu s_truncf_fpu \
> + s_roundeven_fpu s_roundevenf_fpu
> +
> +libm-sysdep_routines += s_floor_fpu s_floorf_fpu \
> + s_ceil_fpu s_ceilf_fpu \
> + s_trunc_fpu s_truncf_fpu \
> + s_roundeven_fpu s_roundevenf_fpu
> +
> +endif
> diff --git a/sysdeps/mips/fpu/s_ceil.c b/sysdeps/mips/fpu/s_ceil.c
> new file mode 100644
> index 0000000000..91a90a70c5
> --- /dev/null
> +++ b/sysdeps/mips/fpu/s_ceil.c
> @@ -0,0 +1,30 @@
> +/* Copyright (C) 2023 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be
> useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library. If not, see
> + <https://www.gnu.org/licenses/>. */
> +
> +/*
> + * ceil(x)
> + * Return x rounded toward -inf to integral value
> + * Method:
> + * Bit twiddling.
> + */
> +
> +#if !((__mips_fpr == 64) && (__mips_hard_float == 1)
> \
> + && ((__mips == 32 && __mips_isa_rev > 1) || __mips == 64))
> +
>
>
> __mips_fpr == 64
> this condition should not be here.
> it means fp64.
> In fact your code should also support fp32 and fpxx.
>
The MIPS instruction documentation has specifies restrictions for the
ceil, round, floor and trunc. "The result of this instruction is
UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU
register model; it is predictable if executing on a 64-bit FPU in the
FR=1 mode, but not with FR=0, and not on a 32-bit FPU."
And fp64 ABI is the only configuration that restricts FPU work in FR=1
mode.
next prev parent reply other threads:[~2024-01-02 9:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-25 10:35 [PATCH 0/2] Add hard-float rounding instructions support for MIPS architecture Junxian Zhu
2023-12-25 10:35 ` [PATCH 1/2] limb-alias-double.h: Fix missing semicolon Junxian Zhu
2023-12-25 10:35 ` [PATCH 2/2] MIPS: Hard-float rounding instructions support Junxian Zhu
2023-12-25 10:51 ` Xi Ruoyao
2023-12-26 2:37 ` Junxian Zhu
2023-12-26 8:29 ` Xi Ruoyao
2023-12-26 20:12 ` Adhemerval Zanella Netto
2023-12-26 21:50 ` Xi Ruoyao
2023-12-26 22:50 ` Xi Ruoyao
2023-12-27 13:25 ` Adhemerval Zanella Netto
2024-01-02 10:08 ` Junxian Zhu
2024-01-02 9:43 ` Junxian Zhu
2024-01-02 9:57 ` Xi Ruoyao
[not found] ` <5f0f4c83-f6d8-4af3-8cce-e12cd5314da1@oss.cipunited.com>
2024-01-31 9:08 ` Xi Ruoyao
2024-01-25 13:58 ` Junxian Zhu
2024-01-25 14:37 ` Xi Ruoyao
2023-12-25 12:36 ` YunQiang Su
2023-12-26 2:48 ` Junxian Zhu
2024-01-02 9:51 ` Junxian Zhu [this message]
2023-12-29 1:00 ` Joseph Myers
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